CN1606096A - Low power consumption static random memory with low level thread amplitude of oscillation - Google Patents
Low power consumption static random memory with low level thread amplitude of oscillation Download PDFInfo
- Publication number
- CN1606096A CN1606096A CN 200410065237 CN200410065237A CN1606096A CN 1606096 A CN1606096 A CN 1606096A CN 200410065237 CN200410065237 CN 200410065237 CN 200410065237 A CN200410065237 A CN 200410065237A CN 1606096 A CN1606096 A CN 1606096A
- Authority
- CN
- China
- Prior art keywords
- input
- circuit
- electric charge
- output
- termination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
Disclosed is a low power consumption static random memory with low level thread amplitude of oscillation, wherein the memory comprises a pre-charging circuit based on electric charge sharing, a memory unit, a line decoder, a row decoder, a selector, a read-write control circuit, a sensitive amplifier and an input processing circuit, wherein the bit line end of the pre-charging circuit is connected to the bidirectional port of the selector, the output end of the input treatment circuit is connected with the input end of the sensitive amplifier and the selector.
Description
Technical field
The present invention is a kind of design of high-performance memory, belongs to the technical field that integrated circuit is made.
Background technology
Along with improving constantly and the tight demand of electronic market of integrated circuit (IC) design technological level, high performance system level chip (SoC) arises at the historic moment.In order to improve performance, embedded a large amount of storeies among the SoC usually, its area is up to the 50%-60% of whole SoC chip area, and power consumption of memory accounts for the 25%-40% of whole SoC chip power-consumption.At flush bonding processor, RAM on common embedded Cache and the sheet, and these all are made up of SRAM (static RAM).Therefore the SRAM power problems more and more causes people's attention.
The power consumption of SRAM mainly is made up of three parts.The one, dynamic power consumption, i.e. capacitor charge and discharge institute power consumed.The 2nd, short-circuit dissipation, i.e. power supply and ground conducting time institute power consumed.The 3rd, the caused quiescent dissipation of metal-oxide-semiconductor leakage current.Dynamic power consumption accounts for the largest percentage in three kinds of power consumptions, and the SRAM neutrality line connects many memory banks unit, and its capacitive load is very big, and it is very big that bit line discharges and recharges caused dynamic power consumption, account for 80% of overall dynamic power consumption, so it is very big to whole SRAM power consumption influence to optimize the bit line dynamic power consumption.The bit line dynamic power consumption can be used formula (1) expression:
F and
Be respectively the inversion frequency and the capacitive load of bit line,
Be the bit-line voltage amplitude of oscillation,
It is supply voltage.As can be seen from the above equation under the fixing condition of inversion frequency and supply voltage, the optimization of bit line power consumption has two kinds of methods: the one, reduce bit line capacitance, this method basic thought is that bank array is cut apart, and reduces the Number of Storage Units on the bit line, thereby reduces capacitive load.The 2nd, reduce the bit-line voltage amplitude of oscillation.Because V when SRAM carries out write operation
SwingReach V
DD, and V during read operation
SwingVery little, so V
SwingResearch mainly concentrates on write cycles.V for example
DD/ 2 bit line amplitudes of oscillation, current-mode write operation, the memory bank unit design of similar sense amplifier.
But above these methods all are to improve at the storage unit bit line amplitude of oscillation of carrying out write operation, and
Do not consider to be chosen, but do not carry out the storage unit bit line amplitude of oscillation of write operation by word line.The bit line dynamic power consumption that these storage unit bit line amplitudes of oscillation are consumed also is very big.
Summary of the invention
Technical matters: in order to reduce above-mentioned unnecessary bit line dynamic power consumption, the present invention has designed a kind of power consumption static random memory with low of low level thread amplitude of oscillation, and bit line V compares
SwingReach V
DDRoutine (FVBS) SRAM, in the time, performance index such as area change under the very little condition, can make at write cycles and not choose storage unit bit line V
SwingReduce by 50%, reduced dynamic power consumption effectively.
Technical scheme: the power consumption static random memory with low of low level thread amplitude of oscillation of the present invention (LVBS SRAM) comprises pre-charge circuit, memory bank unit, row decoder, column decoder, selector switch, read-write control circuit, sense amplifier, the input processing circuit of sharing based on electric charge; Wherein, connect " bidirectional port " of selector switch respectively based on " bit line " end of the shared pre-charge circuit of electric charge, row decoder joins with " word line ", is connected to a memory bank unit respectively on every pair two adjacent " bit line ", and " word line " of memory bank unit terminates on " word line "; The column decoder output terminal connects selector switch " enable signal " end respectively: the input termination read-write of read-write control circuit, and " amplifier enable signal " in the output terminal connects sense amplifier, and " writing enable signal " in the output terminal connects input processing circuit; Input processing circuit, output terminal connect the input end of sense amplifier and selector switch respectively.In the pre-charge circuit of sharing based on electric charge, electric charge is shared the output terminal of " clock " termination phase inverter " U2 " of circuit, electric charge is shared the output terminal of " data " termination phase inverter " U3 " of circuit, and electric charge is shared " output 1, the output 2 " of circuit and held " voltage 1, the voltage 2 " end that connects bit-line pre-charge circuit " U6, U7 " respectively; The input end of the output termination phase inverter " U4 " of d type flip flop " U1 ", the output terminal of phase inverter " U4 " connect " precharging signal 2 " end of bit-line pre-charge circuit " U6, U7 " respectively; The output terminal of phase inverter " U5 " connects " precharging signal 1 " end of pre-charge circuit " U6, U7 " respectively.Electric charge is shared circuit " U0 " and is made up of the shared driving circuit of two-way electric charge, each road electric charge is shared in the driving circuit, two input termination " data, clock " signals input of d type flip flop " U00 ", the output termination two input XOR gate " U01 " of d type flip flop " U0 ", output termination two input nand gates " U02 " of two input XOR gate " U01 ", the output termination phase inverter " U09 " of two input nand gates " U02 ", the two ends of phase inverter " U09 " connect the two ends of transmission gate " U10 " respectively; Input termination " data, clock " the signal input of two input nand gates " U03 ", two input rejection gates " U04 ", the grid of the output termination PMOS transistor " U05 " of two input nand gates " U03 ", the grid of the output termination nmos pass transistor " U06 " of two input rejection gates " U04 ".
The pre-charge circuit design:
In the SRAM pre-charge circuit, adopted electric charge sharing method, electric charge is shared circuit as shown in Figure 2: share circuit as can be known by electric charge, when the clock signal is ' 0 ', the transmission gate that connects output 1, output 2 is closed, the value of data-signal no matter, electric charge share that two metal-oxide-semiconductor U05, U06 can only have one to be opened in the driving circuit.So export 1, output 2 has only one to be output as V
DD, another is output as GND.When data-signal changes after clock signal becomes ' 1 ', U05, U06 close simultaneously, and XOR gate U01 is output as ' 1 ', and transmission gate U10, U11 open.As long as output load capacitance equates that according to principle of charge conservation, the voltage of output 1, output 2 all becomes V
DD/ 2.
Share circuit according to electric charge, design SRAM low-voltage pre-charge circuit.
The output 1 of the shared circuit of electric charge is connected 64 bit-line pre-charge circuits respectively with output 2 in the SRAM low-voltage pre-charge circuit, bit-line pre-charge circuit is made up of three NMOS pipes, output 1 is respectively to link to each other with bit line by N1, N3 with output 2, clock signal is initialized as ' 0 ', the process U1 of precharging signal transparent transmission, precharging signal 1 and precharging signal 2 signals are the precharging signal negate like this.Precharging signal is ' 1 ' when carrying out read-write operation, and output 1 and output 2 are output as V
DDAnd GND.When read-write operation is finished, clock signal and precharging signal change into ' 1 ' and ' 0 ' successively.Precharging signal 1 signal change is ' 1 ' like this, and precharging signal 2 signals are because the effect of latching of U1 still remains ' 0 ', and metal-oxide-semiconductor N1, N3 still turn-off and metal-oxide-semiconductor N2 conducting at this moment.Because bit-line pre-charge circuit neutrality line 1 is connected transistor size with bit line 2 identical and length is the same, so capacitive load is identical, thereby electric charge is shared and is made two bit lines voltages equal.Simultaneously electric charge is shared the transmission gate that connects two output ports in the circuit and is opened because the output capacitance load is identical, so export 1 and output 2 be V
DD/ 2.Reach the stable back of voltage clock signal and change into ' 0 ', like this precharging signal transparent transmission pass through U1, metal-oxide-semiconductor N1, N3 open.Because output 1 and the capacitive load of output on 2 change, and make electric charge redistribute, reach finally that voltage all is lower than V on stable back bit line 1 and the bit line 2
DD/ 2.Thereby realized the low-voltage bit line.
1. bit line power consumption analysis
In the SRAM bank structure, line decoder output makes word line enable when carrying out read-write operation, selects delegation memory bank unit.Column decoder is as 2
nSelect the control signal of a Mux, select 2 simultaneously
nBit data enters the respective stored body unit.By Fig. 4 analysis as can be known, after word line is ' 1 ', per 2
nHave only selected an operation in the individual memory bank unit, all the other are 2 years old
nThough-1 memory bank cell bit line voltage also has the amplitude of oscillation, does not participate in write operation.The bit line power consumption is in this case:
For FVBS SRAM and LVBS SRAM, to make two bit lines change in voltage of the memory bank unit that participates in write operation before be V for ' 1 ' at word-line signal
DDAnd GND.Make the bit line amplitude of oscillation that participates in the memory bank unit of write operation among two kinds of SRAM all reach V like this
DDWhen word-line signal was ' 1 ', the memory bank cell bit line voltage that participates in write operation among two kinds of SRAM was identical, so the access time of write operation is also identical.Fig. 5 shows when word-line signal is ' 1 ', does not choose the memory bank unit bit-line voltage amplitude of oscillation in FVBS SRAM and LVBS SRAM respectively.
Can be similar to by formula (2) and Fig. 6 and to draw two kinds of structure SRAM bit line power consumptions and be respectively:
Therefore when carrying out write operation, under the identical condition of inversion frequency, capacitive load, n is big more, and it is many more that LVBS SRAM reduces the bit line power consumption.When n is very big, can reduce by 50% bit line power consumption nearly.
2, SNM (static noise margin) analyzes
When word line is ' 1 ', bit line links to each other with the storage inside body node, causes the memory bank element state change thereby may cause internal node voltages to change.The SNM of SRAM memory bank is defined by causing the least interference voltage Vn of state turnover.
When word line is ' 1 ', because FVBS SRAM bit-line pre-charge is to V
DD, memory bank unit ' 0 ' node voltage may raise, and causes state turnover.LVBS SRAM bit-line voltage is lower than V
DD, memory bank unit ' 1 ' node voltage may reduce, and causes state turnover.Suppose that bit-line voltage is an extreme voltage ' 0 ', obtain having the SRAM memory bank circuit diagram 7 of Vn according to above narration.
The SNM that process calculates FVBS SRAM is 0.9V, and LVBS SRAM structure SNM is 0.7V.Though SNM reduces to some extent, the LVBS SRAM memory bank node voltage amplitude of oscillation is 0.4V to the maximum, and in the scope that SNM allows, so the memory bank unit is in steady state (SS).
Beneficial effect; For low-power consumption SRAM research, all be to improve abroad, and do not consider to be chosen by word line at the storage unit bit line amplitude of oscillation of carrying out write operation, but do not carry out the storage unit bit line amplitude of oscillation of write operation.The present invention has designed a kind of low level thread amplitude of oscillation (LVBS) SRAM structure that has, and bit line V compares
SwingReach V
DDRoutine (FVBS) SRAM, in the time, performance index such as area change under the very little condition, can make at write cycles and not choose storage unit bit line V
SwingReduce by 1/2, effectively reduce dynamic power consumption.
Description of drawings
Fig. 1 shares the structural representation of circuit for electric charge.Wherein have: d type flip flop U00, two imports different
Or door U01, two input nand gate U02, U03, two input rejection gate U04, PMOS transistor U05:NMOS transistor U06, phase inverter U07, U08, U09, U12, transmission gate U10, U11.
Fig. 2 is a SRAM low-voltage pre-charge circuit synoptic diagram.Wherein have: electric charge is shared circuit U 0, d type flip flop U1, phase inverter U2, U3, U4, U5, bit-line pre-charge circuit U6, U7.
Fig. 3 is a SRAM low-voltage pre-charge circuit signal waveforms.
Fig. 4 is a SRAM bank structure synoptic diagram.Wherein have: based on the pre-charge circuit 1 that electric charge is shared, memory bank unit 2, row decoder 3, column decoder 4, selector switch 5, read-write control circuit 6, sense amplifier 7, input processing circuit 8.
Fig. 5 is the bit-line voltage amplitude of oscillation synoptic diagram that two kinds of SRAM do not choose the memory bank unit, wherein (a) FVBS SRAM voltage swing; (b) LVBS SRAM voltage swing.
Fig. 6 is a bit-line voltage amplitude of oscillation synoptic diagram.
Fig. 7 is the SRAM memory bank circuit diagram that has Vn.(a) FVBS SRAM wherein; (b) LVBS SRAM.
Embodiment
The power consumption static random memory with low of low level thread amplitude of oscillation of the present invention comprises pre-charge circuit 1, memory bank unit 2, row decoder 3, column decoder 4, selector switch 5, read-write control circuit 6, sense amplifier 7, the input processing circuit of sharing based on electric charge 8; Wherein, connect " bidirectional port " of selector switch 5 respectively based on " bit line " end of the shared pre-charge circuit 1 of electric charge, row decoder 3 joins with " word line ", be connected to a memory bank unit 2 respectively on every pair two adjacent " bit line ", " word line " of memory bank unit 2 terminates on " word line "; Column decoder 4 output terminals connect " enable signal " end of selector switch 5 respectively; The input termination read-write of read-write control circuit 6, " amplifier enable signal " in the output terminal connects sense amplifier 7, and " writing enable signal " in the output terminal connects input processing circuit 8; Input processing circuit 8, output terminal connect the input end of sense amplifier 7 and selector switch 5 respectively.In the pre-charge circuit of sharing based on electric charge 1, electric charge is shared the output terminal of " clock " termination phase inverter " U2 " of circuit U 0, electric charge is shared circuit U 0) the output terminal of " data " termination phase inverter " U3 ", " output 1, output 2 " end that electric charge is shared circuit U 0 connects " voltage 1, voltage 2 " end of bit-line pre-charge circuit U6, U7 respectively; The input end of the output termination phase inverter U4 of d type flip flop U1, the output terminal of phase inverter U4 connect " precharging signal 2 " end of bit-line pre-charge circuit U6, U7 respectively; The output terminal of phase inverter U5 connect respectively pre-charge circuit U6, U7's " precharging signal 1 " end.
Electric charge is shared circuit U 0 and is made up of the shared driving circuit of two-way electric charge, each road electric charge is shared in the driving circuit, two input termination " data, clock " signals input of d type flip flop U00, the output termination two input XOR gate U01 of d type flip flop U0, the output termination two input nand gate U02 of two input XOR gate U01, the output termination phase inverter U09 of two input nand gate U02, the two ends of phase inverter U09 connect the two ends of transmission gate U10 respectively; Input termination " data, clock " the signal input of two input nand gate U03, two input rejection gate U04, the grid of the output termination PMOS transistor U05 of two input nand gate U03, the grid of the output termination nmos pass transistor U06 of two input rejection gate U04.
FVBS SRAM and LVBS SRAM that relatively to adopt full method for customizing design capacity be the 4K byte.Two kinds of structures all adopt bank structure as shown in Figure 3.Wherein three address wires are imported as column decoder.According to formula (4) with formula (5) can be derived FVBS SRAM and LVBS SRAM bit line power consumption is respectively:
From formula (6), when formula (7) is extrapolated and carried out write operation, LVBS SRAM can save 44% bit line power consumption.Because the bit line power consumption accounts for about 80% of whole dynamic power consumption, so dynamic power consumption can be saved about 35%.
Suppose that frequency of operation is 50MHz, adopt Synopsys nanosim and the 0.25uM of Charter company model to carry out emulation, experimental result as shown in Table 1.
Table one or two kind of structure SRAM performance relatively
| Write operation | Total power consumption | Read-write operation | Total power consumption | Access time | |
| FVBS?SRAM | ??12453uW | ?13316uW | ?10866uW | ?12607uW | ?1.17ns |
| LVBS?SRAM | ??7960uW | ?8911uW | ?7635uW | ?9061uW | ?1.18ns |
From experimental result as can be seen two kinds of structure SRAM access times basic identical, this with literary composition in the analysis unanimity of relevant access time in the third part.LVBS SRAM dynamic power consumption reduces 37% than FVBS SRAM dynamic power consumption when SRAM carries out write operation, and total power consumption reduces 33%.When SRAM carried out read-write operation, LVBS SRAM dynamic power consumption reduced 3% than FVBS SRAM dynamic power consumption, and total power consumption reduces 28%.Considering has increased some extra circuit loads in the pre-charge circuit, consumed some power consumptions.Experimental result is consistent with theoretical derivation.
Claims (3)
1, a kind of power consumption static random memory with low of low level thread amplitude of oscillation is characterized in that this storer comprises pre-charge circuit (1), memory bank unit (2), row decoder (3), column decoder (4), selector switch (5), read-write control circuit (6), sense amplifier (7), the input processing circuit of sharing based on electric charge (8); Wherein, connect " bidirectional port " of selector switch (5) respectively based on " bit line " end of the shared pre-charge circuit (1) of electric charge, row decoder (3) joins with " word line ", be connected to a memory bank unit (2) respectively on every pair two adjacent " bit line ", " word line " of memory bank unit (2) terminates on " word line ": column decoder (4) output terminal connects " enable signal " end of selector switch (5) respectively; The input termination read-write of read-write control circuit (6), " amplifier enable signal " in the output terminal connects sense amplifier (7), and " the writing enable signal " in the output terminal connects input processing circuit (8); Input processing circuit (8), output terminal connect the input end of sense amplifier (7) and selector switch (5) respectively.
2, the power consumption static random memory with low of low level thread amplitude of oscillation according to claim 1, in the pre-charge circuit (1) that it is characterized in that sharing based on electric charge, electric charge is shared the output terminal of " clock " termination phase inverter " U2 " of circuit (U0), electric charge is shared the output terminal of " data " termination phase inverter " U3 " of circuit (U0), electric charge is shared circuit (U0) " output 1; output 2 " end and is met bit-line pre-charge circuit (U6 respectively, U7) " voltage 1; voltage 2 " end: the input end of the output termination phase inverter (U4) of d type flip flop (U1), the output terminal of phase inverter (U4) meets bit-line pre-charge circuit (U6 respectively, U7) " precharging signal 2 " end; The output terminal of phase inverter (U5) connects " precharging signal 1 " end of pre-charge circuit (U6, U7) respectively.
3, the power consumption static random memory with low of low level thread amplitude of oscillation according to claim 1, it is characterized in that electric charge shares circuit (U0) and share driving circuit by the two-way electric charge and form, each road electric charge is shared in the driving circuit, two input termination " data; clock " signals input of d type flip flop (U00), the output termination two input XOR gate (U01) of d type flip flop (U0), output termination two input nand gates (U02) of two input XOR gate (U01), the output termination phase inverter (U09) of two input nand gates (U02), the two ends of phase inverter (U09) connect the two ends of transmission gate (U10) respectively; Input termination " data, clock " the signal input of two input nand gates (U03), two input rejection gates (U04), the grid of the output termination PMOS transistor (U05) of two input nand gates (U03), the grid of the output termination nmos pass transistor (U06) of two input rejection gates (U04).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100652374A CN100419913C (en) | 2004-11-03 | 2004-11-03 | Low power consumption static random memory with low level thread amplitude of oscillation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100652374A CN100419913C (en) | 2004-11-03 | 2004-11-03 | Low power consumption static random memory with low level thread amplitude of oscillation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1606096A true CN1606096A (en) | 2005-04-13 |
| CN100419913C CN100419913C (en) | 2008-09-17 |
Family
ID=34764652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100652374A Active CN100419913C (en) | 2004-11-03 | 2004-11-03 | Low power consumption static random memory with low level thread amplitude of oscillation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100419913C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102171761A (en) * | 2011-04-18 | 2011-08-31 | 华为技术有限公司 | Timing processing method and circuit for synchronous static random accessible memory (SRAM) |
| CN101593553B (en) * | 2008-05-29 | 2012-04-18 | 奇景光电股份有限公司 | Device and method for controlling precharging action of static random access memory |
| CN102750972A (en) * | 2012-06-29 | 2012-10-24 | 浪潮(北京)电子信息产业有限公司 | Data memorizer and read control method thereof |
| CN103186502A (en) * | 2011-12-30 | 2013-07-03 | 世意法（北京）半导体研发有限责任公司 | Register file organization for sharing process contexts of processors |
| CN104464806A (en) * | 2014-08-27 | 2015-03-25 | 北京中电华大电子设计有限责任公司 | Sense amplifier applicable to EEPROM and FLASH |
| CN105976859A (en) * | 2016-05-20 | 2016-09-28 | 西安紫光国芯半导体有限公司 | Static random access memory with ultralow writing power consumption and control method of writing operation of static random access memory |
| CN103903646B (en) * | 2014-03-31 | 2016-11-30 | 西安紫光国芯半导体有限公司 | A kind of low two-port SRAM writing power consumption |
| CN106297875A (en) * | 2016-08-18 | 2017-01-04 | 佛山中科芯蔚科技有限公司 | The read method of a kind of SRAM and system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6128207A (en) * | 1998-11-02 | 2000-10-03 | Integrated Device Technology, Inc. | Low-power content addressable memory cell |
| US6700415B2 (en) * | 2001-06-07 | 2004-03-02 | Atmel Corporation | Sense amplifier with configurable voltage swing control |
| US6791864B2 (en) * | 2003-01-06 | 2004-09-14 | Texas Instruments Incorporated | Column voltage control for write |
| CN2751413Y (en) * | 2004-11-03 | 2006-01-11 | 东南大学 | Low power consumption static RAM |
-
2004
- 2004-11-03 CN CNB2004100652374A patent/CN100419913C/en active Active
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593553B (en) * | 2008-05-29 | 2012-04-18 | 奇景光电股份有限公司 | Device and method for controlling precharging action of static random access memory |
| CN102171761A (en) * | 2011-04-18 | 2011-08-31 | 华为技术有限公司 | Timing processing method and circuit for synchronous static random accessible memory (SRAM) |
| WO2011103824A2 (en) * | 2011-04-18 | 2011-09-01 | 华为技术有限公司 | Timing processing method and circuit for synchronous static random accessible memory (sram) |
| WO2011103824A3 (en) * | 2011-04-18 | 2012-03-22 | 华为技术有限公司 | Timing processing method and circuit for synchronous static random accessible memory (sram) |
| US8988932B2 (en) | 2011-04-18 | 2015-03-24 | Huawei Technologies Co., Ltd. | Time processing method and circuit for synchronous SRAM |
| CN102171761B (en) * | 2011-04-18 | 2013-04-17 | 华为技术有限公司 | Timing processing method and circuit for synchronous static random accessible memory (SRAM) |
| CN103186502A (en) * | 2011-12-30 | 2013-07-03 | 世意法（北京）半导体研发有限责任公司 | Register file organization for sharing process contexts of processors |
| CN103186502B (en) * | 2011-12-30 | 2016-08-10 | 世意法（北京）半导体研发有限责任公司 | For sharing the register file organization of processor process context |
| CN102750972A (en) * | 2012-06-29 | 2012-10-24 | 浪潮(北京)电子信息产业有限公司 | Data memorizer and read control method thereof |
| CN103903646B (en) * | 2014-03-31 | 2016-11-30 | 西安紫光国芯半导体有限公司 | A kind of low two-port SRAM writing power consumption |
| CN104464806A (en) * | 2014-08-27 | 2015-03-25 | 北京中电华大电子设计有限责任公司 | Sense amplifier applicable to EEPROM and FLASH |
| CN105976859A (en) * | 2016-05-20 | 2016-09-28 | 西安紫光国芯半导体有限公司 | Static random access memory with ultralow writing power consumption and control method of writing operation of static random access memory |
| CN105976859B (en) * | 2016-05-20 | 2019-05-17 | 西安紫光国芯半导体有限公司 | A kind of control method of the ultralow Static RAM write operation for writing power consumption |
| CN106297875A (en) * | 2016-08-18 | 2017-01-04 | 佛山中科芯蔚科技有限公司 | The read method of a kind of SRAM and system |
| CN106297875B (en) * | 2016-08-18 | 2019-02-05 | 佛山中科芯蔚科技有限公司 | A kind of read method and system of Static RAM |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100419913C (en) | 2008-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zhang et al. | Highly-associative caches for low-power processors | |
| US6804143B1 (en) | Write-assisted SRAM bit cell | |
| CN110414677A (en) | It is a kind of to deposit interior counting circuit suitable for connect binaryzation neural network entirely | |
| US7586771B2 (en) | Tree-style and-type match circuit device applied to content addressable memory | |
| US20030086315A1 (en) | Semiconductor memory device | |
| CN106486156B (en) | A kind of storage unit based on FinFET | |
| Choi et al. | Low cost ternary content addressable memory using adaptive matchline discharging scheme | |
| Ko et al. | Energy optimization of multi-level processor cache architectures | |
| CN1819058A (en) | Memory outputting circuit and data outputting method | |
| Zhang et al. | Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process | |
| CN100419913C (en) | Low power consumption static random memory with low level thread amplitude of oscillation | |
| CN105702281B (en) | Structure is eliminated in a kind of half selected interference of SRAM based on hierarchical bit line structure | |
| Wang et al. | A 40-nm ultra-low leakage voltage-stacked SRAM for intelligent IoT sensors | |
| CN2751413Y (en) | Low power consumption static RAM | |
| CN102394102A (en) | Close threshold power supply voltage SRAM unit with virtual address structure | |
| CN201946317U (en) | Subthreshold storage array circuit | |
| CN102034534B (en) | Sub-threshold storage array circuit | |
| CN109935260A (en) | A kind of average 7T1R element circuit using multiple multiplex strategy | |
| CN101840728A (en) | Dual-end static random access memory (SRMA) unit | |
| CN108269599A (en) | A kind of static storage cell for balancing bit line leakage current | |
| CN107393584A (en) | A kind of single-ended reading memory cell of full swing based on FinFET | |
| JPS61184794A (en) | Semiconductor memory device | |
| Srivastav et al. | Charge scavenging gate coupled hierarchical bitline scheme for ultra-low power srams in 65nm lstp cmos | |
| CN108447515A (en) | A kind of read and write abruption storage unit based on FinFET | |
| Gupta et al. | 16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |