CN103902249B - intensive data frame queue controller and control method - Google Patents
intensive data frame queue controller and control method Download PDFInfo
- Publication number
- CN103902249B CN103902249B CN201210574664.XA CN201210574664A CN103902249B CN 103902249 B CN103902249 B CN 103902249B CN 201210574664 A CN201210574664 A CN 201210574664A CN 103902249 B CN103902249 B CN 103902249B
- Authority
- CN
- China
- Prior art keywords
- frame
- address
- queue
- fifo
- dual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention relates to a kind of intensive data frame queue controller and control method, this intensive data frame queue controller comprise for order deposit all Frame first addresss FIFO, for storer store data frame length and the dual-ported memory of shared storage resources of content and the special steering logic for realizing data frame queue control and management; Special steering logic is connected with FIFO and dual-ported memory respectively.The invention provides a kind of realize Frame closely store arrangement, limited memory resources utilization factor can be improved, effectively solve the bottleneck problem of storage resources, be conducive to realizing high performance switch and communication interface on existing fpga chip basis and intensive data frame queue controller and the control method of hardware design difficulty and cost can be reduced.
Description
Technical field
The invention belongs to Computer Control Technology field, relate to a kind of intensive data frame queue controller and control method, particularly relate to a kind of intensive data frame queue controller to data frame queue management in switch and communication node and control method.
Background technology
In high-speed communication system design, in order to ensure transfer efficiency and the telecommunication service quality of system, need to need in switch, communication node to adopt a large amount of storage resources store data frames to process access rate do not mate to alleviate communication interface and upper strata.
The hardware design of communication system often adopts FPGA programming device to realize, and limits by chip technology, and FPGA internal storage resources is limited, and therefore FPGA storage resources becomes the bottleneck of restriction high-speed communication system design.
Traditional data frame storage management adopts in units of maximum data frame length, memory block is divided into isometric storage block, forms a loop buffer queue.The method is simple.Traditional data frame storage management adopts in units of maximum data frame length, and memory block is divided into isometric storage block, and storage block is started from scratch, serial number, forms a loop buffer queue.The method is simple.But in actual application, the data frame length of transmission is often less than maximum frame size.In queue, the length of each data block must be not less than the length of maximum data frame.Such as: the span of ethernet data frame is 64-1518 byte, and the length of data block can not be less than 1518 bytes, when the frame length transmitted is 64 byte, the utilization factor of this data block only has 4.2%(64/1518).Therefore, traditional data frame storage management is low to utilization ratio of storage resources, and design cost is high.
Summary of the invention
In order to solve the above-mentioned technical matters existed in background technology, the invention provides a kind of realize Frame closely store arrangement, limited memory resources utilization factor can be improved, effectively solve the bottleneck problem of storage resources, be conducive to realizing high performance switch and communication interface on existing fpga chip basis and intensive data frame queue controller and the control method of hardware design difficulty and cost can be reduced.
Technical solution of the present invention is: the invention provides a kind of intensive data frame queue controller, its special character is: described intensive data frame queue controller comprise for order deposit all Frame first addresss FIFO, for storer store data frame length and the dual-ported memory of shared storage resources of content and the special steering logic for realizing data frame queue control and management; Described special steering logic is connected with FIFO and dual-ported memory respectively.
Above-mentioned special steering logic comprises the control register group comprising queue first address QueueHeadPtr, rear of queue address QueueTailPtr, queue length QueueLength, maximum data frame length Frame_MAXLen for depositing circle queue;
According to queue first address QueueHeadPtr, rear of queue address QueueTailPtr in control register group, obtain idle storage space in dual-ported memory, the length of Frame and content are written in dual-ported memory, Frame is written to FIFO at the first address of dual-ported memory simultaneously, and adjusts the Input Control Element of rear of queue address QueueTailPtr;
And the Frame first address read in FIFO, according to Frame first address read data frame from dual-ported memory, and adjust the output control unit of queue first address QueueHeadPtr;
Described Input Control Element accesses output control unit by dual-ported memory; Described control register group is connected with FIFO and dual-ported memory respectively.
A control method for intensive data frame queue controller, its special character is: described control method comprises the following steps:
1) initialization is carried out to control register group and FIFO;
2) Frame input block is written to dual-ported memory by newly receiving Frame, and is written in FIFO by the address of Frame;
3) Frame output unit obtains Frame first address from FIFO, according to the content of the first frame of data from dual-ported memory read data frame.
Above-mentioned steps 1) specific implementation be:
1.1) queue first address and rear of queue address are set: the queue first address QueueHeadPtr in control register group, rear of queue address QueueTailPtr are set to zero respectively;
1.2) queue length is set: control register group queue length QueueLength is set according to the size of dual-ported memory;
1.3) maximum data frame length is set: according to pre-defined maximum frame length, arrange maximum data frame length Frame_MAXLen in control register group; Frame_MAXLen value is the integral multiple of 4 bytes;
1.4) FIFO is resetted: reset FIFO, empty all information deposited in FIFO.
Above-mentioned steps 1.3) in span be between 32-4096 byte.
Above-mentioned steps 2) specific implementation be:
2.1) the full state of the sky of dual-ported memory is judged: if Frame circle queue is full, then directly abandon this Frame; If not, then step 2.2 is performed);
2.2) fifo status is judged: judge that whether FIFO is full, if FIFO is full, then directly abandon this Frame; If not, then step 2.3 is performed);
2.3) Frame first address is in the memory unit calculated: described Frame first address is in the memory unit the tail address QueueTailPtr that dual-ported memory logically forms a Frame circle queue;
2.4) length of Frame and content are write in storage unit corresponding to Frame first address;
2.5) Frame first address is written in FIFO:
2.6) rear of queue address QueueTailPtr is adjusted, described QueueTailPtr is QueueTailPtr and Frame_Len sum, judge whether new territory, QueueTailPtr subsequent memory area can also deposit a maximum data frame, set up when (QueueTailPtr+Frame_MAXLen) %QueueLength is less than QueueTailPtr, represent that rear of queue address QueueTailPtr has arrived the tail end of dual-ported memory, then arranging rear of queue address QueueTailPtr is zero.
Above-mentioned steps 2.1) in dual-ported memory logically form a Frame circle queue, described Frame circle queue is judged as that full condition is: (QueueTailPtr+2*Frame_MAXLen) %QueueLength>=QueueHeadPtr.
Above-mentioned steps 3) specific implementation be:
3.1) judge the state of FIFO, if FIFO is empty, then dual-ported memory is without new Frame, directly returns; If not, then step 3.2 is performed);
3.2) read data frame first address Frame_Addr from FIFO;
3.3) according to Frame first address, before reading from the Frame first address of double port memory, nybble is as the length Frame_Len of Frame, according to the length of Frame, from the content of the Frame first address Frame_Addr+4 read data frame of double port memory;
3.4) adjust the queue first address QueueHeadPtr of circle queue, QueueHeadPtr is set to Frame_Addr.
The present invention proposes a kind of intensive data frame queue controller and control method, this intensive data frame queue controller adopts FIFO+ dual-ported memory+special steering logic, the shared memory bank of a structure chain structure, realizes supporting elongated, intensive data frame queue controller circuitry.Wherein dual-port is used for the content of storer store data frame, forms the circle queue of in logic; FIFO is used for order and deposits all Frame first addresss.Frame first address represents the offset address of this Frame in dual-ported memory.Special steering logic realizes data frame queue control and management.Special steering logic comprises control register group, Input Control Element and output control unit.Input Control Element and output control unit are respectively in dual-ported memory and the operation of FIFO two ends, when receiving Frame, the length of Frame and content are written in dual-ported memory by input control, are written in FIFO by dual-ported memory store data frame first address.Export and control to be responsible for from FIFO read data frame index information, according to length and the content of Frame first address read data frame from dual-ported memory.The control method of this intensive data frame queue controller adopts the strategies such as chain type storage and circle queue management to realize a kind of intensive data frame queue management.Intensive data frame queue controller provided by the present invention and control method are according to the physical length memory allocated space of individual data frame, realize the tight storage arrangement of Frame, improve limited memory resources utilization factor, effectively solve the bottleneck problem of storage resources, be conducive to realizing high performance switch and communication interface on existing fpga chip basis, reduce hardware design difficulty and cost, ensure that communication system has fine transmission service quality.In addition, this intensive queuing data frame queue Management Controller realizes simply, extensibility is strong, access delay is little.Hardware circuit is adopted to realize a kind of intensive data frame queue controller.Specifically, tool of the present invention has the following advantages:
Resource utilization is high: adopt chain store operating strategy, achieve Frame and closely store arrangement, improve utilization ratio of storage resources, reduces system to storage resource demands.
Transfer efficiency is high: adopt the control and management of hardware circuit data frame queue, meets the requirement of communication high-speed transfer.
Extensibility is strong: the maximum length of the storer of data frame queue controller, the maximum length of Frame are configurable, uses flexibly, has good extensibility.
Design difficulty is little: effectively improve Communication System Design scale in single-chip, and systems interconnection realizes simple, ensures that communication system has fine transmission service quality, reduces Communication System Design difficulty.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of intensive data frame queue controller provided by the present invention;
Fig. 2 is intensive data queue provided by the present invention Management Controller fundamental diagram.
Embodiment
See Fig. 1, intensive data queue controller, based on dual-ported memory and FIFO, adopts chain type management structure to carry out the close-packed arrays of Frame, realizes a kind of data frame queue management control circuit based on FPGA design.This circuit is made up of Input Control Element, output control unit, dual-ported memory, FIFO, control register group five part.
Wherein:
Dual-ported memory: for the shared storage resources of store data frame length and content.
FIFO: for store data frame first address, Frame address represents the offset address of these data in dual-ported memory.FIFO adopts a first in first out strategy to realize the sequential storage of multiple Frame address.
Control register group: comprise queue first address QueueHeadPtr, rear of queue address QueueTailPtr, queue length QueueLength, maximum data frame length Frame_MAXLen for depositing circle queue.Control the access of dual-ported memory, dual-ported memory logically forms a buffer circle.
Input Control Element: according to queue first address QueueHeadPtr, rear of queue address QueueTailPtr in control register group, obtain idle storage space in dual-ported memory, the length of Frame and content are written in dual-ported memory, Frame is written to FIFO at the first address of dual-ported memory simultaneously, and adjusts rear of queue address QueueTailPtr;
Output control unit: read the Frame first address in FIFO, according to Frame first address read data frame from dual-ported memory, and adjust queue first address QueueHeadPtr.
See Fig. 2, the present invention, while providing above-mentioned controller, additionally provides a kind of control method based on this controller, and the method is mainly divided into three steps: initialization, Frame input, Frame export.
Wherein:
1., during initialization, controller needs initialization control register group and FIFO.Dual-ported memory is formed in logic a buffer circle.Initialization detailed process is as follows.
1.1) queue first address and rear of queue address are set: the queue first address QueueHeadPtr in control register group, rear of queue address QueueTailPtr are set to zero respectively;
1.2) queue length is set: control register group queue length QueueLength is set according to dual-ported memory size;
1.3) maximum data frame length is set: pre-define maximum frame length according to user, maximum data frame length Frame_MAXLen in control register group is set; Frame_MAXLen value is the integral multiple of 4 bytes, and typical value scope is between 32-4096 byte.
1.4) reset FIFO: reset FIFO, empty all information deposited in FIFO.
2. Frame input: Frame input block is responsible for being written to dual-ported memory by newly receiving Frame, and is written in FIFO by the address of Frame, and idiographic flow is as follows:
2.1) the full state of dual-ported memory sky is judged: dual-ported memory logically forms a Frame circle queue, and Frame circle queue is judged as that full condition is: (QueueTailPtr+2*Frame_MAXLen) %QueueLength>=QueueHeadPtr.If Frame circle queue is full, then directly abandons this Frame, otherwise enter into step 2.2);
2.2) fifo status is judged: judge that whether FIFO is full, if FIFO is full, then directly abandons this Frame, otherwise enter into step 2.3);
2.3) calculate Frame first address in the memory unit: dual-ported memory logically forms a Frame circle queue, rear of queue address QueueTailPtr and new data frame are at the first address of storage unit;
2.4) Frame is written to storage unit: the length of Frame and content are write in storage unit corresponding to Frame first address;
2.5) Frame first address is written in FIFO: Frame first address is written in FIFO.
2.6) the rear of queue address of Frame circle queue is adjusted: adjustment rear of queue address QueueTailPtr, QueueTailPtr=QueueTailPtr+Frame_Len, judge whether new territory, QueueTailPtr subsequent memory area can also deposit a maximum data frame, when condition (QueueTailPtr+Frame_MAXLen) %QueueLength<QueueTailPtr sets up, represent that rear of queue address QueueTailPtr has arrived the tail end of dual-ported memory, then arranging rear of queue address QueueTailPtr is zero.
3, Frame exports: Frame output unit is responsible for from FIFO, obtain Frame first address, and according to the content of the first frame of data from dual-ported memory read data frame, idiographic flow is as follows:
3.1) judge fifo status: the state judging FIFO, if FIFO is empty, show that dual-ported memory is without new Frame, directly returns, otherwise enters into step 3.2);
3.2) Frame first address is obtained: read data frame first address Frame_Addr from FIFO;
3.3) content of read data frame: according to Frame first address, before reading from the Frame first address of double port memory, nybble is as the length Frame_Len of Frame, according to the length of Frame, from the content of the Frame first address Frame_Addr+4 read data frame of double port memory;
3.4) the queue first address of Frame circle queue is adjusted: the queue first address QueueHeadPtr of adjustment circle queue, is set to Frame_Addr by QueueHeadPtr.
Claims (7)
1. an intensive data frame queue controller, is characterized in that: described intensive data frame queue controller comprise for order deposit all Frame first addresss FIFO, for storer store data frame length and the dual-ported memory of shared storage resources of content and the special steering logic for realizing data frame queue control and management;
Described special steering logic comprises the control register group comprising queue first address QueueHeadPtr, rear of queue address QueueTailPtr, queue length QueueLength, maximum data frame length Frame_MAXLen for depositing circle queue;
According to queue first address QueueHeadPtr, rear of queue address QueueTailPtr in control register group, obtain idle storage space in dual-ported memory, the length of Frame and content are written in dual-ported memory, Frame is written to FIFO at the first address of dual-ported memory simultaneously, and adjusts the Input Control Element of rear of queue address QueueTailPtr;
And the Frame first address read in FIFO, according to Frame first address read data frame from dual-ported memory, and adjust the output control unit of queue first address QueueHeadPtr;
Described Input Control Element accesses output control unit by dual-ported memory; Described control register group is connected with FIFO and dual-ported memory respectively.
2. the control method of intensive data frame queue controller according to claim 1, is characterized in that: described control method comprises the following steps:
1) initialization is carried out to control register group and FIFO;
2) Frame input block is written to dual-ported memory by newly receiving Frame, and is written in FIFO by the address of Frame;
3) Frame output unit obtains Frame first address from FIFO, according to the content of the first frame of data from dual-ported memory read data frame.
3. control method according to claim 2, is characterized in that: described step 1) specific implementation be:
1.1) queue first address and rear of queue address are set: the queue first address QueueHeadPtr in control register group, rear of queue address QueueTailPtr are set to zero respectively;
1.2) queue length is set: control register group queue length QueueLength is set according to the size of dual-ported memory;
1.3) maximum data frame length is set: according to pre-defined maximum frame length, arrange maximum data frame length Frame_MAXLen in control register group; Frame_MAXLen value is the integral multiple of 4 bytes;
1.4) FIFO is resetted: reset FIFO, empty all information deposited in FIFO.
4. control method according to claim 3, is characterized in that: described step 1.3) in span be between 32-4096 byte.
5. the control method according to claim 3 or 4, is characterized in that: described step 2) specific implementation be:
2.1) the full state of the sky of dual-ported memory is judged: if Frame circle queue is full, then directly abandon this Frame; If not, then step 2.2 is performed);
2.2) fifo status is judged: judge that whether FIFO is full, if FIFO is full, then directly abandon this Frame; If not, then step 2.3 is performed);
2.3) Frame first address is in the memory unit calculated: described Frame first address is in the memory unit the tail address QueueTailPtr that dual-ported memory logically forms a Frame circle queue;
2.4) length of Frame and content are write in storage unit corresponding to Frame first address;
2.5) Frame first address is written in FIFO:
2.6) rear of queue address QueueTailPtr is adjusted, described QueueTailPtr is QueueTailPtr and Frame_Len sum, judge whether new territory, QueueTailPtr subsequent memory area can also deposit a maximum data frame, set up when (QueueTailPtr+Frame_MAXLen) %QueueLength is less than QueueTailPtr, represent that rear of queue address QueueTailPtr has arrived the tail end of dual-ported memory, then arranging rear of queue address QueueTailPtr is zero.
6. control method according to claim 5, it is characterized in that: described step 2.1) in dual-ported memory logically form a Frame circle queue, described Frame circle queue is judged as that full condition is: (QueueTailPtr+2*Frame_MAXLen) %QueueLength>=QueueHeadPtr.
7. control method according to claim 6, is characterized in that: described step 3) specific implementation be:
3.1) judge the state of FIFO, if FIFO is empty, then dual-ported memory is without new Frame, directly returns; If not, then step 3.2 is performed);
3.2) read data frame first address Frame_Addr from FIFO;
3.3) according to Frame first address, before reading from the Frame first address of double port memory, nybble is as the length Frame_Len of Frame, according to the length of Frame, from the content of the Frame first address Frame_Addr+4 read data frame of double port memory;
3.4) adjust the queue first address QueueHeadPtr of circle queue, QueueHeadPtr is set to Frame_Addr.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210574664.XA CN103902249B (en) | 2012-12-26 | 2012-12-26 | intensive data frame queue controller and control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210574664.XA CN103902249B (en) | 2012-12-26 | 2012-12-26 | intensive data frame queue controller and control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103902249A CN103902249A (en) | 2014-07-02 |
| CN103902249B true CN103902249B (en) | 2015-08-19 |
Family
ID=50993596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210574664.XA Active CN103902249B (en) | 2012-12-26 | 2012-12-26 | intensive data frame queue controller and control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103902249B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2507066Y (en) * | 2001-10-18 | 2002-08-21 | 深圳市中兴集成电路设计有限责任公司 | Direct memory access controller |
| CN201626437U (en) * | 2010-03-03 | 2010-11-10 | 中国铁道科学研究院机车车辆研究所 | Multifunction vehicle bus controller and multifunction vehicle bus network card |
| CN101771554B (en) * | 2008-12-31 | 2012-01-11 | 中国航空工业第一集团公司第六三一研究所 | Redundancy management circuit and management method thereof |
| CN101963896B (en) * | 2010-08-20 | 2012-11-14 | 中国科学院计算技术研究所 | Memory device with quadratic index structure and operation method thereof |
-
2012
- 2012-12-26 CN CN201210574664.XA patent/CN103902249B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2507066Y (en) * | 2001-10-18 | 2002-08-21 | 深圳市中兴集成电路设计有限责任公司 | Direct memory access controller |
| CN101771554B (en) * | 2008-12-31 | 2012-01-11 | 中国航空工业第一集团公司第六三一研究所 | Redundancy management circuit and management method thereof |
| CN201626437U (en) * | 2010-03-03 | 2010-11-10 | 中国铁道科学研究院机车车辆研究所 | Multifunction vehicle bus controller and multifunction vehicle bus network card |
| CN101963896B (en) * | 2010-08-20 | 2012-11-14 | 中国科学院计算技术研究所 | Memory device with quadratic index structure and operation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103902249A (en) | 2014-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8225026B2 (en) | Data packet access control apparatus and method thereof | |
| CN107590085B (en) | A kind of dynamic reconfigurable array data path and its control method with multi-level buffer | |
| US20060136681A1 (en) | Method and apparatus to support multiple memory banks with a memory block | |
| US11700209B2 (en) | Multi-path packet descriptor delivery scheme | |
| CN101252536A (en) | Router multi-queue data pack buffer management and output queue scheduling system | |
| CN102866980B (en) | Network communication cell used for multi-core microprocessor on-chip interconnected network | |
| CN109446132A (en) | A kind of interface bus device and data communication protocol | |
| CN102508803A (en) | Matrix transposition memory controller | |
| CN109861931A (en) | A kind of storage redundant system of high speed Ethernet exchange chip | |
| CN109215565A (en) | A kind of reception card, data storage dispatching method and LED display control program | |
| CN107038134A (en) | A kind of SRIO interface solid hard disks system and its implementation based on FPGA | |
| US10601723B2 (en) | Bandwidth matched scheduler | |
| CN106372029A (en) | Point-to-point on-chip communication module based on interruption | |
| CN103731364B (en) | X86 platform based method for achieving trillion traffic rapid packaging | |
| CN103902505A (en) | Configurable FFT processor circuit structure based on switching network | |
| CN103117962B (en) | A kind of spaceborne Shared memory switch device | |
| CN100499563C (en) | Increasing memory access efficiency for packet applications | |
| WO2023030195A1 (en) | Memory management method and apparatus, control program and controller | |
| CN103902249B (en) | intensive data frame queue controller and control method | |
| CN101789840B (en) | Pan-T crossing device and pan-T crossing method | |
| CN114936171B (en) | Storage access controller architecture | |
| CN104714832A (en) | Buffer management method used for airborne data network asynchronous data interaction area | |
| CN110413536A (en) | A kind of multiple data format high-speed parallel NandFlash storage device | |
| CN103166863A (en) | Lumped type 8 X 8 low-latency and high-bandwidth crosspoint cache queued on-chip router | |
| CN110096456A (en) | A kind of High rate and large capacity caching method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |