CN103876735A - System and method for collecting high-performance brain electrical signals - Google Patents

Abstract

The invention relates to the technical field of signal collection and analysis, in particular to a system and method for collecting high-performance brain electrical signals. The system for collecting the high-performance brain electrical signals comprises a shell and a circular board arranged in the shell. The circuit board comprises an ADS1298 analog-digital conversion chip, an Altera FPGA chip, a brain electrode, an upper computer, a preprocessing circuit, a DM9000A Ethernet interface chip, a right-leg driving electrode and an SDRAM. The brain electrode is connected with the preprocessing circuit and the preprocessing circuit is connected with the ADS1298 analog-digital conversion chip. The ADS1298 analog-digital conversion chip is connected with the Altera FPGA chip. The output end of the ADS1298 analog-digital conversion chip is connected with the right-leg driving electrode. The Altera FPGA chip is connected with the upper computer through the DM9000A Ethernet interface chip. The SDRAM is connected with the Altera FPGA chip. The system is simple in hardware structure, low in power consumption, convenient to carry, high in accuracy, safe and reliable in data transmission, short in product development period and convenient to popularize and apply.

Description

A kind of high-performance eeg signal acquisition system and acquisition method thereof

Technical field

The present invention relates to signal collection and analysis technical field, specifically relate to a kind of high-performance eeg signal acquisition system and acquisition method thereof.

Background technology

EEG signals (EEG) is a kind of typical bioelectrical signals, it is the overall reflection of cerebral cortex cranial nerve cell electrical activity, a large amount of physiology and pathological information are wherein comprised, being one of important physiological parameter of Clinical detection, is also the important means of the area researches such as Cognitive Science, brain-computer interface and Alertness.Because traditional eeg signal acquisition equipment is all huger, be not easy in good time obtaining of EEG signals, therefore study portable brain electric signal collecting device significant.

Eeg signal acquisition system mainly comprises signal amplification and conditioning, analog digital conversion, signal processing and transmission etc.Because the impedance of human body is high and it is large to change, EEG signals is very faint again, the interference of external environment condition is very large, therefore the amplification of eeg signal acquisition system and modulate circuit more complicated, conventionally to comprise prime amplification, bandpass filtering, notch filter, multistage amplification of high input impedance and high cmrr etc., cause the large power consumption of volume high.Analog-to-digital precision and speed have also determined the performance of eeg signal acquisition system, adopt the modulus conversion chip of 10, or adopt 12 AD1671 chips of the high sampling rate 1.25MBPS of ADI company, or adopt 16 mould/number conversion chips.Adopt in single-chip microcomputer, ARM and the system of DSP as control device, generally can only data acquisition and process comparatively single function, wherein the strongest with the data-handling capacity of DSP.By contrast, adopt FPGA to programme and can be configured neatly by hardware description language as main control chip, realize the parallel processing to multi-channel data, multiple functions can be realized on single-chip, designed based on FGPA and ADS1258 the evoked potentuial measuring system that is integrated with vision, audition and body sense stimulus signal source and 16 passage eeg signal acquisition functions simultaneously.The means of EEG signals transmission are take the wired mode such as pci bus, USB as main, and wireless way for transmitting speed is lower, but is easier to portable design, therefore can be for specific application.

Summary of the invention

High-performance eeg signal acquisition system and acquisition method thereof that technical problem to be solved by this invention is to provide that a kind of system hardware structure is simple, power consumption is lower, is convenient for carrying, precision is higher, data transmission security is reliable, product development cycle is short.

For solving the problems of the technologies described above, the invention provides following technical scheme: a kind of high-performance eeg signal acquisition system, comprise housing and be arranged on the circuit board in housing, described circuit board comprises ADS1298 mould/number conversion chip, AlteraFPGA chip, brain electrode, host computer, pre-process circuit, DM9000A Ethernet chip, right lower limb drive electrode and SDRAM memorizer, described brain electrode is connected with pre-process circuit, and pre-process circuit is connected with ADS1298 mould/number conversion chip; Described ADS1298 mould/number conversion chip is connected with AlteraFPGA chip, ADS1298 mould/number conversion chip output is connected with right lower limb drive electrode, AlteraFPGA chip is connected with host computer by DM9000A Ethernet chip, and SDRAM memorizer is connected with AlteraFPGA chip.

On such scheme basis, preferably, described pre-process circuit comprises resistance R 1, resistance R 2, capacitor C 1, capacitor C 2 and two diodes, and described resistance R 1 one end is connected with brain electrode outfan, and resistance R 1 other end is connected with resistance R 2 one end, capacitor C 1 one end; Described capacitor C 1 other end ground connection, resistance R 2 other ends and capacitor C 2 one end are connected with two diode cathodes, capacitor C 2 other end ground connection; Described two diodes connect back-to-back by its positive pole, and negative pole of two diodes connects positive supply, and another negative pole connects negative supply.

Preferred on such scheme basis; described right lower limb drive electrode is made up of RLD circuit and outside R3, R4, the C3 of ADS1298 mould/number conversion chip internal; wherein after R4 and C3 parallel connection at its overall front end series connection R3, R3 plays current-limiting protection effect, R4 and C3 form reverse filtering and amplifying circuit.

A kind of high-performance eeg signal acquisition system acquisition method providing according to technique scheme, comprises the following steps:

(1) power-up initializing; In this step, PWDN=1, RESET=1, time delay 1S arranges RESET pulse, waits for 18 CLK all the time;

(2) transmit operation order and configuration register; In this step, START=0, CS=0, CLK frequency division produces SCLK, and DIN writes SDATAC operational order, related register address and configuration data, SDATAC operational order successively;

(3) start to change and read translation data; In this step, START=1, DIN=0, cycle criterion DRDY state value, is to read DOUT data at 0 o'clock, starts SDRAM memorizer, deposits data in.

On such scheme basis, preferably, described operational order is divided into data operation commands and register read write order; Data operation commands comprises SDATA and RDATAC, RDATAC continuous-reading certificate, and continuous-reading, according to only writing RDATAC operational order one time, just can read translation data in the time that each DRDY becomes low level; Register read write order is divided into RREG and WREG, and RREG and WREG comprise respectively two bytes, and first byte is read-write register initial address, and second byte is read-write register number.

The beneficial effect that the present invention compared with prior art has is:

(1) the present invention utilizes the high accuracy of ADS1298 mould/number conversion chip, take AlteraFPGA chip as Master control chip, by the simulation such as notch filter, bandpass filtering part is transferred to digital side, under the prerequisite of guaranteed performance, simplifying EEG signals amplifies and the analog circuit of nursing one's health, realize the collection of the portable brain signal of telecommunication, what be connected with AlteraFPGA chip has ADS1298 mould/number conversion chip, Ethernet chip DM9000A and a SDRAM memorizer.The interface circuit of AlteraFPGA chip is exactly that the signal controlling port of these chips, reading and writing data port and address port are directly connected with the I/O of AlteraFPGA chip, distribute corresponding I/O mouth by Quartus II, can realize effective connection of interface circuit;

(2) the present invention adopts Altera Cyclone II family chip EP2C35F672 as the core of controlling and processing, 8 passages, low noise, low-power consumption, ADS1298ADS1298 mould/number conversion chip of 24 are as acquisition system core, simplify the hardware designs of system, there is low in energy consumption, portable, precision advantages of higher;

(3) the present invention adopts AlteraFPGA chip and DM9000A ethernet controller to combine, and successfully eeg signal acquisition system is connected with PC host computer, and the loss of data while having avoided directly uploading, has realized high-speed data communication to each other;

(4) system of the present invention utilize Quartus II instrument and Verilog HDL language to AlteraFPGA chip design, emulation and checking, be convenient to modification and the optimization of design, in the development and Design cycle that has greatly shortened product, therefore native system has good use value and application prospect.

In sum, system hardware structure of the present invention is simple, power consumption is lower, be convenient for carrying, precision is higher, data transmission security is reliable, product development cycle is short, be convenient to promote the use of, and efficiently solves the deficiencies in the prior art.

Accompanying drawing explanation

Fig. 1 is overall plan theory diagram of the present invention;

Fig. 2 is eeg signal acquisition system pre-process circuit circuit diagram of the present invention;

Fig. 3 is the right lower limb drive electrode of eeg signal acquisition system of the present invention circuit diagram;

Fig. 4 is FPGA internal structure functional module structure figure of the present invention;

Fig. 5 is ADS1298 mould/number conversion chip internal design frame chart in FPGA of the present invention.

Number in the figure is: 1-ADS1298 mould/number conversion chip; 2-AlteraFPGA chip; 3-brain electrode; 4-host computer; 5-pre-process circuit; 6-DM9000A is network interface chip too; The right lower limb drive electrode of 7-; 8-SDRAM memorizer.

The specific embodiment

In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.

As shown in Figure 1, a kind of high-performance eeg signal acquisition system, comprise housing and be arranged on the circuit board in housing, described circuit board comprises ADS1298 mould/number conversion chip 1, AlteraFPGA chip 2, brain electrode 3, host computer 4, pre-process circuit 5, DM9000A Ethernet chip 6, right lower limb drive electrode 7 and SDRAM memorizer 8, described brain electrode 3 is connected with ADS1298 mould/number conversion chip 1 by pre-process circuit 5, described ADS1298 mould/number conversion chip 1 joins with AlteraFPGA chip 2, described ADS1298 mould/number conversion chip 1 outfan is connected with right lower limb drive electrode 7, described AlteraFPGA chip 2 by with DM9000A too network interface chip 6 be connected with host computer 4, described AlteraFPGA chip 2 joins with SDRAM memorizer 8.

As shown in Figure 2, in the present embodiment, described pre-process circuit 5 resistance R 1, resistance R 2, capacitor C 1, capacitor C 2 and two diodes, described resistance R 1 one end is connected with brain electrode 3 outfans, resistance R 1 other end is connected with resistance R 2 one end, capacitor C 1 one end, capacitor C 1 other end ground connection; Described resistance R 2 other ends and capacitor C 2 one end are connected with two diode cathodes, capacitor C 2 other end ground connection; Described two diodes connect back-to-back by its positive pole, and negative pole of two diodes connects positive supply, and another negative pole connects negative supply.

The amplitude of the EEG signals of human body spontaneous is very little, be generally 5～100 μ V, and the amplitude of evoked brain potential signal is less, is only 2 μ V left and right.

The ADS1298 of TI is 24,8 passage difference inputs mould/number conversion chips, and maximum common mode rejection ratio can reach 115dB, and direct current input impedance 1G Ω is set at internal gain under the condition of 12 times and reference voltage VREF=2.4V, and signal resolution is:

$V_{\mathrm{LSB}}=\frac{1}{12}\frac{{\mathrm{<figure-callout\; id="2"\; label="V\; REF"\; filenames="HSA0000102598030000011.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{REF}}}{2^{23}-1}=0.0238\mathrm{\&mu;V}---\left(1\right)$

Therefore, by EEG signals, without amplifying and conditioning is directly carried out analog digital conversion and still can be satisfied the demand after simple low-pass filtering, therefore pre-process circuit designs as shown in Figure 2, its frequency response function is:

$H\left(\mathrm{j\&omega;}\right)=\frac{1}{1-{\mathrm{\&omega;}}^2{C}_1{C}_2{R}_1{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HSA0000102598030000011.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+\mathrm{j\&omega;}{C}_2{R}_2+\mathrm{j\&omega;}({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="HSA0000102598030000011.png,HSA0000102598030000031.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_2)R_1}---\left(2\right)$

Be 96.2Hz by the known 3dB cut-off frequency of formula (2), the main frequency band of EEG signals is concentrated 0.1～100Hz, and this pre-process circuit can be contained the useful information of EEG signals completely.

As shown in Figure 3; in the present embodiment, described right lower limb drive electrode 7 is made up of the RLD circuit of ADS1298 mould/number conversion chip 1 inside and outside R3, R4, C3, wherein after R4 and C3 parallel connection at its overall front end series connection R3; R3 plays current-limiting protection effect, and R4 and C3 form reverse filtering and amplifying circuit.Right lower limb drive electrode 7 is a kind of the most frequently used, the most effective methods that suppress the common mode disturbances (the particularly power frequency of 50Hz) in acquiring biological electric signals system.Due to ADS1298 mould/number conversion chip 1 inner integrated right lower limb drive electrode 7, therefore only need to configure ADS1298 mould/number conversion chip 1 inner related register, and use a small amount of electronic device in periphery, can realize this function.

In order to realize the eeg signal acquisition of high accuracy, high reliability, native system adopts Altera Cyclone II family chip EP2C35F672 as the core of controlling and processing, EP2C35 Series FPGA inside comprises 33216 logical blocks (LE), 105 M4K RAM pieces, RAM total amount reaches 483840,35 embedded multipliers, 4 phaselocked loops (PLL), available maximum I/O mouth is 475, and internal resource meets the demand of high performance eeg collection system completely.

What in native system, be connected with FPGA has ADS1298 mould/number conversion chip 1, DM9000A Ethernet chip 6 and a SDRAM memorizer 8.The interface circuit of AlteraFPGA chip 2 is exactly that the signal controlling port of these chips, reading and writing data port and address port are directly connected with the I/O of AlteraFPGA chip 2, distribute corresponding I/O mouth by Quartus II, can realize effective connection of interface circuit.

As shown in Figure 4, for the concrete function construction module block diagram of core processing control module, native system uses Verilog HDL language to write separately control module, SDRAM memorizer 8 control modules, digital filter module and the ethernet port transmission control module of A/D converter, by functional simulation with sequential emulation verify whether modules can the corresponding control function of complete independently.After being proved to be successful, final by example, in the inner core processing control module that forms an eeg signal acquisition system of AlteraFPGA chip 2.

The digital filtering module of native system is mainly 50Hz wave trap and digital band-pass filter, and both software design approach are similar, introduces the design of notch method of 50Hz here.The wave trap technical specification designing in native system is: sampling frequency fs is 1kHz, trap frequency fo is 50Hz, 3dB band side frequency is 45Hz and 55Hz, the upper and lower side frequency of stopband is 49Hz and 51Hz, stopband attenuation is not less than the realization of 40dB. for the ease of hardware, select the IIR wave trap of second order herein, its transfer function is suc as formula shown in (3):

$H\left(z\right)=\frac{1-2\cos (2\mathrm{\&pi;}{f}_o/f_s)z^{-1}+z^{-2}}{1-2k\cos (2\mathrm{\&pi;}{f}_o/f_s)z^{-1}+k^2{z}^{-2}}---\left(3\right)$

The value of k has determined notch depth, adjusts, thereby realize best trap according to concrete signal.For EEG signal, best k value need to arrange several register-stored coefficients and intermediate value according to transfer function while being 0.88.FPGA software design, and at each clock, these intermediate value displacements is upgraded, and then recalculates and obtains new output valve.

An acquisition method for high-performance eeg signal acquisition system, comprises the following steps:

(1) power-up initializing; In this step, PWDN=1, RESET=1, time delay 1S arranges RESET pulse, waits for 18 CLK all the time;

(2) transmit operation order and configuration register; In this step, START=0, CS=0, CLK frequency division produces SCLK, and DIN writes SDATAC operational order, related register address and configuration data, SDATAC operational order successively;

(3) start to change and read translation data; In this step, START=1, DIN=0, cycle criterion DRDY state value, is to read DOUT data at 0 o'clock, starts SDRAM memorizer, deposits data in.

In the present embodiment, described operational order is divided into data operation commands and register read write order, and data operation commands mainly comprises SDATA and RDATAC (continuous-reading certificate).Continuous-reading, according to only writing RDATAC operational order one time, just can read translation data in the time that each DRDY becomes low level.Register read write order is divided into RREG and these two operational orders of WREG. comprise respectively two bytes, the initial address that first byte is read-write register, second number that byte is read-write register.

Particularly, pre-process circuit 5 comprises RC low-pass filtering and overvoltage crowbar, and the signal that brain electrode 3 is collected carries out being directly sent in ADS1298 mould/number conversion chip 1 and carrying out mould/number conversion after low-pass filtering and overvoltage protection.Right lower limb drive electrode 7 is mainly for suppressing common mode disturbances, and the reverse filtering and amplifying circuit being made up of RLD circuit and the outside capacitance resistance of ADS1298 mould/number conversion chip 1 inside forms.

System adopts AlteraFPGA chip 2 as Master control chip, utilize hardware description language to write configuration I/O mouth and become general serial SPI interface, be connected and realize communication with the SPI interface of ADS1298 mould/number conversion chip 1 of high-precision multi-path, thereby the analogue signal that control ADS1298 mould/number conversion chip 1 collects brain electrode 3 is converted to digital signal, trap is stored in SDRAM memorizer 8 after processing after filtering, as the buffer portion of image data, to prepare for follow-up transport module.

Data transmission module is mainly to adopt AlteraFPGA chip 2 to configure I/O mouth as with the too control interface of network interface chip 6 of DM9000A, and with DM9000A too the control interface of network interface chip 6 connect, realize its logic control; Adopt udp protocol by the data packing of reading from SDRAM memorizer 8, by RJ45 network interface, be transferred to host computer 4.The sample rate of 8 passage 1kHz, needs the transfer rate of 192Kb/s in theory, and the transfer rate of Ethernet interface 10/100M can be satisfied the demand completely.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.

Claims (5)

1. a high-performance eeg signal acquisition system, comprise housing and be arranged on the circuit board in housing, it is characterized in that: described circuit board comprises ADS1298 mould/number conversion chip (1), AlteraFPGA chip (2), brain electrode (3), host computer (4), pre-process circuit (5), DM9000A Ethernet chip (6), right lower limb drive electrode (7) and SDRAM memorizer (8), described brain electrode (3) is connected with pre-process circuit (5), pre-process circuit (5) is connected with ADS1298 mould/number conversion chip (1), described ADS1298 mould/number conversion chip (1) is connected with AlteraFPGA chip (2), ADS1298 mould/number conversion chip (1) outfan is connected with right lower limb drive electrode (7), AlteraFPGA chip (2) is connected with host computer (4) by DM9000A Ethernet chip (6), and SDRAM memorizer (8) is connected with AlteraFPGA chip (2).

2. according to a kind of high-performance eeg signal acquisition system described in claims 1, it is characterized in that: described pre-process circuit (5) comprises resistance R 1, resistance R 2, capacitor C 1, capacitor C 2 and two diodes, described resistance R 1 one end is connected with brain electrode (3) outfan, and resistance R 1 other end is connected with resistance R 2 one end, capacitor C 1 one end; Described capacitor C 1 other end ground connection, resistance R 2 other ends and capacitor C 2 one end are connected with two diode cathodes, capacitor C 2 other end ground connection; Described two diodes connect back-to-back by its positive pole, and negative pole of two diodes connects positive supply, and another negative pole connects negative supply.

3. according to a kind of high-performance eeg signal acquisition system described in claims 2; it is characterized in that: described right lower limb drive electrode (7) is made up of the inner RLD circuit of ADS1298 mould/number conversion chip (1) and outside R3, R4, C3; wherein after R4 and C3 parallel connection at its overall front end series connection R3; R3 plays current-limiting protection effect, and R4 and C3 form reverse filtering and amplifying circuit.

4. according to the acquisition method of a kind of high-performance eeg signal acquisition system described in claims 1 or 2 or 3, it is characterized in that: mainly comprise the following steps:

(1) power-up initializing; In this step, PWDN=1, RESET=1, time delay 1S arranges RESET pulse, waits for 18 CLK all the time;

(2) transmit operation order and configuration register; In this step, START=0, CS=0, CLK frequency division produces SCLK, and DIN writes SDATAC operational order, related register address and configuration data, SDATAC operational order successively;

(3) start to change and read translation data; In this step, START=1, DIN=0, cycle criterion DRDY state value, is to read DOUT data at 0 o'clock, starts SDRAM memorizer, deposits data in.

5. according to the acquisition method of a kind of high-performance eeg signal acquisition system described in claims 4, it is characterized in that: described operational order is divided into data operation commands and register read write order; Data operation commands comprises SDATA and RDATAC, RDATAC continuous-reading certificate; Register read write order is divided into RREG and WREG, and RREG and WREG comprise respectively two bytes, and first byte is read-write register initial address, and second byte is read-write register number.

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