CN103873036A - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN103873036A CN103873036A CN201210546554.2A CN201210546554A CN103873036A CN 103873036 A CN103873036 A CN 103873036A CN 201210546554 A CN201210546554 A CN 201210546554A CN 103873036 A CN103873036 A CN 103873036A
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- switch
- power supply
- node
- capacitor
- supply node
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Abstract
The invention discloses a power-on reset circuit, which comprises a first impedance device, a first switch, a first capacitor, a second switch, a third switch, a fourth switch, a second impedance device, a second capacitor and a control circuit coupled at a reset input end of a circuit device. When the power-on reset circuit supplies power, the first and third switches are switched on, the second and fourth switches are not switched on, and when the power charges the second capacitor to a set level through the second impedance device, the control circuit outputs a reset signal; when the power of the power-on reset circuit is removed, the first and third switches are not switched on, the second and fourth switches are switched on, the second capacitor is discharged to a voltage level close to a ground reference point through the fourth switch. The quiescent current is zero when the power-on reset circuit is connected with a power supply next time, and the control circuit in the power-on reset circuit can output a correct control signal.
Description
Technical field
The present invention has about electrify restoration circuit, is particularly to send the electrify restoration circuit of a set reset signal.
Background technology
In the time of power supply initial start, the voltage that power supply produces cannot reach a predeterminated voltage value immediately.If for a digital circuit, by causing, the initial state of this digital circuit is not clear by this voltage that does not reach predeterminated voltage value.Generally speaking, electrify restoration circuit is incorporated in very lagre scale integrated circuit (VLSIC) (VLSI), is used for producing a reset signal.In the time of power supply initial start, the internal circuit of VLSI can obtain a known initial state according to this reset signal.
Fig. 1 shows the schematic diagram that electrify restoration circuit is applied to circuit arrangement.In Fig. 1, in the time that circuit arrangement 150 powers on, the power supply node VDD that electrify restoration circuit 100 couples can from zero potential climb to set value, this power supply node VDD can be by a resistor P who is made up of PMO S transistor
1to a capacitor C
pcharging.One control circuit 130 can be according to this capacitor C
pon voltage produce a reset signal give this circuit arrangement 150.The power supply of this power supply node VDD is supplied with while being removed, this capacitor C
pcan be by this resistor P
1and to this power supply node VDD (now the current potential of power supply node VDD approaches with reference to ground connection) electric discharge.But, this resistor P being formed by PMOS transistor
1, in the short time, can only operate and make this capacitor C
pvoltage be discharged to the conducting voltage of P-N junction, cannot make this capacitor C
pelectric discharge completely.This capacitor C
pvoltage cannot be discharged to and equate with reference to ground connection GND.Therefore, when this circuit arrangement 150 (upper circuit reset circuit 100) is upper while once connecting with the mains, this capacitor C
pon the voltage that has been pre-existing in can make this control circuit 130 produce wrong control signal, or this electrify restoration circuit 100 cannot be worked.
Therefore have a new electrify restoration circuit need to be provided.In discharge process, the voltage of the electric capacity of this electrify restoration circuit can be discharged to this earthed voltage and equate.Therefore,, in the time that this electrify restoration circuit is connected with the mains next time, the control circuit in this electrify restoration circuit can export correct control signal or this electrify restoration circuit can be worked.
Summary of the invention
A kind of electrify restoration circuit that the present invention discloses, comprising: one first impedance means and one first switch, be coupled between a power supply node and a first node after series winding each other; Wherein, a control end of this first switch couples this power supply node; One first capacitor, is coupled to this first node and with reference between ground connection; One second switch, be coupled between this first node and a connected node, and the control end of this second switch couples this power supply node; One the 3rd switch, be coupled to this connected node and this with reference between ground connection, and the control end of the 3rd switch couples this power supply node; One the 4th switch, be coupled to a Section Point and this with reference between ground connection, and the control end of the 4th switch is coupled to this connected node; One second impedance means, is coupled between this power supply node and this Section Point; One second capacitor, is coupled to this Section Point and this is with reference between ground connection; And a control circuit, couple between this Section Point and the replacement input of a circuit arrangement.
Wherein, in the time having electric power to supply with on this power supply node, this first and the 3rd switch conduction, this is second and the 4th not conducting of switch years old, when electric power on this power supply node charges the set current potential of this second capacitor to by this second impedance means, make this control circuit export a reset signal.When this electric power is supplied with in the time that this power supply node removes, this first and the 3rd not conducting of switch, this second and the 4th switch conduction, make this second discharging capacitors to approaching this voltage level with reference to ground connection by the 4th switch.
While the invention enables this electrify restoration circuit to connect with the mains, quiescent current is zero next time, and then control circuit in this electrify restoration circuit can be exported correct control signal.
Brief description of the drawings
Fig. 1 shows the schematic diagram that electrify restoration circuit is applied to circuit arrangement.
Fig. 2 A shows according to the schematic diagram that is applied to the electrify restoration circuit on circuit arrangement described in one embodiment of the invention.
Fig. 2 B shows the schematic diagram that the power supply node of Fig. 2 A has electric power to supply with.
Fig. 2 C shows that the power supply node of Fig. 2 B removes the schematic diagram that electric power is supplied with.
Fig. 3 shows according to the schematic diagram that is applied to the electrify restoration circuit on circuit arrangement described in one embodiment of the invention.
Being simply described as follows of symbol in accompanying drawing:
GND: with reference to ground connection
VDD: power supply node (voltage)
P
1: PMOS transistor
C
p: capacitor
130: control circuit
150: circuit arrangement
100: electrify restoration circuit
R
1: the first impedance means
R
2: the second impedance means
SW
1: the first switch
SW
2: second switch
SW
3: the 3rd switch
SW
4: the 4th switch
C
1: the first capacitor
C
2: the second capacitor
200: electrify restoration circuit
300: electrify restoration circuit
230: control circuit
250: circuit arrangement
T
1～T
4: first-, tetra-control ends
N
p: power supply node
N
1: first node
N
2: Section Point
N
c: connected node
IN
1: replacement input
MP
1～MP
3: the first～three PMOS transistor
MN
1～MN
3: the first～three nmos pass transistor.
Specific embodiment
Manufacture and the using method of various embodiments of the invention will be discussed in detail below.But it should be noted that many feasible inventive concepts provided by the present invention may be implemented in various particular ranges.These specific embodiments are only for illustrating manufacture of the present invention and using method, but non-for limiting scope of the present invention.
Fig. 2 A shows according to the schematic diagram of the electrify restoration circuit that is applied to circuit arrangement described in one embodiment of the invention.One electrify restoration circuit 200 comprises: one first impedance means R
1, one second impedance means R
2, one first switch SW
1, a second switch SW
2, one the 3rd switch SW
3, one the 4th switch SW
4, one first capacitor C
1, one second capacitor C
2, a control circuit 230.
This first impedance means R
1with this first switch SW
1contact each other and be coupled to a power supply node N
pan and first node N
1between; And, this first switch SW
1a control end T
1couple this power supply node N
p.This first capacitor C
1be coupled to this first node N
1and one with reference between ground connection GND.This second switch SW
2be coupled to this first node N
1with a connected node N
cbetween and this second switch SW
2control end T
2couple this power supply node N
p.One the 3rd switch SW
3be coupled to this connected node N
cand this is with reference between ground connection GND and the 3rd switch SW
3control end T
3couple this power supply node N
p.The 4th switch SW
4be coupled to a Section Point N
2and this is with reference between ground connection GND and the 4th switch SW
4control end T
4be coupled to this connected node N
c.This second impedance means R
2be coupled to this power supply node N
pwith this Section Point N
2between.This second capacitor C
2be coupled to this Section Point N
2and this is with reference between ground connection GND.This control circuit 230 couples this Section Point N
2replacement input IN with a circuit arrangement 250
1between.
Fig. 2 B shows the schematic diagram that the power supply node of Fig. 2 A has electric power to supply with.As this power supply node N
pon have electric power supply with (power supply node N
pon there will be voltage VDD) time, this first switch SW
1conducting.This power supply node N
pon electric power (voltage VDD) by this first impedance means R
1to this first capacitor C
1charging.Now, this power supply node N
pon this second switch of electric power control SW
2not conducting and the 3rd switch SW
3conducting.Due to the 3rd switch SW
3conducting, makes this connected node N
ccurrent potential close to reference to ground connection GND; Therefore the 4th switch SW
4not conducting.This power supply node N
pon electric power by this second impedance means R
2this second capacitor C charges
2to a set current potential.This control circuit 230 is exported this replacement input IN of a reset signal to this circuit arrangement 250 according to this set current potential
1.
Fig. 2 C shows that the power supply node of Fig. 2 B removes the schematic diagram that electric power is supplied with.When electric power is supplied with (voltage VDD) this power supply node N certainly
p(power supply node N while removing
pfor example to be couple to reference to ground connection GND), this first switch SW
1not conducting and the 3rd switch SW
3not conducting, and this second switch SW
2conducting.This first capacitor C
1voltage by this second switch SW of conducting
2pass to the 4th switch SW
4control end T
4, make the 4th switch SW
4conducting.This second capacitor C
2by the 4th switch SW
4be discharged to and approach this voltage level with reference to ground connection GND.
In addition, when electric power is supplied with from this power supply node N
pwhile removing, this electrify restoration circuit 200 operates required voltage only need be by this first capacitor C
1institute provides, and therefore there is no the electric current that additional power produces and flows into this electrify restoration circuit 200, therefore quiescent current is zero.
Fig. 3 shows according to the schematic diagram that is applied to the electrify restoration circuit 300 on circuit arrangement described in one embodiment of the invention.The circuit framework of Fig. 3 is identical with Fig. 2 A those shown, and difference is only that Fig. 3 further discloses more detailed circuit implementation detail.As shown in Figure 3, this first switch SW of Fig. 2 A
1, the 3rd switch SW
3and the 4th switch SW
4can be respectively by nmos pass transistor MN
1, MN
2, MN
3institute forms; And this second switch SW
2can be by PMOS transistor MP
2institute forms.Again as shown in Figure 3, this first impedance means R of Fig. 2 A
1with this second impedance means R
2can be respectively by PMOS transistor MP
1and MP
3institute forms, wherein this PMOS transistor MP
1and MP
2grid and drain electrode be connected to each other.Should be noted the first impedance means R in the present embodiment
1with this second impedance means R
2respectively by PMOS transistor MP
1and MP
3institute forms, but this kind of circuit topography is only the use of demonstration, but not is used for limiting circuit structure of the present invention.Due to this second switch SW
2and the 3rd switch SW
3respectively by PMOS transistor MP
2with nmos pass transistor MN
2institute forms, therefore at power supply node N
pwhile powering on, this second switch SW
2and the 3rd switch SW
3be respectively and close and conducting; At power supply node N
pwhile not powering on, this second switch SW
2and the 3rd switch SW
3be respectively conducting and close.The action of circuit shown in Fig. 3, narrated in above-mentioned Fig. 2 A ~ Fig. 2 C, was no longer repeated at this.
Because of this second capacitor C
2be discharged to and approached this voltage level with reference to ground connection GND, so this power supply node N of this electrify restoration circuit 300 next time
pon have electric power supply with time, can correctly operate and export a reset signal.
The foregoing is only preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; anyone familiar with this technology; without departing from the spirit and scope of the present invention; can do on this basis further improvement and variation, therefore protection scope of the present invention is when being as the criterion with the application's the scope that claims were defined.
Claims (3)
1. an electrify restoration circuit, is characterized in that, comprising:
One first impedance means and one first switch, be coupled between a power supply node and a first node after series winding each other; Wherein, a control end of this first switch couples this power supply node;
One first capacitor, is coupled to this first node and with reference between ground connection;
One second switch, be coupled between this first node and a connected node, and the control end of this second switch couples this power supply node;
One the 3rd switch, be coupled to this connected node and this with reference between ground connection, and the control end of the 3rd switch couples this power supply node;
One the 4th switch, be coupled to a Section Point and this with reference between ground connection, and the control end of the 4th switch is coupled to this connected node;
One second impedance means, is coupled between this power supply node and this Section Point;
One second capacitor, is coupled to this Section Point and this is with reference between ground connection; And
One control circuit, couples between this Section Point and the replacement input of a circuit arrangement;
Wherein, in the time having electric power to supply with on this power supply node, this first switch and the 3rd switch conduction, this second switch and the 4th not conducting of switch, when electric power on this power supply node charges the set current potential of this second capacitor to by this second impedance means, make this control circuit export a reset signal;
When this electric power is supplied with in the time that this power supply node removes, this first switch and the 3rd not conducting of switch, this second switch and the 4th switch conduction, make this second discharging capacitors to approaching this voltage level with reference to ground connection by the 4th switch.
2. electrify restoration circuit according to claim 1, is characterized in that, in the time having electric power to supply with on this power supply node, this electric power is supplied with this first capacitor charging; Supply with in the time that this power supply node removes when this electric power, the voltage of this first capacitor is supplied to the control end of the 4th switch by this second switch, make the 4th switch conduction.
3. electrify restoration circuit according to claim 2, is characterized in that, this first switch, the 3rd switch and the 4th switch are nmos pass transistor, and this second switch is PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210546554.2A CN103873036B (en) | 2012-12-14 | 2012-12-14 | Power-on reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210546554.2A CN103873036B (en) | 2012-12-14 | 2012-12-14 | Power-on reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103873036A true CN103873036A (en) | 2014-06-18 |
| CN103873036B CN103873036B (en) | 2017-02-22 |
Family
ID=50911224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210546554.2A Expired - Fee Related CN103873036B (en) | 2012-12-14 | 2012-12-14 | Power-on reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103873036B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108023580A (en) * | 2016-10-28 | 2018-05-11 | 拉碧斯半导体株式会社 | The generation method of semiconductor device and power-on reset signal |
| CN109412130A (en) * | 2017-08-15 | 2019-03-01 | 平高集团有限公司 | A kind of mechanical dc circuit breaker and its charge circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093998A (en) * | 2007-08-15 | 2007-12-26 | 威盛电子股份有限公司 | Decoding method and device |
| US20080048743A1 (en) * | 2006-07-28 | 2008-02-28 | Stmicroelectronics S.R.L. | Power on reset circuit for a digital device including an on-chip voltage down converter |
| US20120305814A1 (en) * | 2011-05-31 | 2012-12-06 | Hon Hai Precision Industry Co., Ltd. | Reset circuit for electronic devices |
-
2012
- 2012-12-14 CN CN201210546554.2A patent/CN103873036B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080048743A1 (en) * | 2006-07-28 | 2008-02-28 | Stmicroelectronics S.R.L. | Power on reset circuit for a digital device including an on-chip voltage down converter |
| CN101093998A (en) * | 2007-08-15 | 2007-12-26 | 威盛电子股份有限公司 | Decoding method and device |
| US20120305814A1 (en) * | 2011-05-31 | 2012-12-06 | Hon Hai Precision Industry Co., Ltd. | Reset circuit for electronic devices |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108023580A (en) * | 2016-10-28 | 2018-05-11 | 拉碧斯半导体株式会社 | The generation method of semiconductor device and power-on reset signal |
| CN108023580B (en) * | 2016-10-28 | 2023-12-22 | 拉碧斯半导体株式会社 | Semiconductor device and method for generating power-on reset signal |
| CN109412130A (en) * | 2017-08-15 | 2019-03-01 | 平高集团有限公司 | A kind of mechanical dc circuit breaker and its charge circuit |
| CN109412130B (en) * | 2017-08-15 | 2021-12-17 | 平高集团有限公司 | Mechanical direct current breaker and charging circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103873036B (en) | 2017-02-22 |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170222 Termination date: 20201214 |