CN103872140A - Planar ring gate transistor based on nanowire and preparation method thereof - Google Patents
Planar ring gate transistor based on nanowire and preparation method thereof Download PDFInfo
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- 239000002070 nanowire Substances 0.000 title claims abstract description 93
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims abstract description 5
- 238000010894 electron beam technology Methods 0.000 claims description 13
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 12
- 238000011161 development Methods 0.000 claims description 7
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 7
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 235000019157 thiamine Nutrition 0.000 claims description 4
- 150000003544 thiamines Chemical class 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000002389 environmental scanning electron microscopy Methods 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims description 2
- 230000004807 localization Effects 0.000 claims description 2
- 238000002207 thermal evaporation Methods 0.000 claims description 2
- 238000005275 alloying Methods 0.000 abstract 1
- 238000000231 atomic layer deposition Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- BFNBIHQBYMNNAN-UHFFFAOYSA-N ammonium sulfate Chemical compound N.N.OS(O)(=O)=O BFNBIHQBYMNNAN-UHFFFAOYSA-N 0.000 description 2
- 229910052921 ammonium sulfate Inorganic materials 0.000 description 2
- 235000011130 ammonium sulphate Nutrition 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000008236 heating water Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000006250 one-dimensional material Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a planar ring gate transistor based on a nanowire and a preparation method thereof. The planar ring gate transistor based on the nanowire has the structure that the material of a conducting channel is a low-resistance nanowire parallel with a substrate; gate medium and a gate electrode successively surround the low-resistance nanowire along the radial direction of the nanowire; a source and drain electrode has a certain gap with the gate medium and the gate electrode on the side wall of the nanowire; the low-resistance nanowire is surrounded by the source and drain electrode. The invention also discloses the preparation method for the planar ring gate transistor. The preparation method for the planar ring gate transistor comprises the following steps: firstly, preparing the gate electrode; then, preparing the source and drain electrode; forming a gate electrode window; growing a gate medium layer and an evaporation gate electrode with an atomic layer deposition method; plating a metal film to form the source and drain electrode; obtaining the low-resistance contact resistance by the heavy doping of an intrinsic or low-doping nanowire or the alloying with metal. According to the transistor structure and the preparation method, a device with a short channel can be prepared, stray capacitance can be effectively reduced, and the regulation and control capability of the grid on the channel is enhanced so as to improve the performance of the device.
Description
Technical field
The invention belongs to nanoelectronics technical field, be specifically related to a kind of planar rings gate transistor based on nano wire and preparation method thereof.
Background technology
Along with the development of semi-conductor industry, the size of single metal-oxide-semiconductor is more and more less, and size is dwindled and can be with the problem of serving, and is exactly wherein short-channel effect more significantly.For the ability of regulation and control of reinforcing grid is to suppress short-channel effect, people propose multiple gate design scheme, from double grid to Fin grid.In all grid structures, gate-all-around structure can the most effectively improve the ability of grid regulation and control in theory, suppresses short-channel effect.Than conventional blocks material, the one-dimensional materials such as nano wire have the inherent advantage that is easy to prepare gate-all-around structure.
A very important index of characterize semiconductor material electric property is carrier mobility, and for current main-stream silicon technology, the electric property of the silicon adopting is not optimum, its mobility is lower, and the carrier mobility of III-V family material, especially electron mobility are far above silicon, in the development of following semi-conductor industry, particularly in radio frequency electric devices field, the very possible substituted for silicon material of III-V family material.
At present both at home and abroad there are a lot of seminar to possess to grow the ability of III-V family nano wire on silicon substrate: the people such as the Lars Samuelson of Lund university of Sweden are at Journal of Crystal Growth334 (2011) 51 – 56, in the article that is entitled as " Self-seeded; position-controlled InAs nanowire growth on Si:A growth parameter study " of delivering, announce the achievement of the method growth InAs nanometer line ordered array that adopts self-catalysis on silicon substrate; The people such as the Takashi Fukui of Hokkaido, Japan university are at Nature488 (2012) 189, deliver the article that is entitled as " A III – V nanowire channel on silicon for high-performance vertical transistors ", also possessed the ability of the III-V family nano wire cyclic array of growing on silicon substrate.
From the electric property of material and current progress, III-V family nano wire is probably further applied in radio frequency electric devices field.The work of the planar rings grid radio-frequency devices based on III-V family nano wire at present comes from Lund university of Sweden, and (its work is published in Nano Lett., is entitled as " Realizing Lateral Wrap-Gated Nanowire FETs:Controlling Gate Length with Chemistry Rather than Lithography ".) and Japanese NTT company (its work is published in APL and is entitled as Encapsulated gate-all-around InAs nanowire field-effect transistors), but the former technique is comparatively complicated, larger to sample damage, and bottom gate thin film is first carried out in the latter's employing, then shift nano wire, finally wrap again layer of metal, form ring grid, the metal that wraps up nano wire plates at twice, and middle like this meeting forms a fixed gap, thereby can not fine parcel nano wire.
Summary of the invention
The object of the invention is to prepare and can suppress more fast, better the planar rings gate transistor based on nano wire short-channel effect, that improve grid-control ability.
To achieve these goals, the present invention is by the following technical solutions:
A kind of planar rings gate transistor based on nano wire comprises: substrate, suspend and be parallel to the nano wire of substrate and be positioned on substrate and radially surround the source electrode, gate electrode and the drain electrode that are arranged in order of described nano wire;
The nano wire that described transistorized conducting channel is radially surrounded by gate electrode, has gate medium between described gate electrode and described nano wire;
Described source electrode and drain electrode have spacing with gate electrode respectively, between described source electrode and gate medium, gate electrode and between drain electrode and gate medium, gate electrode, connect without electricity in nanowire sidewalls.
Preferably, the above-mentioned planar rings gate transistor based on nano wire, its substrate is monocrystalline silicon or the monocrystalline silicon that is coated with silica.
Preferably, described nano wire is autodoping low-resistance nano wire, and its material is III-V family material.
Preferably, described gate medium is high dielectric constant material.
Preferably, source electrode, gate electrode and the very metal electrode that leaks electricity.Wherein, described source electrode and drain electrode metal require to form with nano wire the metal of ohmic contact, comprise gold, aluminium, nickel etc.
The above-mentioned planar rings gate transistor preparation method based on nano wire, comprises the steps:
1) first get rid of one deck glue at substrate, then on the even substrate of crossing glue, shift nano wire, and locate nano wire; Get rid of again one deck glue, nano wire is mingled with in the middle of two-layer glue;
2) output gate electrode window and gate electrode window is gone to cull processing, then eroding the native oxide layer on the nano wire under gate electrode window;
3) gate medium of growing on the nano wire under gate electrode window; Prepare gate electrode, then peel off;
4) output source electrode window through ray and drain electrode window, and source electrode window through ray and drain electrode window are gone to cull processing, then erode the native oxide layer on the nano wire under source electrode window through ray and drain electrode window;
5) prepare source electrode and drain electrode, then peel off.
Preferably, the glue described in step 1) is PMMA(polymethyl methacrylate), described nano wire is the autodoping of introducing in the process of grow nanowire carrying out.
Preferably, in step 1), described substrate is markd substrate, and localization method is for using ESEM to locate on markd substrate.
Preferably, step 2) in, by location, exposure and development, fixing, define gate electrode area, exposure method is electron beam exposure, and the method for removing cull is that oxygen plasma removes cull, uses thiamines solution or the mixed acid solution of HCL and IPA corrodes.
Preferably, in step 3), the method for growth gate medium is ald; The preparation method of gate electrode is magnetron sputtering plating, uses acetone to peel off.
Preferably, use the method peeled off of acetone to be: bubble is in the acetone of 60 degrees Celsius of heating water baths 1 hour, and then dropper suck acetone and blow several times.
Preferably, in step 4), by even glue, exposure and development, fixing, define electrode district, source and drain regions, exposure method is electron beam exposure, and the method for removing cull is that oxygen plasma removes cull, uses thiamines solution or the mixed acid solution of HCL and IPA corrodes.
Preferably, in step 5), the preparation method of source electrode and drain electrode is thermal evaporation plated film, electron beam plated film or sputter.
Beneficial effect:
Planar rings gate transistor based on nano wire of the present invention, nano wire is low-resistance nano wire, can reduce largely the dead resistance between gate electrode and source electrode and drain electrode; The width of gate electrode determines by there being exposure to define window, therefore can realize short gate device, thereby improve the mutual conductance of device, the operating rate of boost device; And then gate electrode and gate medium complete outputing after gate electrode window, and therefore gate electrode is self aligned; And gate electrode radially wraps up along nano wire, compare existing other grid structure and there is stronger grid ability of regulation and control, thereby can effectively suppress short-channel effect.
Brief description of the drawings
Fig. 1 is domain (overlooking) schematic diagram of the planar rings gate transistor based on nano wire in the embodiment of the present invention.In figure, 101-low-resistance nano wire; 102-nano wire native oxide layer; The oxide layer of 103-growth; 104-gate electrode; 105-drain electrode; 106-source electricity level.
Fig. 2 be in the embodiment of the present invention planar rings gate transistor based on nano wire along the cross-sectional view of A-A ' direction in Fig. 1.In figure, 201-substrate; 202-nano wire; 203-native oxide layer; 204-drain electrode; 205-source electrode; 206-gate medium; 207-gate electrode.
Fig. 3 (a) to Fig. 3 (l) be the cross-sectional view that in the embodiment of the present invention, device forms in each step.301-substrate in figure; 302-nano wire; 303-native oxide layer; 304-drain electrode; 305-source electrode; 306-gate medium; 307-gate electrode; 308-electron beam resist.
Fig. 4 (a) is that the probe station of a device in the embodiment of the present invention is measured transfer characteristic curve.
Fig. 4 (b) is for changing into the situation measurement result under semilog coordinate.
Embodiment
Below in conjunction with accompanying drawing, taking the planar rings gate transistor based on InAs nano wire, as embodiment, the invention will be further described.
Fig. 1 is domain (overlooking) schematic diagram of the planar rings gate transistor based on nano wire in the embodiment of the present invention, and wherein 101 is low-resistance nano wire, and 102 is the outer native oxide layer surrounding of nano wire, and 103 is the HfO with the growth of ALD method
2, 104 is gate electrode, and 105 is drain electrode, and 106 is source electrode.
Fig. 2 is the generalized section along A-A ' direction in Fig. 1.Substrate 201 has the monocrystalline silicon of one deck silica for surface coverage; More than 201 part of substrate from left to right comprises respectively source electrode 205, gate electrode 207 and drain electrode 204; Transistorized conducting channel is surrounded to suspend by gate electrode 207 and is parallel to the nano wire 202 of substrate 201, and not besieged nano wire 202 skins are native oxide layer 203; Between gate electrode 207 and nano wire 202, have gate medium 206, gate electrode 207 and gate medium 206 surround nano wire 202 and make nano wire 202 separate with substrate 201 and suspend; Source electrode 205 and drain electrode 204 wrap up nano wire 202 and are at regular intervals with gate electrode 207 and gate medium 206.
The above-mentioned planar rings gate transistor preparation method based on nano wire is as follows:
1) utilize sol evenning machine being covered with the thick SiO of 200nm
2monocrystalline silicon on to get rid of one deck PMMA A2(whirl coating speed be 1500 revs/min, 60 seconds time), about 100 nanometers of thickness, as shown in Fig. 3 (a), in figure, 301 is substrate, 308 is electron beam resist.
2) nano wire (being provided by Chinese Academy of Sciences's semiconductor) is transferred on the even substrate of crossing one deck PMMA, as shown in Fig. 3 (b), in figure, 302 for naturally introducing the InAs nano wire of doping, and 303 is the outer field native oxide layer of nano wire.Wherein substrate is markd substrate, and its preparation process adopts a series of micro-nano electronic technology to complete, and first adopts photoetching technique to expose needed marker graphic, and then developing fixing, then carry out plated film with electron beam plated film instrument is peeled off etc. and to be prepared mark.
3) getting rid of one deck PMMA A4(whirl coating speed is 4000 revs/min again, 60 seconds time), about 200 nanometers of thickness, as shown in Figure 3 (c).
4) output gate window, as shown in Fig. 3 (d), concrete technical process is: draw domain and define gate electrode region (about 1 micron of gate electrode width); Electron beam exposure; Develop and photographic fixing;
5) oxide of the low-doped nanowire surface of removal intrinsic-OR, optionally removal method has ammonium sulfate solution or the corrosion of other acid solutions.
6) growth gate medium 306, adopt ald (ALD) method growth gate medium, thickness is 12 nanometers, and optional gate medium has hafnium oxide, zirconia, aluminium oxide and other to have the dielectric material that is greater than 6 with respect to the permittivity magnitude of vacuum.As shown in Fig. 3 (e), in figure, 306 is gate medium.
7) prepare gate electrode 307: after growth gate dielectric layer, directly carry out plated film with magnetron sputtering plating instrument, thickness is approximately 10nm/200nm, and membrane material is metal Ti/Au, as shown in Fig. 3 (f).
8) form gate electrode 307: after plated film, peel off with acetone, as shown in Fig. 3 (g).
9) output source ornamental perforated window mouth, detailed process is is 4000 revs/min by picture domain, spin coating electron beam resist PMMA A4(whirl coating speed, the 60 seconds time), about 200 nanometers of thickness, electron beam exposure, development and fixing, (source electrode and drain electrode width are about in the region of expose to source electrode and drain electrode
500nm), as Fig. 3 (h) and Fig. 3 (i) as shown in.
10) remove oxide layer: optionally removal method has ammonium sulfate solution or the corrosion of other acid solutions, as shown in Fig. 3 (j).
11) prepare source electrode 305 and drain electrode 304 to form ohmic contact, concrete technical process is:
Electron beam plated film or sputter plating (5nm/90nm Ti/Au); Peel off.As shown in Fig. 3 (k) and Fig. 3 (l).
Fig. 4 (a) is that the probe station of a device in the embodiment of the present invention is measured transfer characteristic curve result, wherein, and V
grepresent gate voltage, I
dsrepresent source-drain current.Stationary source drain voltage V
ds=10mV, removes to scan grid with 10mV step-length, and Vg is from-3V to 3V.Fig. 4 (b) is the situation measurement result changing under semilog coordinate, wherein, and V
grepresent gate voltage, I
dsrepresent source-drain current.Its performance index of extracting are from the graph approximately as follows, on-off ratio about 10
4to 10
5; Carrier mobility is 629.3cm
2/ Vs, the sub-threshold slope amplitude of oscillation is 450mV/dec.
Claims (10)
1. the planar rings gate transistor based on nano wire, comprising: substrate, suspend and be parallel to the nano wire of substrate and be positioned on substrate and radially surround the source electrode, gate electrode and the drain electrode that are arranged in order of described nano wire;
The nano wire that described transistorized conducting channel is radially surrounded by gate electrode, has gate medium between described gate electrode and described nano wire;
Described source electrode and drain electrode have spacing with gate electrode respectively, between described source electrode and gate medium, gate electrode and between drain electrode and gate medium, gate electrode, connect without electricity in nanowire sidewalls.
2. the planar rings gate transistor based on nano wire as claimed in claim 1, is characterized in that, described substrate is monocrystalline silicon or the monocrystalline silicon that is coated with silica; Described nano wire is autodoping low-resistance nano wire, and its material is III-V family material.
3. the planar rings gate transistor based on nano wire as claimed in claim 1, is characterized in that, described gate medium is high dielectric constant material; Described source electrode, gate electrode and the very metal electrode that leaks electricity.
4. the preparation method of the planar rings gate transistor based on nano wire as described in as arbitrary in claim 1-3, comprises the steps:
1) first get rid of one deck glue at substrate, then on the even substrate of crossing glue, shift nano wire, and locate nano wire; Get rid of again one deck glue, nano wire is mingled with in the middle of two-layer glue;
2) output gate electrode window and gate electrode window is gone to cull processing, then eroding the native oxide layer of the nano wire under gate electrode window;
3) gate medium of growing on the nano wire under gate electrode window; Prepare gate electrode, then peel off;
4) output source electrode window through ray and drain electrode window, and source electrode window through ray and drain electrode window are gone to cull processing, then erode the native oxide layer of the nano wire under source electrode window through ray and drain electrode window;
5) prepare source electrode and drain electrode, then peel off.
5. the preparation method of the planar rings gate transistor based on nano wire as claimed in claim 4, is characterized in that, the glue described in step 1) is PMMA, and described nano wire is the autodoping of introducing in the process of grow nanowire carrying out.
6. the preparation method of the planar rings gate transistor based on nano wire as claimed in claim 4, is characterized in that, in step 1), described substrate is markd substrate, and localization method is for using ESEM to locate on markd substrate.
7. the preparation method of the planar rings gate transistor based on nano wire as claimed in claim 4, it is characterized in that, step 2) in, by location, exposure and development, fixing, define gate electrode area, exposure method is electron beam exposure, and the method for removing cull is that oxygen plasma removes cull, uses thiamines solution or the mixed acid solution of HCL and IPA corrodes.
8. the preparation method of the planar rings gate transistor based on nano wire as claimed in claim 4, is characterized in that, in step 3), the method for growth gate medium is ald; The preparation method of gate electrode is magnetron sputtering plating, uses acetone to peel off.
9. the preparation method of the planar rings gate transistor based on nano wire as claimed in claim 4, it is characterized in that, in step 4), by even glue, exposure and development, fixing, define electrode district, source and drain regions, exposure method is electron beam exposure, and the method for removing cull is that oxygen plasma removes cull, uses thiamines solution or the mixed acid solution of HCL and IPA corrodes.
10. the preparation method of the planar rings gate transistor based on nano wire as claimed in claim 4, is characterized in that, in step 5), the preparation method of described source electrode and drain electrode is thermal evaporation plated film, electron beam plated film or sputter.
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| CN104979403A (en) * | 2015-05-20 | 2015-10-14 | 北京大学 | Conducting channel wholly-wrapped nanowire plane surrounding-gate field effect device and preparation method therefor |
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| CN102157556A (en) * | 2011-01-27 | 2011-08-17 | 北京大学 | Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof |
| US20130221319A1 (en) * | 2012-02-27 | 2013-08-29 | International Business Machines Corporation | Gate-All Around Semiconductor Nanowire FET's On Bulk Semicoductor Wafers |
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| CN102157556A (en) * | 2011-01-27 | 2011-08-17 | 北京大学 | Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof |
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| KRISTIAN STORM ET AL: "Realizing Lateral Wrap-Gated Nanowire FETs: Contr olling Gate Length with Chemistry Rather than Lithography", 《NANO LETTERS》, 15 February 2011 (2011-02-15) * |
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| CN104979403A (en) * | 2015-05-20 | 2015-10-14 | 北京大学 | Conducting channel wholly-wrapped nanowire plane surrounding-gate field effect device and preparation method therefor |
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