CN103872136A - Power transistor of double-gate MOS structure and manufacturing method of power transistor - Google Patents
Power transistor of double-gate MOS structure and manufacturing method of power transistor Download PDFInfo
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- CN103872136A CN103872136A CN201410111358.1A CN201410111358A CN103872136A CN 103872136 A CN103872136 A CN 103872136A CN 201410111358 A CN201410111358 A CN 201410111358A CN 103872136 A CN103872136 A CN 103872136A
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 216
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- 230000003647 oxidation Effects 0.000 claims abstract description 25
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims description 206
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 63
- 229910052710 silicon Inorganic materials 0.000 claims description 63
- 239000010703 silicon Substances 0.000 claims description 63
- 238000001259 photo etching Methods 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 238000009792 diffusion process Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 238000005304 joining Methods 0.000 claims description 16
- 238000011161 development Methods 0.000 claims description 15
- 238000005260 corrosion Methods 0.000 claims description 12
- 230000007797 corrosion Effects 0.000 claims description 12
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000003466 welding Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 16
- -1 boron ion Chemical class 0.000 description 14
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The invention relates to a power transistor of a double-gate MOS structure. A gate oxidation layer is located on a first doping layer. A second doping layer is located inside the first doping layer and connected with the gate oxidation layer. A third doping layer is located inside the second doping layer and connected with the gate oxidation layer. An insulating dielectric layer covers a polycrystalline silicon layer of an active area primitive cell. A metal layer covers the insulating dielectric layer and extends into a lead hole of the active area primitive cell and is communicated with the third doping layer and the second doping layer. The polycrystalline silicon layer of the active area primitive cell comprises a first polycrystalline silicon gate and a second polycrystalline silicon gate, wherein the first polycrystalline silicon gate and the second polycrystalline silicon gate are isolated from each other by an insulating dielectric layer and are not connected with each other, and the first polycrystalline silicon gate and the second polycrystalline silicon gate are connected to corresponding gate electrode welding areas through metal leads respectively so as to be controlled respectively. The power transistor of the double-gate MOS structure is simple in structure, the polycrystalline silicon layer is divided into the two polycrystalline silicon gates capable of being controlled respectively, the current channel density can be flexibly controlled, and the power transistor can reach the optimum performance state.
Description
Technical field
The present invention relates to power transistor of a kind of dual-gate MOS structure and preparation method thereof, belong to technical field of semiconductor device.
Background technology
In conventional MOSFET, IGBT, the manufacturing process of MCT constant power semiconductor device, its source region primitive cell structure is as shown in Figure 1, to carry out after grid oxygen is processed forming gate oxide 4 at the first doped layer 3, depositing polysilicon layer 5 on gate oxide 4 again, then to polysilicon layer 5 photoetching, etch first window, in first window, inject ion, diffuse to form the second doped layer 2, and then inject ion, diffuse to form the 3rd doped layer 1, carry out again the deposit of insulating medium layer 6, lithography fair lead 8, last deposited metal 7.
But the device of said structure is in order to improve the anti-short circuit capability of power semiconductor device, conventionally can increase the spacing L between polysilicon gate width H or the polysilicon gate of active area.But after chip manufacturing completes, spacing L between width H and the polysilicon gate of the polysilicon gate of active area can not change again, as the width H of constant increase active area polysilicon gate and the spacing L between it, will certainly cause the decline of current channel density in active area, cause the current density of device to decline, the device pressure drop meeting of design increases like this, thereby in the time of application, can increase the quiescent dissipation of device.
Summary of the invention
The object of this invention is to provide a kind of simple in structure, by polysilicon layer being divided into two polysilicon gates that can control respectively, can control flexibly current channel density, make device reach power transistor with dual-gate MOS structure of optimum performance state and preparation method thereof.
The present invention is that the technical scheme achieving the above object is: a kind of power transistor of dual-gate MOS structure, comprise metal level, insulating medium layer, polysilicon layer, gate oxide, the 3rd doped layer and the second doped layer and the first doped layer, gate oxide is positioned on the first doped layer, the second doped layer is positioned at the first doped layer and is connected with gate oxide, the 3rd doped layer is positioned at the second doped layer and is connected with gate oxide, insulating medium layer overlays on the polysilicon layer of active area primitive unit cell, metal level overlays on insulating medium layer, metal level extends in the fairlead of active area primitive unit cell and the conducting of joining of the 3rd doped layer and the second doped layer, it is characterized in that: the polysilicon layer of described active area primitive unit cell comprises by insulating medium layer isolates, and mutually discrete at least one first polysilicon gate and at least one second polysilicon gate, and the first polysilicon gate and the second polysilicon gate are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, to control respectively the first polysilicon gate and the second polysilicon gate.
Wherein: the first described polysilicon gate and the second polysilicon gate interval arrange, and the insulating medium layer between the first polysilicon gate and the second polysilicon gate is provided with the middle leads hole of active area primitive unit cell, metal level extends in middle leads hole and the conducting of joining of the 3rd doped layer and the second doped layer.
Described the first polysilicon gate and the second polysilicon gate form grid unit, insulating medium layer and gate oxide between the first polysilicon gate and the second polysilicon gate in each grid unit join, insulating medium layer between the first polysilicon gate and the second polysilicon gate between adjacent gate unit is provided with the middle leads hole of active area primitive unit cell, and metal level extends in middle leads hole and the conducting of joining of the 3rd doped layer and the second doped layer.
Described the first polysilicon gate and the second polysilicon gate form grid unit, insulating medium layer and gate oxide between the first polysilicon gate and the second polysilicon gate in each grid unit join, insulating medium layer between the first polysilicon gate and the first polysilicon gate between adjacent gate unit is provided with the middle leads hole of active area primitive unit cell, metal level extends in middle leads hole and the conducting of joining of the 3rd doped layer and the second doped layer, or insulating medium layer between the second polysilicon gate and the second polysilicon gate between adjacent gate unit is provided with the middle leads hole of active area primitive unit cell, metal level extends in middle leads hole and the conducting of joining of the 3rd doped layer and the second doped layer.
The width h1 of the first described polysilicon gate is at 0.5 μ m～100 μ m, and the width h2 of the second polysilicon gate is at 0.5 μ m～100 μ m.
The manufacture method of the power transistor of dual-gate MOS structure of the present invention, is characterized in that: according to the following steps,
(1), gate oxidation: the silicon chip with the first doped layer after clean is put into oxidation furnace and carry out gate oxidation process, to form gate oxide;
(2), polysilicon deposit: silicon chip is put into deposit stove, depositing polysilicon layer on the gate oxide of silicon chip;
(3), polysilicon doping: silicon chip is put into diffusion furnace, polysilicon layer is adulterated and forms conductive layer;
(4), photoetching: apply photoresist at silicon chip surface, carry out photoetching, development, etch polysilicon layer and gate oxide, after etching, photoresist is removed, form the first polysilicon gate and the second polysilicon gate, and form first window between the first polysilicon gate and the second polysilicon gate;
(5), Implantation and diffusion: the foreign ion different from the first doped layer injected in first window, then at 1000～1250 DEG C of second doped layers that diffuse to form active area primitive unit cell;
(6), Implantation and diffusion: will inject in first window with the first doped layer Ion Phase foreign ion together, and then silicon chip is put into diffusion furnace, diffuse to form the 3rd doped layer of active area primitive unit cell;
(7), insulating medium layer deposit and backflow: at silicon chip surface deposit insulating medium layer, dielectric layer thickness exists
, then insulating medium layer is carried out to reflow treatment;
(8), fairlead photoetching and corrosion: apply photoresist, photoetching, the insulating medium layer that develops, is etched with source region primitive unit cell and the 3rd doped layer at silicon chip surface, the degree of depth of etching exceeds the 3rd doped layer degree of depth 0.1 μ m～0.5 μ m and forms fairlead and the middle leads hole of source region primitive unit cell;
(9), metal level deposit: to silicon chip sputter or evaporated metal layer, metal layer thickness is 0.5 μ m～5 μ m;
(10), metal lithographic and corrosion: apply photoresist, photoetching, development, etching sheet metal formation electrode at metal level, the first polysilicon gate and the second polysilicon gate are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make the power transistor of the MOS structure with double grid.
The manufacture method of the power transistor of another dual-gate MOS structure of the present invention, is characterized in that: according to the following steps,
(1), gate oxidation: the silicon chip with the first doped layer after clean is put into oxidation furnace and carry out gate oxidation process, to form gate oxide;
(2), polysilicon deposit: silicon chip is put into deposit stove, depositing polysilicon layer on the gate oxide of silicon chip;
(3), polysilicon doping: silicon chip is put into diffusion furnace, polysilicon layer is adulterated and forms conductive layer;
(4), photoetching: apply photoresist at silicon chip surface, carry out photoetching, development, etch polysilicon layer and gate oxide and form grid unit, after etching, photoresist is removed, and form first window between each grid unit;
(5), Implantation and diffusion: the foreign ion different from the first doped layer injected in first window, then at 1000～1250 DEG C of second doped layers that diffuse to form active area primitive unit cell;
(6), Implantation and diffusion: will inject in first window with the first doped layer Ion Phase foreign ion together, and then silicon chip is put into diffusion furnace, diffuse to form the 3rd doped layer of active area primitive unit cell;
(7), photoetching: apply photoresist on silicon chip, carry out light should, polysilicon layer in development, etching grid unit, form the first polysilicon gate and the second polysilicon gate, and between the first polysilicon gate and the second polysilicon gate, form Second Window, described Second Window width is controlled at 0.5 μ m～30 μ m;
(8), insulating medium layer deposit and backflow: at silicon chip surface deposit insulating medium layer, dielectric layer thickness exists
, then insulating medium layer is carried out to reflow treatment;
(9), fairlead photoetching and corrosion: apply photoresist, photoetching, the insulating medium layer that develops, is etched with source region primitive unit cell and the 3rd doped layer at silicon chip surface, the degree of depth of etching exceeds the 3rd doped layer degree of depth 0.1 μ m～0.5 μ m and forms fairlead and the middle leads hole of source region primitive unit cell;
(10), metal level deposit: to silicon chip sputter or evaporated metal layer, metal layer thickness is 0.5 μ m～5 μ m;
(11), metal lithographic and corrosion: apply photoresist, photoetching, development, etching sheet metal formation electrode at metal level, the first polysilicon gate and the second polysilicon gate are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make the power transistor of the MOS structure with double grid.
The present invention is divided into the polysilicon layer of active area primitive unit cell at least one first polysilicon gate and at least one second polysilicon gate of mutually not joining, and the first polysilicon gate and the second polysilicon gate are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make polysilicon layer be divided into two polysilicon gates that can control respectively, can control respectively the first polysilicon gate and the second polysilicon gate, and flexible control device current channel density, and the current density of control device.In the time of the device of the high short-circuit capacity of needs, can be only by the first polysilicon gate or the second polysilicon gate, one of them is drawn, can make like this to reduce current channel density, make device there is high anti-short circuit capability thereby device saturation current is declined; In the time not needing high short-circuit capacity device, the polysilicon gate of two parts all can also be drawn, can keep higher current channel density, and improve current density, thereby reduce device forward voltage drop, make the quiescent dissipation of device less.When same device had both needed to have high short-circuit capacity according to working condition, sometimes do not need again high short circuit current ability, just the first polysilicon gate and the second polysilicon gate can be drawn respectively, by changing the driving signal on one of them polysilicon gate, in the time not needing short-circuit capacity, open the driving signal on two polysilicon gates, can increase current channel density; In the time of needs short-circuit capacity, can close again the driving signal on one of them polysilicon gate, make it possess good short-circuit capacity.The present invention is control device current channel density flexibly, can make device reach optimum performance state.The power transistor that the present invention has dual-gate MOS structure adopts common process to make, and can not show to increase to manufacture, and has good manufacturability, is convenient to suitability for industrialized production.
Brief description of the drawings
Below in conjunction with accompanying drawing, embodiments of the invention are described in further detail.
Fig. 1 is the structural representation of the power transistor of former MOS structure.
Fig. 2 is the structural representation of the power transistor of a kind of dual-gate MOS structure of the present invention.
Fig. 3 is the structural representation of the power transistor of the another kind of dual-gate MOS structure of the present invention.
Fig. 4 is the structural representation of the power transistor of another dual-gate MOS structure of the present invention.
Fig. 5 is the power transistor of dual-gate MOS structure of the present invention and conventional power transistor collector current and collector voltage curve.
Wherein: the 1-the three doped layer, the 2-the second doped layer, the 3-the first doped layer, 4-gate oxide, 5-polysilicon layer, the 51-the first polysilicon gate, the 52-the second polysilicon gate, 6-insulating medium layer, 7-metal level, 8-fairlead, 9-middle leads hole.
Embodiment
See shown in Fig. 2～4, the power transistor of dual-gate MOS structure of the present invention, comprise metal level 7, insulating medium layer 6, polysilicon layer, gate oxide 4, the 3rd doped layer 1 and the second doped layer 2 and the first doped layer 3, gate oxide 4 is positioned on the first doped layer 3, the second doped layer 2 is positioned at the first doped layer 3 and is connected with gate oxide 4, the 3rd doped layer 1 is positioned at the second doped layer 2 and is connected with gate oxide 4, insulating medium layer 6 overlays on the polysilicon layer of active area primitive unit cell, metal level 7 overlays on insulating medium layer 6, metal level 7 extends in the fairlead 8 of active area primitive unit cell and the conducting of joining of the 3rd doped layer 1 and the second doped layer 2, the polysilicon layer of active area primitive unit cell comprises by insulating medium layer 6 and isolating, and mutually discrete at least one first polysilicon gate 51 and at least one second polysilicon gate 52, and the first polysilicon gate 51 and the second polysilicon gate 52 are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, therefore can control respectively the first polysilicon gate 51 and the second polysilicon gate 52, with flexible control device current channel density, and the current density of control device, can make device reach optimum performance state.
As shown in Figure 2, its first polysilicon gate 51 of the polysilicon layer of active area of the present invention primitive unit cell and the second polysilicon gate 52 intervals arrange, and the insulating medium layer 6 between the first polysilicon gate 51 and the second polysilicon gate 52 is provided with the middle leads hole 9 of active area primitive unit cell, metal level 7 extends in middle leads hole 9 and the conducting of joining of the 3rd doped layer 1 and the second doped layer 2, to form two controllable grids, and control flexibly the current channel density of active area.
As shown in Figure 3, it is the power transistor of the dual-gate MOS structure of another kind of structure of the present invention, its difference is that the first polysilicon gate 51 and the second polysilicon gate 52 form independently grid unit, as two grid unit, or more grid unit, the first polysilicon gate 51 and the second polysilicon gate 52 can be arranged according to the order of sequence, insulating medium layer 6 between the first polysilicon gate 51 and the second polysilicon gate 52 in adjacent gate unit joins with gate oxide 4, insulating medium layer 6 between the first polysilicon gate 51 and the second polysilicon gate 52 between adjacent gate unit is provided with the middle leads hole 9 of active area primitive unit cell, metal level 7 extends in middle leads hole 9 and the conducting of joining of the 3rd doped layer 1 and the second doped layer 2, to form two controllable grids, and control flexibly the current channel density of active area.
Can be as shown in Figure 4, the present invention plants the power transistor of the dual-gate MOS structure of structure again, its difference is that the first polysilicon gate 51 and the second polysilicon gate 52 form independently grid unit, insulating medium layer 6 between the first polysilicon gate 51 and the second polysilicon gate 52 in each grid unit joins with gate oxide 4, insulating medium layer 6 between the first polysilicon gate 51 and the first polysilicon gate 51 between adjacent gate unit is provided with the middle leads hole 9 of active area primitive unit cell, and metal level 7 extends in middle leads hole 9 and the conducting of joining of the 3rd doped layer 1 and the second doped layer 2.Or insulating medium layer 6 between the second polysilicon gate 52 and the second polysilicon gate 52 between adjacent gate of the present invention unit is provided with the middle leads hole 9 of active area primitive unit cell, metal level 7 extends in middle leads hole 9 and the conducting of joining of the 3rd doped layer 1 and the second doped layer 2, can form equally two controllable grids, and control flexibly the current channel density of active area.
The width h1 of the present invention's the first polysilicon gate 51 is at 0.5 μ m～100 μ m, the width h2 of the second polysilicon gate 52 is at 0.5 μ m～100 μ m, the width h1 of the first polysilicon gate 51 in Fig. 2 is at 0.5 μ m～100 μ m, the width h2 of the second polysilicon gate 52 is at 0.5 μ m～100 μ m, and the width h1 of the first polysilicon gate 51 in Fig. 3 and Fig. 4 is at 0.5 μ m～60 μ m, the width h2 of the second polysilicon gate 52 is at 0.5m～60 μ m.
As shown in Figure 2, the manufacture method of the power transistor of a kind of dual-gate MOS structure of the present invention, according to the following steps,
(1), gate oxidation: the silicon chip with the first doped layer 3 after clean is put into oxidation furnace and carry out gate oxidation process, silicon chip is put into oxidation furnace and carry out gate oxidation under 900 DEG C～1200 DEG C conditions, forms gate oxide 4, and the thickness of gate oxide 4 exists
.
(2), polysilicon deposit: silicon chip is put into deposit stove, and depositing polysilicon layer 5 on the gate oxide 4 of silicon chip, utilizes low pressure chemical vapor deposition (LPCVD) depositing polysilicon layer 5 on gate oxide 4, and the THICKNESS CONTROL of polysilicon layer 5 exists
, this thickness is preferably controlled at
, can determine according to the designing requirement of device the concrete thickness of polysilicon layer.
(3), polysilicon doping: silicon chip is put into diffusion furnace, at 850 DEG C～1000 DEG C temperature, polysilicon layer 5 is adulterated and forms conductive layer.
(4), photoetching: technique applies photoresist at silicon chip surface routinely, carry out photoetching, development, etch polysilicon layer 5 and gate oxide 4, after etching, photoresist is removed, form the first polysilicon gate 51 and the second polysilicon gate 52, the width h2 of the width h1 of the first polysilicon gate 51 and the second polysilicon gate 52 is all controlled at 0.5 μ m～100 μ m, between the first polysilicon gate 51 and the second polysilicon gate 52, form first window, first window width is controlled at 0.5 μ m～100 μ m.
(5), Implantation and diffusion: the foreign ion different from the first doped layer injected in first window, can inject in first window by ion implantor, this the first impurity can adopt boron ion or phosphonium ion, in the time adopting boron ion, its Implantation Energy is at 60～120KeV, and implantation dosage is at 5E12～5E14; If adopt when phosphonium ion, its Implantation Energy is at 60～180KeV, and implantation dosage is at 5E12～5E14, then at 1000～1250 DEG C of second doped layers 2 that diffuse to form active area primitive unit cell;
(6), Implantation and diffusion: will can inject in first window by ion implantor with the first doped layer Ion Phase foreign ion together, can adopt phosphonium ion or arsenic ion or boron ion or boron difluoride ion etc., and then silicon chip is put into diffusion furnace, at 900～1100 DEG C of temperature, diffuse to form the 3rd doped layer 1 of active area primitive unit cell.
(7), insulating medium layer 6 deposits and backflow: at silicon chip surface deposit insulating medium layer 6, silicon chip can be put into deposit stove, with Plasma-enhanced chemical vapor deposition (PECVD), at silicon chip surface deposit insulating medium layer 6, this insulating medium layer 6 adopts conventional phosphorosilicate glass or boron-phosphorosilicate glass, make insulating medium layer 6 surfaces comparatively smooth when reaching reflow treatment, preferably select boron-phosphorosilicate glass, insulating medium layer 6 thickness exist
, be preferably in
, by the control to insulating medium layer 6 thickness, can ensure to stop the ability of movable charge pickup, can ensure again the accuracy of fairlead 8 and middle leads hole 9 etchings, then insulating medium layer is carried out to reflow treatment.
(8), fairlead photoetching and corrosion: technique applies photoresist, photoetching at silicon chip surface, develops, is etched with insulating medium layer and the 3rd doped layer 1 of source region primitive unit cell routinely, and the degree of depth of etching exceeds the 3rd doped layer degree of depth 0.1 μ m～0.5 μ m and forms fairlead 8 and the middle leads hole 9 of source region primitive unit cell.
(9), metal level deposit: to silicon chip sputter or evaporated metal layer 7, metal level 7 thickness are 0.5 μ m～5 μ m.
((10), metal lithographic and corrosion: technique applies photoresist, photoetching, development, etching sheet metal 7 at metal level 7 and forms electrode routinely, the first polysilicon gate 51 and the second polysilicon gate 52 are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make the power transistor of the MOS structure with double grid.
Seeing shown in Fig. 3,4, is the manufacture method of the power transistor of the dual-gate MOS structure of another structure of the present invention, according to the following steps,
(1), gate oxidation: the silicon chip with the first doped layer 3 after clean is put into oxidation furnace and carry out gate oxidation process, silicon chip is put into oxidation furnace and carry out gate oxidation under 900 DEG C～1200 DEG C conditions, forms gate oxide 4, and the thickness of gate oxide 4 exists
.
(2), polysilicon deposit: silicon chip is put into deposit stove, and depositing polysilicon layer 5 on the gate oxide 4 of silicon chip, utilizes low pressure chemical vapor deposition (LPCVD) depositing polysilicon layer 5 on gate oxide 4, and the THICKNESS CONTROL of polysilicon layer 5 exists
, this thickness is preferably controlled at
, can determine according to the designing requirement of device the concrete thickness of polysilicon layer 5.
(3), polysilicon doping: silicon chip is put into diffusion furnace, at 850 DEG C～1000 DEG C temperature, polysilicon layer 5 is adulterated and forms conductive layer.
(4), photoetching: apply photoresist at silicon chip surface, carry out photoetching, development, etch polysilicon layer 5 and gate oxide 4 and form grid unit, after etching, photoresist is removed, and form first window between each grid unit, first window width is controlled at 0.5 μ m～100 μ m.
(5), Implantation and diffusion: the foreign ion different from the first doped layer injected in first window, can inject in first window by ion implantor, this the first impurity can adopt boron ion or phosphonium ion, in the time adopting boron ion, its Implantation Energy is at 60～120KeV, and implantation dosage is at 5E12～5E14; If adopt when phosphonium ion, its Implantation Energy is at 60～180KeV, and implantation dosage is at 5E12～5E14, then at 1000～1250 DEG C of second doped layers 2 that diffuse to form active area primitive unit cell.
(6), Implantation and diffusion: will can inject in first window by ion implantor with the first doped layer Ion Phase foreign ion together, can adopt phosphonium ion or arsenic ion or boron ion or boron difluoride ion etc., and then silicon chip is put into diffusion furnace, at 900～1100 DEG C of temperature, diffuse to form the 3rd doped layer 1 of active area primitive unit cell.
(7), photoetching: apply photoresist on silicon chip, carry out light should, polysilicon layer 5 in development, etching grid unit, form at least one first polysilicon gate 51 and at least one second polysilicon gate 52, the width h2 of the width h1 of the first polysilicon gate 51 and the second polysilicon gate 52 is all controlled at 0.5 μ m～60 μ m, and adjacent the first polysilicon gate 51 and the second polysilicon gate 52 form Second Window, and this Second Window width is controlled at 0.5 μ m～30 μ m.
(8), insulating medium layer 6 deposits and backflow: at silicon chip surface deposit insulating medium layer 6, silicon chip can be put into deposit stove, with Plasma-enhanced chemical vapor deposition (PECVD), at silicon chip surface deposit insulating medium layer 6, this insulating medium layer 6 adopts conventional phosphorosilicate glass or boron-phosphorosilicate glass, make insulating medium layer 6 surfaces comparatively smooth when reaching reflow treatment, preferably select boron-phosphorosilicate glass, insulating medium layer 6 thickness exist
, be preferably in
, by the control to insulating medium layer 6 thickness, can ensure to stop the ability of movable charge pickup, can ensure again the accuracy of fairlead 8 and middle leads hole 9 etchings, then insulating medium layer 6 is carried out to reflow treatment.
(9), fairlead photoetching and corrosion: technique applies photoresist, photoetching at silicon chip surface, develops, is etched with insulating medium layer 6 and the 3rd doped layer 1 of source region primitive unit cell routinely, and the degree of depth of etching exceeds the 3rd doped layer degree of depth 0.1 μ m～0.5 μ m and forms fairlead 8 and the middle leads hole 9 of source region primitive unit cell.
(10), metal level deposit: to silicon chip sputter or evaporated metal layer 7, metal level 7 thickness are 0.5 μ m～5 μ m.
(11), metal lithographic and corrosion: technique applies photoresist, photoetching, development, etching sheet metal 7 at metal level 7 and forms electrode routinely, the first polysilicon gate 51 and the second polysilicon gate 52 are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make the power transistor of the MOS structure with double grid.
See that Fig. 5 is the power transistor that adopts the dual-gate MOS structure shown in Fig. 2 and Fig. 3 in the present invention, and draw the graph of a relation between device collector current and collector voltage under various conditions by emulation, Fig. 3 is identical with the simulation architecture of Fig. 4.As shown in Figure 5, conventional device is under short-circuit condition, and its collector voltage is all greater than 40V; And adopt device of the present invention as can be seen from Figure 5, in the time that the second polysilicon gate 52 is closed, collector voltage is in the time of 50V, saturation current is at 1E-4A/ μ m and 1.4E-4A/ μ m, have and existing device 1.2E-4A/ μ m, all have lower saturation current, therefore, in the time that the second polysilicon gate 52 is closed, device has good anti-short circuit capability.As shown in Figure 5, in normal operation, its collector voltage is all less than 10V to conventional device; And open when the second polysilicon gate 52, collector voltage is in the time of 5V, the collector current of the power transistor of dual-gate MOS structure of the present invention is all at 5E-5A/ μ m, the collector current 2.5E-5A/ μ m of existing device, the collector current of existing device is 2 times of device of the present invention, therefore in the time that the second polysilicon gate 52 is opened, device of the present invention has higher current density.
Claims (7)
1. the power transistor of a dual-gate MOS structure, comprise metal level (7), insulating medium layer (6), polysilicon layer, gate oxide (4), the 3rd doped layer (1) and the second doped layer (2) and the first doped layer (3), gate oxide (4) is positioned on the first doped layer (3), the second doped layer (2) is positioned at the first doped layer (3) and is connected with gate oxide (4), the 3rd doped layer (1) is positioned at the second doped layer (2) and is connected with gate oxide (4), insulating medium layer (6) overlays on the polysilicon layer of active area primitive unit cell, metal level (7) overlays on insulating medium layer (6), metal level (7) extends in the fairlead (8) of active area primitive unit cell and the conducting of joining of the 3rd doped layer (1) and the second doped layer (2), it is characterized in that: the polysilicon layer of described active area primitive unit cell comprises by insulating medium layer (6) and isolating, and mutually discrete at least one first polysilicon gate (51) and at least one the second polysilicon gate (52), and the first polysilicon gate (51) and the second polysilicon gate (52) are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, to control respectively the first polysilicon gate (51) and the second polysilicon gate (52).
2. the power transistor of dual-gate MOS structure according to claim 1, it is characterized in that: described the first polysilicon gate (51) arranges with the second polysilicon gate (52) interval, and the insulating medium layer (6) between the first polysilicon gate (51) and the second polysilicon gate (52) is provided with the middle leads hole (9) of active area primitive unit cell, metal level (7) extends in middle leads hole (9) and the conducting of joining of the 3rd doped layer (1) and the second doped layer (2).
3. the power transistor of dual-gate MOS structure according to claim 1, it is characterized in that: described the first polysilicon gate (51) and the second polysilicon gate (52) form grid unit, insulating medium layer (6) between the first polysilicon gate (51) and the second polysilicon gate (52) in each grid unit joins with gate oxide (4), insulating medium layer (6) between the first polysilicon gate (51) and the second polysilicon gate (52) between adjacent gate unit is provided with the middle leads hole (9) of active area primitive unit cell, metal level (7) extends in middle leads hole (9) and the conducting of joining of the 3rd doped layer (1) and the second doped layer (2).
4. the power transistor of dual-gate MOS structure according to claim 1, it is characterized in that: described the first polysilicon gate (51) and the second polysilicon gate (52) form grid unit, insulating medium layer (6) between the first polysilicon gate (51) and the second polysilicon gate (52) in each grid unit joins with gate oxide (4), insulating medium layer (6) between the first polysilicon gate (51) and the first polysilicon gate (51) between adjacent gate unit is provided with the middle leads hole (9) of active area primitive unit cell, metal level (7) extends in middle leads hole (9) and the conducting of joining of the 3rd doped layer (1) and the second doped layer (2), or insulating medium layer (6) between the second polysilicon gate (52) and the second polysilicon gate (52) between adjacent gate unit is provided with the middle leads hole (9) of active area primitive unit cell, metal level (7) extends in middle leads hole (9) and the conducting of joining of the 3rd doped layer (1) and the second doped layer (2).
5. according to the power transistor of the dual-gate MOS structure described in claim 1 to 4, it is characterized in that: the width h1 of described the first polysilicon gate (51) is at 0.5 μ m～100 μ m, and the width h2 of the second polysilicon gate (52) is at 0.5 μ m～100 μ m.
6. according to the manufacture method of the power transistor of the dual-gate MOS structure one of claim 1 or 2 or 5 Suo Shu, it is characterized in that: according to the following steps,
(1), gate oxidation: the silicon chip with the first doped layer after clean is put into oxidation furnace and carry out gate oxidation process, to form gate oxide;
(2), polysilicon deposit: silicon chip is put into deposit stove, depositing polysilicon layer on the gate oxide of silicon chip;
(3), polysilicon doping: silicon chip is put into diffusion furnace, polysilicon layer is adulterated and forms conductive layer;
(4), photoetching: apply photoresist at silicon chip surface, carry out photoetching, development, etch polysilicon layer and gate oxide, after etching, photoresist is removed, form the first polysilicon gate and the second polysilicon gate, and form first window between the first polysilicon gate and the second polysilicon gate;
(5), Implantation and diffusion: the foreign ion different from the first doped layer injected in first window, then at 1000～1250 DEG C of second doped layers that diffuse to form active area primitive unit cell;
(6), Implantation and diffusion: will inject in first window with the first doped layer Ion Phase foreign ion together, and then silicon chip is put into diffusion furnace, diffuse to form the 3rd doped layer of active area primitive unit cell;
(7), insulating medium layer deposit and backflow: at silicon chip surface deposit insulating medium layer, dielectric layer thickness exists
, then insulating medium layer is carried out to reflow treatment;
(8), fairlead photoetching and corrosion: apply photoresist, photoetching, the insulating medium layer that develops, is etched with source region primitive unit cell and the 3rd doped layer at silicon chip surface, the degree of depth of etching exceeds the 3rd doped layer degree of depth 0.1 μ m～0.5 μ m and forms fairlead and the middle leads hole of source region primitive unit cell;
(9), metal level deposit: to silicon chip sputter or evaporated metal layer, metal layer thickness is 0.5 μ m～5 μ m;
(10), metal lithographic and corrosion: apply photoresist, photoetching, development, etching sheet metal formation electrode at metal level, the first polysilicon gate and the second polysilicon gate are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make the power transistor of the MOS structure with double grid.
7. according to the manufacture method of the power transistor of the dual-gate MOS structure one of claim 1 or 3 or 4 or 5 Suo Shu, it is characterized in that: according to the following steps,
(1), gate oxidation: the silicon chip with the first doped layer after clean is put into oxidation furnace and carry out gate oxidation process, to form gate oxide;
(2), polysilicon deposit: silicon chip is put into deposit stove, depositing polysilicon layer on the gate oxide of silicon chip;
(3), polysilicon doping: silicon chip is put into diffusion furnace, polysilicon layer is adulterated and forms conductive layer;
(4), photoetching: apply photoresist at silicon chip surface, carry out photoetching, development, etch polysilicon layer and gate oxide and form grid unit, after etching, photoresist is removed, and form first window between each grid unit;
(5), Implantation and diffusion: the foreign ion different from the first doped layer injected in first window, then at 1000～1250 DEG C of second doped layers that diffuse to form active area primitive unit cell;
(6), Implantation and diffusion: will inject in first window with the first doped layer Ion Phase foreign ion together, and then silicon chip is put into diffusion furnace, diffuse to form the 3rd doped layer of active area primitive unit cell;
(7), photoetching: apply photoresist on silicon chip, carry out light should, polysilicon layer in development, etching grid unit, form the first polysilicon gate and the second polysilicon gate, and between the first polysilicon gate and the second polysilicon gate, form Second Window, described Second Window width is controlled at 0.5 μ m～30 μ m;
(8), insulating medium layer deposit and backflow: at silicon chip surface deposit insulating medium layer, dielectric layer thickness exists
, then insulating medium layer is carried out to reflow treatment;
(9), fairlead photoetching and corrosion: apply photoresist, photoetching, the insulating medium layer that develops, is etched with source region primitive unit cell and the 3rd doped layer at silicon chip surface, the degree of depth of etching exceeds the 3rd doped layer degree of depth 0.1 μ m～0.5 μ m and forms fairlead and the middle leads hole of source region primitive unit cell;
(10), metal level deposit: to silicon chip sputter or evaporated metal layer, metal layer thickness is 0.5 μ m～5 μ m;
(11), metal lithographic and corrosion: apply photoresist, photoetching, development, etching sheet metal formation electrode at metal level, the first polysilicon gate and the second polysilicon gate are connected to territory, each self-corresponding gate pad by metal lead wire separately respectively, make the power transistor of the MOS structure with double grid.
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| WO2015143697A1 (en) * | 2014-03-28 | 2015-10-01 | 江苏宏微科技股份有限公司 | Power transistor with double-gate mos structure, and manufacturing method therefor |
| CN105870016A (en) * | 2015-01-21 | 2016-08-17 | 北大方正集团有限公司 | Power device manufacturing method and power device |
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