CN103872017B - Test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and wafer - Google Patents
Test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and wafer Download PDFInfo
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- CN103872017B CN103872017B CN201210530102.5A CN201210530102A CN103872017B CN 103872017 B CN103872017 B CN 103872017B CN 201210530102 A CN201210530102 A CN 201210530102A CN 103872017 B CN103872017 B CN 103872017B
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Abstract
The invention provides a test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and a wafer. The test structure at least includes: an interdigitated antenna part used for collecting charges and including a first connecting end and a second connecting end; and a field effect transistor structure part which includes a structure needed by formation of a field effect transistor, and the grid electrode of the field effect transistor that is formed is connected with the first connecting end of the antenna part. The wafer at least includes the aforementioned test structure; and a plurality of electric connecting points which are all arranged on a surface layer. Each electric connecting point is connected with one of the second connecting end included in the test structure, the grid electrode, the drain electrode, and the source electrode of the field effect transistor formed respectively by each test structure, and a substrate connecting end of the field effect transistor. Advantages of the test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and the wafer include: one test structure can complete two tests including PID and ILD tests, and the area of a cutting channel region of the provided wafer is small.
Description
Technical field
The present invention relates to manufacture of semiconductor field, more particularly to a kind of test structure that can be used for PID and ILD test and
Wafer.
Background technology
As shown in figure 1, it is a kind of existing wafer schematic diagram, this wafer 1 includes multiple chip structure areas 11, chip structure
Spacer between area 11 and chip structure area 11 is Cutting Road area.When each self-contained device structure layer in each chip structure area 11
After completing, by Cutting Road area is carried out with cutting, each chip structure area 11 is separated.And the development with technology, respectively
Wafer production business, in order to chase benefit, often updates skill to reduce the area of one single chip structural area, so that
Make greater number of chip structure is comprised on single wafer.
In order to ensure the quality of chip structure, wafer production business needs to carry out various tests to the wafer of preparation, wherein, right
In the wafer of less than 0.3 micron technique productions, the test carrying out include PID (Plasma Induced Damage) test with
ILD (Inter Layer Dielectric) tests.Generally, wafer production business passes through to arrange PID survey in the cutting area of wafer
Examination structure and ILD test structure to carry out PID test and ILD test respectively.In wafer arrange PID test structure quantity according to
The species of the field effect transistor that the quantity of the device layer being comprised according to chip in wafer structure and each device layer comprise is come really
The quantity of the device layer that fixed, setting ILD test structure quantity is then comprised according to chip in wafer structure is determining.
For example, if the chip structure that a wafer is comprised has 6 layer device layers, each device layer includes thin grid oxygen N-type MOS
Pipe, thick grid oxygen N-type metal-oxide-semiconductor, thin grid oxygen p-type metal-oxide-semiconductor, thick grid oxygen p-type metal-oxide-semiconductor totally 4 kinds of field effect transistor, then correspondingly, in wafer
Each floor in Cutting Road area need to arrange 4 PID test structures and 1 ILD test structure, 4*6=24 PID tests altogether
Structure and 6 ILD test structures.Due to the field-effect tube structure that each PID test structure comprises have grid, drain electrode, source electrode,
4 exits of substrate, each ILD test structure have 2 exits, therefore the cutting area on wafer top layer needs to arrange 4*24=
96 the first weld pads, 2*6=12 the second weld pads, wherein, first weld pad connect the exit of a PID test structure, one
Individual second weld pad connects the exit of an ILD test.Obviously, so many weld pad occupies excessive wafer area, therefore urgent
It is essential and existing test structure will be improved.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide one kind can be used for PID and ILD test
Test structure.
Another object of the present invention is to providing a kind of Cutting Road area area little wafer.
For achieving the above object and other related purposes, the present invention provides a kind of test knot that can be used for PID and ILD test
Structure, it is arranged in wafer, at least includes：
In interdigitated and for collecting the antenna part of electric charge, it comprises the first connection end and the second connection end；
Field-effect tube structure portion, including the structure being formed required for field effect transistor, and the grid of the field effect transistor being formed
Connect the first connection end of described antenna part.
Preferably, the thickness of described grid to be determined by the gate of the field effect transistor in the corresponding device layer of wafer.
Preferably, the type of the field effect transistor being formed is come really by the type of the field effect transistor in the corresponding device layer of wafer
Fixed.
Preferably, described can be used for the test structure that PID and ILD tests and also include：It is connected between described grid and ground
Protection tubular construction；It is further preferable that described protection tubular construction is diode structure.
Preferably, the described test structure that can be used for PID and ILD test is arranged on the Cutting Road area in described wafer.
The wafer of the present invention, it includes multiple chip region and by the Cutting Road area that each chip region separates, and at least also includes：
At least one aforesaid test structure that can be used for PID and ILD test；And
Multiple electric connecting points, are arranged at top layer, each connect the second connection end that test structure comprised,
And each test structure each formed the grid of field effect transistor, drain electrode, source electrode and described field effect transistor substrate even
Connect one of end.
Preferably, all electric connecting points are arranged at Cutting Road area.
Preferably, chip region comprises multilayer device layer, and the number of plies that Cutting Road area comprises is identical with the device number of plies, and Cutting Road
The each floor in area is respectively provided with the test structure of at least one.
As described above, the test structure and the wafer that can be used for PID and ILD test of the present invention, have the advantages that：
A kind of test structure can complete PID test and ILD test；The area shared by Cutting Road area of wafer provided by the present invention
Little.
Brief description
Fig. 1 is shown as wafer schematic diagram of the prior art.
Fig. 2 is shown as the test structure schematic diagram that can be used for PID and ILD test of the present invention.
Component label instructions
Specific embodiment
Hereinafter embodiments of the present invention are illustrated by particular specific embodiment, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the present invention easily.
Refer to Fig. 1 to Fig. 2.It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., all only in order to
Content disclosed in cooperation description, so that those skilled in the art understands and reads, being not limited to the present invention can be real
The qualificationss applied, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size
Whole, under not affecting present invention effect that can be generated by and the purpose that can reach, all should still fall in disclosed skill
In the range of art content obtains and can cover.Meanwhile, in this specification cited as " on ", D score, "left", "right", " middle " and
The term of " one " etc., is merely convenient to understanding of narration, and is not used to limit the enforceable scope of the present invention, its relativeness
It is altered or modified, under no essence change technology contents, when being also considered as the enforceable category of the present invention.
As illustrated, the present invention provides a kind of test structure that can be used for PID and ILD test.Described test structure 2 is at least
Including：Antenna part 21 and field-effect tube structure portion 22.
Described antenna part 21 is in interdigitated, as shown in Fig. 2 it has the first connection end 211 and the second connection end 212, uses
In collection electric charge it is preferable that described antenna part 21 to be prepared using metal material.
Described field-effect tube structure portion 22 includes forming the structure required for field effect transistor, and the field effect transistor being formed
Grid connects the first connection end 211 of described antenna part 21.
As a kind of optimal way, described test structure 2 also includes protecting tubular construction 23, for example, diode structure, this guarantor
Pillar structure 23 is connected between grid and the ground in field-effect tube structure portion 22, for protecting the grid oxygen in field-effect tube structure portion 22
Layer.
From the above mentioned, ILD test can be carried out by the grid of the second connection end 212 and field-effect tube structure portion 22, pass through
The grid in field-effect tube structure portion 22, drain electrode, source electrode, substrate connection end can carry out PID test.
Above-mentioned test structure 2 can be prepared during preparing the chip structure that wafer is comprised simultaneously formed.
For example, select a Silicon Wafer, this Silicon Wafer is formed each chip structure a layer device layer while, cutting
The equivalent layer in road area forms the test structure of the present invention, wherein, if device layer includes thin grid oxygen N-type metal-oxide-semiconductor, thick grid oxygen N-type
Metal-oxide-semiconductor, thin grid oxygen p-type metal-oxide-semiconductor, thick grid oxygen p-type metal-oxide-semiconductor totally 4 kinds of field effect transistor, then can form 4 present invention in Cutting Road area
Described test structure, also can only form 1 test structure of the present invention and 3 existing PID test structures etc..Work as formation
During 4 test structures of the present invention, the field effect transistor in 4 test structures being formed is respectively thin grid oxygen N-type MOS
Pipe, thick grid oxygen N-type metal-oxide-semiconductor, thin grid oxygen p-type metal-oxide-semiconductor, thick grid oxygen p-type metal-oxide-semiconductor；If of the present invention in Cutting Road area formation 1
Test structure and 3 existing PID test structures, then the field effect transistor in the test structure of the present invention being formed can be thin grid
One of oxygen N-type metal-oxide-semiconductor, thick grid oxygen N-type metal-oxide-semiconductor, thin grid oxygen p-type metal-oxide-semiconductor, thick grid oxygen p-type metal-oxide-semiconductor.
Then, after the completion of each device layer in the chip structure that this wafer is comprised all is prepared, re-form on top layer
Multiple electric connecting points, each electric connecting point connect the second connection end that test structure comprised and each
In the grid of the field effect transistor that test structure is each formed, the substrate connection end of drain electrode, source electrode and described field effect transistor one
Individual.Wherein, electric connecting point can be weld pad etc..
The wafer thus being formed includes：Multiple chip region and the Cutting Road area separating each chip region, in Cutting Road
Each floor in area at least formed with a test structure of the present invention, also includes multiple electrically connecting on the top layer in Cutting Road area
Contact, the second connection end that each electric connecting point one test structure of connection is comprised and each test structure are each
From one of the grid of the field effect transistor being formed, the substrate connection end of drain electrode, source electrode and described field effect transistor.
The quantity of the weld pad that this wafer Cutting Road area is comprised to be described below taking the wafer comprising 6 layer device floor as a example.
Based on described above, for the wafer of 6 layer device layers, if each device layer all comprises thin grid oxygen N-type metal-oxide-semiconductor, thickness
Grid oxygen N-type metal-oxide-semiconductor, thin grid oxygen p-type metal-oxide-semiconductor, thick grid oxygen p-type metal-oxide-semiconductor totally 4 kinds of field effect transistor, correspondingly, Cutting Road area also comprises
6 layers, and each layer include at least one test structure of the present invention：
The first situation：If 4 test structures of the present invention of one layer of inclusion, due in 4 surveys of the present invention
Examination structure in it is only necessary to a test structure second connection end connect a weld pad can carry out ILD test, therefore 4 this
Second connection end of 3 in bright described test structure does not need to connect weld pad, therefore, under this kind of situation, required for one layer
Weld pad quantity be 1+4*4=17；
Second case, if one layer includes being not more than 4 test structures of the present invention, because existing PID tests knot
Structure only needs to 4, and connection grid, the weld pad of the substrate connection end of drain electrode, source electrode and described field effect transistor can carry out PID respectively
Test, and according to 2 or 3 test structures of the present invention, also only need to a test structure of the present invention
Second connection end connects a weld pad and can carry out ILD test, therefore the weld pad quantity required for one layer is also 1+4*4=17.
Therefore, for the wafer comprising 6 layer device layers, the weld pad quantity that its top layer is formed is 17*6=102, is less than
Existing need 108, therefore can save the area in wafer Cutting Road region, and then the area of chip structure can be increased, thus carrying
The economic benefit of high wafer production manufacturer.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (9)
1. a kind of test structure that can be used for PID and ILD test is it is characterised in that described can be used for the survey that PID and ILD tests
In wafer, it at least includes examination structure setting：
In interdigitated and for collecting the antenna part of electric charge, it comprises the first connection end and the second connection end；
Field-effect tube structure portion, including the structure being formed required for field effect transistor, and the grid of the field effect transistor being formed connects
First connection end of described antenna part；
Wherein, ILD test is carried out by the grid of the second connection end and field-effect tube structure portion, by field-effect tube structure portion
Grid, drain electrode, source electrode, substrate connection end carry out PID test.
2. the test structure that can be used for PID and ILD test according to claim 1 it is characterised in that：The thickness of described grid
Degree to be determined by the gate of the field effect transistor in the corresponding device layer of wafer.
3. the test structure that can be used for PID and ILD test according to claim 1 it is characterised in that：The field effect being formed
Should the type of pipe be determined by the type of the field effect transistor in the corresponding device layer of wafer.
4. according to claim 1 can be used for test structure that PID and ILD tests it is characterised in that also including：It is connected to
Protection tubular construction between described grid and ground.
5. the test structure that can be used for PID and ILD test according to claim 4 it is characterised in that：Described protection pipe knot
Structure is diode structure.
6. the test structure that can be used for PID and ILD test according to claim 1 it is characterised in that：Described can be used for
The test structure of PID and ILD test is arranged on the Cutting Road area in described wafer.
7. a kind of wafer, it includes multiple chip region and the Cutting Road area separating each chip region, and the feature of described wafer exists
In at least also including：
The test structure that can be used for PID and ILD test described at least one any one of claim 1 to 6；
Multiple electric connecting points, are arranged at top layer, each connect the second connection end that test structure comprised and
The grid of the field effect transistor that each test structure is each formed, the substrate connection end of drain electrode, source electrode and described field effect transistor
One of.
8. wafer according to claim 7 it is characterised in that：All electric connecting points are arranged at Cutting Road area.
9. wafer according to claim 8 it is characterised in that：Chip region comprises multilayer device layer, and Cutting Road area comprises
The number of plies is identical with the device number of plies, and each floor in Cutting Road area is respectively provided with least one test structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210530102.5A CN103872017B (en) | 2012-12-11 | 2012-12-11 | Test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210530102.5A CN103872017B (en) | 2012-12-11 | 2012-12-11 | Test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103872017A CN103872017A (en) | 2014-06-18 |
| CN103872017B true CN103872017B (en) | 2017-02-15 |
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| CN201210530102.5A Active CN103872017B (en) | 2012-12-11 | 2012-12-11 | Test structure that can be used for PID (Plasma Induced Damage) and ILD (Inter Layer Dielectric) tests and wafer |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752345A (en) * | 2008-12-17 | 2010-06-23 | 上海华虹Nec电子有限公司 | Test structure for semiconductor devices P2ID and SM |
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| GB2235587A (en) * | 1989-07-11 | 1991-03-06 | Volkswagen Ag | Janus antenna arrangement |
| US6417544B1 (en) * | 2001-06-11 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Diode-like plasma induced damage protection structure |
| CN101197300B (en) * | 2007-12-25 | 2011-11-09 | 上海宏力半导体制造有限公司 | PPID monitoring method in integrated circuit production process |
| CN101577266B (en) * | 2008-05-08 | 2012-01-25 | 台湾积体电路制造股份有限公司 | Monitoring and testing structure for plasma damage and evaluation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752345A (en) * | 2008-12-17 | 2010-06-23 | 上海华虹Nec电子有限公司 | Test structure for semiconductor devices P2ID and SM |
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| CN103872017A (en) | 2014-06-18 |
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