CN103871836A - Method for processing semiconductor chip - Google Patents
Method for processing semiconductor chip Download PDFInfo
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- CN103871836A CN103871836A CN201210533689.5A CN201210533689A CN103871836A CN 103871836 A CN103871836 A CN 103871836A CN 201210533689 A CN201210533689 A CN 201210533689A CN 103871836 A CN103871836 A CN 103871836A
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- semiconductor chip
- conditioned
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- finishing stove
- chip
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000012545 processing Methods 0.000 title claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 239000001257 hydrogen Substances 0.000 claims abstract description 15
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000003344 environmental pollutant Substances 0.000 claims abstract description 10
- 231100000719 pollutant Toxicity 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims description 31
- 230000001143 conditioned effect Effects 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 22
- 239000003595 mist Substances 0.000 claims description 17
- 239000002245 particle Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000001816 cooling Methods 0.000 claims description 4
- 238000011109 contamination Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910001873 dinitrogen Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- -1 and like this Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000013632 homeostatic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000010583 slow cooling Methods 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The invention discloses a method for processing a semiconductor chip. The method comprises that: pollutants attached on the semiconductor chip are removed so that the cleaned semiconductor chip is acquired; and the mixed gas meeting the first preset condition is piped into a finishing stove in which the cleaned semiconductor chip is positioned so that a dangling bond at the interface of a gate electrode oxide layer and poly-silicon in the semiconductor chip is adjusted into a silicon hydrogen bond, wherein the mixed gas comprises nitrogen and hydrogen.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of method of processing semiconductor chip.
Background technology
The transistor of metals-oxides-semiconductor structure is called for short MOS transistor, its structure comprises the metal utmost point and semiconductor end, there are source electrode and two selective doping regions of drain electrode on the both sides of the metal utmost point, between the metal utmost point and semiconductor end, separate by insulating oxide, wherein, insulating oxide is made up of silicon dioxide.
In metal-oxide-semiconductor, the atomic arrangement of silicon chip inside is in good order, and four valence electrons of each silicon atom are combined and are formed covalent bond structure with the valence electron of atom around.But after cutting action, the covalent bond of silicon chip surface terrace cut slice direction is destroyed, and makes outermost each atom of plane of crystal will have a unpaired electronics, has a unsaturated key, this key is called dangling bonds, and this unsaturated bond plays pendulum.
For the grid place of metal-oxide-semiconductor, because the interface of grid oxic horizon and polysilicon layer exists this undersaturated dangling bonds, be Si-key, in the time that metal-oxide-semiconductor is worked, positive/negative electric charge that grid making alive produces (or inner self electric charge) easily and Si-bond close/disconnect.Wherein, in conjunction with disconnection be a homeostasis process, and the process of this balance is vulnerable to the impact of the factors such as temperature light, and the factors such as temperature can directly affect the energy of electric charge, thereby affects the poised state of Si-key.
The applicant is realizing in the process of embodiment of the present invention technical scheme, at least finds to exist in prior art following technical problem:
If the poised state of Si-key is unstable, the voltage of grid oxic horizon is also just unstable so, causes the raceway groove strong inversion degree varies sample of metal-oxide-semiconductor, thereby affects channel current, and output voltage and electric current just have fluctuation.
And then the output voltage of chip and current fluctuation directly affect the service behaviour of chip compared with conference, cause the yield of product lower.
In the prior art, the way that improves product yield in line operation returning is not proposed.
Summary of the invention
One embodiment of the invention provides a kind of method of processing semiconductor chip, for solving due to output voltage and the lower technical problem of the excessive product yield causing of current fluctuation, by returning in line operation, utilization passes into the mist of hydrogen and nitrogen, make dangling bonds be adjusted into si-h bond, thereby reduced the fluctuation of semiconductor chip output voltage and electric current.Reach the technique effect that product yield is greatly improved.
On the one hand, the present invention, by the application's a embodiment, provides following technical scheme:
A method of processing semiconductor chip, comprising:
Remove the pollutant that semiconductor chip adheres to, obtain the semiconductor chip after cleaning;
Pass into and meet the first pre-conditioned mist toward putting in the finishing stove that has the semiconductor chip after described cleaning, so that the dangling bonds of grid oxic horizon in described semiconductor chip and polysilicon interface are adjusted into si-h bond, wherein, described mist comprises nitrogen and hydrogen.
Optionally, the pollutant that described removing semiconductor chip adheres to, specifically comprises:
Clean described semiconductor chip, stain with eliminating particle;
By the silicon chip of semiconductor chip described in preset rules attenuate, stain to remove back metal, obtain the semiconductor chip after cleaning.
Optionally, described, toward before passing in putting the finishing stove that has described semiconductor chip after clean and meeting the first pre-conditioned mist, described method also comprises:
Pass into and meet the second pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, so that the dusty gas in described finishing stove and particle are discharged to described finishing stove, make the semiconductor chip after described cleaning enter loading procedure.
Optionally, described in putting the finishing stove that has described semiconductor chip after clean, pass into meet the first pre-conditioned mist after, described method also comprises:
Pass into and meet the 3rd pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, the semiconductor chip after cleaning so that described enters uninstall process;
Pass into and meet the 4th pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, the semiconductor chip after cleaning so that described enters cooling procedure.
Optionally, the volume of described mist is specially 10 liters, and wherein, the ratio of hydrogen and nitrogen content is 4:96.
Optionally, described the first pre-conditioned being specially: the time of passing into is 60 minutes, temperature maintains 425 ℃.
Optionally, described the second pre-conditioned being specially: the time of passing into is 28.2 minutes, temperature is raised to 425 ℃ from 25 ℃.
Optionally, described the 3rd pre-conditioned being specially: the time of passing into is 28.2 minutes, temperature maintains 425 ℃.
Optionally, described the 4th pre-conditioned being specially: the time of passing into is 28.2 minutes, temperature drops to 25 ℃ from 425 ℃.
The one or more technical schemes that provide in the embodiment of the present invention, at least have following technique effect or advantage:
In the embodiment of the present invention, pass into and meet the first pre-conditioned mist toward putting in the finishing stove that has the semiconductor chip after cleaning, hydrogen bond is combined with dangling bonds, solve the existence due to dangling bonds, cause the unsettled technical problem of chip electrophysics characteristic, make the unsettled dangling bonds of grid oxic horizon and polysilicon interface in described chip be adjusted into stable si-h bond, thereby the electrophysics characteristic of chip reach stable.
And then because chip reaches stable electrophysics characteristic, the voltage of grid oxic horizon and channel current all become stable so, thereby the fluctuation of output voltage and electric current has obtained very large improvement, the value of tending towards stability.
And then, utilize the yield of the product that described chip manufacturing goes out to obtain significantly improving, can, from 60% raising 90%, reach client's requirement.
Accompanying drawing explanation
Fig. 1 is the flow chart of processing semiconductor chip method in one embodiment of the invention;
Fig. 2 is the structure chart of dangling bonds in semiconductor chip in one embodiment of the invention;
Fig. 3 is the flow chart of removing the pollutant process that semiconductor chip adheres in one embodiment of the invention;
Fig. 4 is the structure chart of si-h bond in semiconductor chip in one embodiment of the invention.
Embodiment
One embodiment of the invention provides a kind of method of processing semiconductor chip, for solving due to the lower technical problem of the large product yield causing of output voltage and current fluctuation, by returning in line operation, utilization passes into the mist of hydrogen and nitrogen, make dangling bonds be adjusted into si-h bond, thereby reduced the fluctuation of semiconductor chip output voltage and electric current.Reach the technique effect that product yield is greatly improved.
Technical scheme in the embodiment of the present invention is for addressing the above problem, and general thought is as follows:
The present invention is by passing into and meet the first pre-conditioned mist toward putting in the finishing stove that has the semiconductor chip after cleaning, hydrogen bond and silicon bond are closed, so that unsettled dangling bonds are adjusted into stable si-h bond, thereby reduce the fluctuation of output voltage and electric current, reached the technique effect that product yield is greatly improved.
In order better to understand technique scheme, below in conjunction with Figure of description and concrete execution mode, technique scheme is described in detail.
One embodiment of the invention provides a kind of method of processing semiconductor chip, be applied to and return in line operation, wherein, returning line operation refers to and completes after the manufacture of semiconductor chip, in the process that it is tested, find that described chip does not meet needs of expected design, now by undesirable chip is sent in workshop again, carry out correlation step operation, so that it reaches the designing requirement of expection.
The embodiment of the present invention adopts P<100>15-25OHM.CM substrate slice, because its boundary defect is little and interface state density is minimum, so dangling bonds are minimum.Certainly,, in concrete application, also can use P<110> substrate slice.Separately, the present embodiment adopts horizontal furnace tube operation, also can adopt vertical furnace tube operation, and according to different boards, the capacity of corresponding boiler tube is also different, and in the present invention, the permission capacity of boiler tube is 12.5L.
As shown in Figure 1, said method comprising the steps of:
Step 101: remove the pollutant that semiconductor chip adheres to, obtain the semiconductor chip after cleaning.
In specific embodiment, because semiconductor chip inside exists dangling bonds, as shown in Figure 2, this unsaturated bond is in labile state, and it has can trapped electron or the ability of other atoms.After chip manufacturing completes, to during again entering workshop, in the time of semiconductor chip described in the atom in surrounding environment or molecule convergence surperficial, can be subject to the attraction of surface atom, be adsorbed in chip surface, thereby chip is stain, pollute.So add man-hour when chip enters workshop again, first need to remove these pollutants, obtaining after clean semiconductor chip, just can enter boiler tube and carry out subsequent operation.Wherein, the contamination of these pollutants can be divided into organic impurities contamination, particle contaminant and metal ion contamination etc.The concrete process of removing as shown in Figure 3, comprising in embodiments of the present invention:
Step 301: clean described semiconductor chip, stain with eliminating particle;
In specific embodiment, can clean chip by alkaline cleaning fluid on the one hand, can use on the other hand the method for physics to utilize mechanical scrub or ultrasonic cleaning technology to remove the particle of particle diameter >=0.4 μ m, or utilize mega sonic wave to remove the particle of >=0.2 μ m.
Complete after the particle contaminant of removing chip surface, entering the implementation process of step 302: by the silicon chip of semiconductor chip described in preset rules attenuate, staiing to remove back metal, obtain the semiconductor chip after cleaning.
In specific embodiment, due in the test process of silicon chip, the test panel of its back contact is likely gold, and like this, metal contamination will, with gold atom, have been caused in the back of described silicon chip.Need in this case silicon chip to carry out attenuate, the scope of attenuate is at 10 μ m to best between 40 μ m, if the value of attenuate is too small, metal contamination can not guarantee to remove completely, if the value of attenuate is excessive, can have influence on follow-up encapsulation.Concrete attenuate degree will be determined according to the minimum thickness thinning of board, in the present embodiment to wafer thinning 30 μ m.
After completing steps 101, enter step 102: pass into and meet the second pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, so that the dusty gas in described finishing stove and particle are discharged to described finishing stove, make the semiconductor chip after described cleaning enter loading procedure.
In specific embodiment, the pure nitrogen gas that is 10L by volume passes in process furnace tube, and the time passing into is 28.2 minutes, and the temperature of finishing stove is slowly raised to 425 ℃ from 25 ℃.
In another embodiment, passing into the time can be also 29 minutes.Described pass into the time can be 28.2 minutes concrete left-right deviations 1 to 2 minute.
Said process is specially loading procedure, by completing steps 102, chip silicon chip environment is around in nitrogen atmosphere, and other may have influence on the pollutant of silicon chip quality to have got rid of oxygen and particle etc., get ready for performing step 103.
Step 103: pass into and meet the first pre-conditioned mist toward putting in the finishing stove that has the semiconductor chip after described cleaning, so that the dangling bonds of grid oxic horizon in described semiconductor chip and polysilicon interface are adjusted into si-h bond, wherein, described mist comprises nitrogen and hydrogen.
In specific embodiment, the cumulative volume that passes into the gas in process furnace tube is specially 10L, and wherein hydrogen content is 4%, and nitrogen content is 96%, and the time passing into is 60 minutes, and the temperature of finishing stove maintains 425 ℃.In concrete application, wherein, passing into hydrogen content in the 10L gas in process furnace tube can be also 5%, nitrogen content can be also 95%, the time passing into also can be 61 minutes, wherein, described in pass into the time can be 60 minutes concrete left-right deviations 1 to 2 minute.
Said process is specially the course of processing, by completing steps 103, and dangling bonds and Hydrogenbond, chip internal mechanism becomes stable si-h bond by unsettled dangling bonds, as shown in Figure 4, the electrophysics characteristic of described chip reaches stable, thereby the output voltage of chip and electric current tend towards stability.
After completing steps 103, enter step 104: pass into and meet the 3rd pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, the semiconductor chip after cleaning so that described enters uninstall process.
In specific embodiment, the pure nitrogen gas that is 10L by volume passes in process furnace tube, and the time passing into is 28.2 minutes, and the temperature of finishing stove maintains 425 ℃.
In another embodiment, passing into the time can be also 29 minutes.Described pass into the time can be 28.2 minutes concrete left-right deviations 1 to 2 minute.
Said process is specially uninstall process, by completing steps 104, makes the silicon chip of described chip return to the state in step 102, and silicon chip environment is around in nitrogen atmosphere.
Step 105: pass into and meet the 4th pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, the semiconductor chip after cleaning so that described enters cooling procedure.
In specific embodiment, the pure nitrogen gas that is 10L by volume passes in process furnace tube, and the time passing into is 28.2 minutes, and the temperature of finishing stove slowly drops to 25 ℃ from 425 ℃.
In another embodiment, passing into the time can be also 29 minutes.Described pass into the time can be 28.2 minutes concrete left-right deviations 1 to 2 minute.
Said process is specially cooling procedure, by completing steps 105, makes the silicon chip of described chip in the temperature identical with external environment.If do not carry out this Slow cooling process, silicon chip can be due to temperature shock, and heat radiation inequality causes fin or fragment, and semiconductor chip is damaged.
In addition, the mixed proportion of the dosage of the pure nitrogen gas that the present invention passes into, hydrogen and nitrogen, the time passing into and temperature, need to consider concrete crystal orientation of applying on the one hand, also will consider on the other hand the concrete coupling of board.
The one or more technical schemes that provide in the embodiment of the present invention, at least have following technique effect or advantage:
In the embodiment of the present invention, pass into and meet the first pre-conditioned mist toward putting in the finishing stove that has the semiconductor chip after cleaning, hydrogen bond is combined with dangling bonds, solve the existence due to dangling bonds, cause the unsettled technical problem of chip electrophysics characteristic, make the unsettled dangling bonds of grid oxic horizon and polysilicon interface in described chip be adjusted into stable si-h bond, thereby the electrophysics characteristic of chip reach stable.
And then because chip reaches stable electrophysics characteristic, the voltage of grid oxic horizon and channel current all become stable so, thereby the fluctuation of output voltage and electric current has obtained very large improvement, the value of tending towards stability.
And then, utilize the yield of the product that described chip manufacturing goes out to obtain significantly improving, can, from 60% raising 90%, reach client's requirement.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (9)
1. a method of processing semiconductor chip, is characterized in that, described method comprises:
Remove the pollutant that semiconductor chip adheres to, obtain the semiconductor chip after cleaning;
Pass into and meet the first pre-conditioned mist toward putting in the finishing stove that has the semiconductor chip after described cleaning, so that the dangling bonds of grid oxic horizon in described semiconductor chip and polysilicon interface are adjusted into si-h bond, wherein, described mist comprises nitrogen and hydrogen.
2. the method for claim 1, is characterized in that, the pollutant that described removing semiconductor chip adheres to, specifically comprises:
Clean described semiconductor chip, stain with eliminating particle;
By the silicon chip of semiconductor chip described in preset rules attenuate, stain to remove back metal, obtain the semiconductor chip after cleaning.
3. the method for claim 1, is characterized in that, described, toward before passing in putting the finishing stove that has described semiconductor chip after clean and meeting the first pre-conditioned mist, described method also comprises:
Pass into and meet the second pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, so that the dusty gas in described finishing stove and particle are discharged to described finishing stove, make the semiconductor chip after described cleaning enter loading procedure.
4. the method for claim 1, is characterized in that, described in putting the finishing stove that has described semiconductor chip after clean, pass into meet the first pre-conditioned mist after, described method also comprises:
Pass into and meet the 3rd pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, the semiconductor chip after cleaning so that described enters uninstall process;
Pass into and meet the 4th pre-conditioned nitrogen toward putting in the finishing stove that has the semiconductor chip after described cleaning, the semiconductor chip after cleaning so that described enters cooling procedure.
5. the method for claim 1, is characterized in that, the volume of described mist is specially 10 liters, and wherein, the ratio of hydrogen and nitrogen content is 4:96.
6. the method for claim 1, is characterized in that, described the first pre-conditioned being specially: the time of passing into is 60 minutes, and temperature maintains 425 ℃.
7. method as claimed in claim 3, is characterized in that, described the second pre-conditioned being specially: the time of passing into is 28.2 minutes, and temperature is raised to 425 ℃ from 25 ℃.
8. method as claimed in claim 4, is characterized in that, described the 3rd pre-conditioned being specially: the time of passing into is 28.2 minutes, and temperature maintains 425 ℃.
9. method as claimed in claim 4, is characterized in that, described the 4th pre-conditioned being specially: the time of passing into is 28.2 minutes, and temperature drops to 25 ℃ from 425 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210533689.5A CN103871836A (en) | 2012-12-11 | 2012-12-11 | Method for processing semiconductor chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210533689.5A CN103871836A (en) | 2012-12-11 | 2012-12-11 | Method for processing semiconductor chip |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697195A (en) * | 1992-09-11 | 1994-04-08 | Seiko Epson Corp | Manufacture of semiconductor device |
| US20050202652A1 (en) * | 2004-03-15 | 2005-09-15 | Sharp Laboratories Of America, Inc. | High-density plasma hydrogenation |
| CN102194869A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Ultra-steep reverse doped metal oxide semiconductor (MOS) device with improved anti-irradiation property |
-
2012
- 2012-12-11 CN CN201210533689.5A patent/CN103871836A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697195A (en) * | 1992-09-11 | 1994-04-08 | Seiko Epson Corp | Manufacture of semiconductor device |
| US20050202652A1 (en) * | 2004-03-15 | 2005-09-15 | Sharp Laboratories Of America, Inc. | High-density plasma hydrogenation |
| CN102194869A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Ultra-steep reverse doped metal oxide semiconductor (MOS) device with improved anti-irradiation property |
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