CN103871467A - Gate pole control voltage generation circuit - Google Patents
Gate pole control voltage generation circuit Download PDFInfo
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- CN103871467A CN103871467A CN201210532474.1A CN201210532474A CN103871467A CN 103871467 A CN103871467 A CN 103871467A CN 201210532474 A CN201210532474 A CN 201210532474A CN 103871467 A CN103871467 A CN 103871467A
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Abstract
The invention discloses a gate pole control voltage generation circuit. A reference current is generated through an operational amplifier, an image current I3 generated by a mirror image flows through a third resistor to generate a reference voltage. An intrinsic NMOS tube working in a saturation area generates a required gate pole control voltage. A third P-type transistor, a first N-type transistor and a second N-type transistor are additionally arranged to generate an image current I4, and the image current I4 flows through a fourth resistor to form a pressure drop between two ends of the fourth resistor in order to make the intrinsic NMOS tube N3 with a negative threshold voltage work in the saturation area. The circuit has a same voltage references generation function with a traditional circuit, and enables the intrinsic NMOS tube with the negative threshold voltage to work in the saturation area, so the mirror image of the intrinsic NMOS tube can effectively realize the clamping effect of a BL potential.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit) manufacturing equipment, particularly relate to a kind of clamped circuit gate pole control voltage generation circuit.
Background technology
In non-easily large property memory integrated circuit, the impact (read disturb) on storage unit performance when reducing read operation, need to limit the current potential of BL (Bit Line, bit line), therefore needs a clamped circuit.The method of general clamped BL voltage is to increase by an intrinsic N-type transistor in SA (Sense Amplifier, sense amplifier) circuit, carrys out clamped BL voltage, as shown in Figure 1 by restriction gate leve control signal (vlim).Be in non-negative technique at the threshold voltage of traditional intrinsic NMOS tube, the generation circuit of gate pole control voltage (vlim) as shown in Figure 2; A reference voltage Vref of negative input end input of operational amplifier, the grid of the input end of operational amplifier, the grid of transistor P1, transistor P2 is connected, the source electrode of transistor P1 is connected with the source electrode of transistor P2 on external voltage (VDD), the drain electrode of transistor P1 is connected with the positive input terminal of operational amplifier by a resistance R 2, form feedback (fdbk), one end of resistance R 1 is connected with the positive input terminal of operational amplifier, other end ground connection; The drain electrode of transistor P2 is connected with drain electrode and the grid of intrinsic NMOS tube N1, and as gate pole control voltage (vlim), the source electrode of intrinsic NMOS tube N1 is by resistance R 3 ground connection.Wherein transistor P1, P2 are PMOS pipe, and the width of transistor P1 is N: M with the ratio of the width of transistor P2, and N, M are greater than 0 number.
Its principle of work is: the FEEDBACK CONTROL by operational amplifier produces reference current I1 (I1=Vref/R1), mirror image produces I2 (I2=I1*M/N) again, therefore v (vlim_bl)=I2*R3=Vref* (M/N) * (R3/R1), wherein v (vlim_bl) is a reference voltage, then the intrinsic NMOS tube N1 being directly connected with drain electrode by gate pole produces needed gate pole control voltage vlim in SA.V (BL) current potential equals v (vlim_bl) current potential substantially like this, gets the effect of clamped BL current potential.
But in the threshold voltage of intrinsic NMOS tube N1 is negative technique, such gate pole control voltage is just inapplicable, reason is: after N1 pipe gate pole is directly connected with drain electrode, N1 pipe works in linear zone, v (BL) > v (vlim) > v (vlim_bl) may be there is like this, the effect of clamped BL current potential cannot be got.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of gate pole control voltage generation circuit, can be at intrinsic NMOS tube threshold voltage when negative, in read procedure, BL current potential is carried out effectively clamped, thereby improve the impact of reading storage unit.
For solving the problems of the technologies described above, a kind of gate pole control voltage generation circuit provided by the invention, comprise: a P transistor npn npn, the 2nd P transistor npn npn, the 3rd P transistor npn npn, the first N-type transistor, the second N-type transistor, the 3rd N-type transistor and operational amplifier, a wherein reference voltage of the negative input end of operational amplifier input, the output terminal of operational amplifier, the grid of the one P transistor npn npn, the grid of the grid of the 2nd P transistor npn npn and the 3rd P transistor npn npn is connected, the source electrode of the one P transistor npn npn, the source electrode of the source electrode of the 2nd P transistor npn npn and the 3rd P transistor npn npn is connected on external voltage, the drain electrode of the one P transistor npn npn is connected with the positive input terminal of operational amplifier by second resistance, form feedback, one end of the first resistance is connected with the positive input terminal of operational amplifier, other end ground connection, the drain electrode of the 2nd P transistor npn npn is joined with the transistorized drain electrode of the 3rd N-type and is passed through the 4th resistance and is connected with the transistorized grid of the 3rd N-type and the transistorized drain electrode of the second N-type, the transistorized grid of the 3rd N-type is drawn a road as gate pole control voltage, and the transistorized source electrode of the 3rd N-type is by a resistance eutral grounding.The drain electrode of the 3rd P transistor npn npn is connected with the transistorized drain electrode of the first N-type, the transistorized grid of the first N-type, the transistorized grid of the second N-type, the transistorized source electrode of the first N-type, the connected ground connection of the transistorized source electrode of the second N-type.
Further, the dimension width of a described P transistor npn npn is N: L with the ratio of the dimension width of described the 2nd P transistor npn npn and the dimension width of described the 3rd P transistor npn npn: (M+L), wherein M, L, N are greater than 0 number.
Further, stating the transistorized dimension width of the first N-type is A: B with the ratio of described the second N-type transistor size width, and wherein A, B are greater than 0 number.
Further, the transistorized dimension width of described the first N-type equates with described the second N-type transistor size width, i.e. A=B.
Gate pole control voltage generation circuit of the present invention, realize the function of the generation reference voltage the same with traditional circuit, make the intrinsic NMOS tube of negative threshold voltage work in saturation region simultaneously, can effectively realize so the clamped effect of BL current potential by the mirror image of intrinsic NMOS tube.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 be commonly use with clamped SA circuit diagram;
Fig. 2 is traditional gate pole control voltage generation circuit figure;
Fig. 3 is gate pole control voltage generation circuit figure of the present invention.
Embodiment
For your auditor can be had a better understanding and awareness object of the present invention, feature and effect, below coordinate accompanying drawing describe in detail as after.
As shown in Figure 2, a reference voltage Vref of negative input end input of operational amplifier, the output terminal of operational amplifier, the grid of the one P transistor npn npn P1, the grid of the grid of the 2nd P transistor npn npn P2 and the 3rd P transistor npn npn P3 is connected, the source electrode of the one P transistor npn npn P1, the source electrode of the source electrode of the 2nd P transistor npn npn P2 and the 3rd P transistor npn npn P3 is connected on external voltage (VDD), the drain electrode of the one P transistor npn npn P1 is connected with the positive input terminal of operational amplifier by second resistance R 2, form feedback (fdbk), first one end of resistance R 1 and the positive input terminal of operational amplifier are connected, other end ground connection, the drain electrode of the 2nd P transistor npn npn P2 is joined with the drain electrode of the 3rd N-type transistor N3 and is passed through the 4th resistance R 4 and is connected with the grid of the 3rd N-type transistor N3 and the drain electrode of the second N-type transistor N2, the grid of the 3rd N-type transistor N3 is drawn a road as gate pole control voltage (vlim), and the source electrode of the 3rd N-type transistor N3 is by resistance R 3 ground connection.The drain electrode of the drain electrode of the 3rd P transistor npn npn P3 and the first N-type transistor N1, the grid of the first N-type transistor N1, the grid of the second N-type transistor N2 is connected, the source electrode of the first N-type transistor N1, the connected ground connection of source electrode of the second N-type transistor N2, wherein the 3rd N-type transistor N3 is intrinsic NMOS tube, the dimension width of the one P transistor npn npn P1 is N: L: (M+L) with the ratio of the dimension width of the 2nd P transistor npn npn P2 and the dimension width of the 3rd P transistor npn npn P3, wherein N, M, L is greater than 0 number, the dimension width of the first N-type transistor N1 is A: B with the ratio of the second N-type transistor N2 dimension width, wherein A, B is greater than 0 number, preferred A=B.
The principle of work of clamped circuit gate pole control voltage generation circuit of the present invention is: produce a reference current I1 by operational amplifier, mirror image generation Liao Yi road image current I3 flows through R3 and produces a reference voltage v (vlim_bl).Then produce needed gate pole control voltage vlim by the intrinsic N pipe that works in saturation region.Wherein, produce Liao Yi road image current I4 by having increased P3/N1/N2, the R4 that flows through, makes R4 two ends produce pressure drop, thereby makes the intrinsic NMOS tube N3 of negative threshold voltage work in saturation region.Like this by the effectively BL current potential in clamper SA circuit of vlim current potential producing.
Wherein, require I4*R4 >-vth, for intrinsic NMOS transistor N1:
Vds＝Vgs+I4*R4＞Vgs-vth
Wherein vds is the voltage difference of drain electrode and source electrode, and vgs is the voltage difference of grid and source electrode, and vth is threshold voltage, and therefore N1 works in saturation region
Simultaneously:
I1＝Vref/R1，
I2＝I1*(M+L)/N，
I4＝I1*(L/N)*B/A＝I1*L/N*B/A
Therefore suppose A=B,
I3＝I2-I4＝I1*(M+L)/N-I1*L/N＝I1*M/N
v(vlim_bl)＝I3*R3＝Vref*(M/N)*(R3/R1)
Can be by regulating P1, P2, P3, N1, the dimension width of N2 and the resistance of resistance R 3 and R1 to regulate the size of v (vlim_bl), the present invention has realized the function of the generation vlim_bl reference voltage the same with traditional circuit, make the intrinsic NMOS tube of negative threshold voltage work in saturation region simultaneously, can effectively realize so the clamped effect of BL current potential by the mirror image of intrinsic NMOS tube.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a gate pole control voltage generation circuit, it is characterized in that, comprise: a P transistor npn npn, the 2nd P transistor npn npn, the 3rd P transistor npn npn, the first N-type transistor, the second N-type transistor, the 3rd N-type transistor and operational amplifier, a wherein reference voltage of the negative input end of operational amplifier input, the output terminal of operational amplifier, the grid of the one P transistor npn npn, the grid of the grid of the 2nd P transistor npn npn and the 3rd P transistor npn npn is connected, the source electrode of the one P transistor npn npn, the source electrode of the source electrode of the 2nd P transistor npn npn and the 3rd P transistor npn npn is connected on external voltage, the drain electrode of the one P transistor npn npn is connected with the positive input terminal of operational amplifier by second resistance, form feedback, one end of the first resistance is connected with the positive input terminal of operational amplifier, other end ground connection, the drain electrode of the 2nd P transistor npn npn is joined with the transistorized drain electrode of the 3rd N-type and is passed through the 4th resistance and is connected with the transistorized grid of the 3rd N-type and the transistorized drain electrode of the second N-type, the transistorized grid of the 3rd N-type is drawn a road as gate pole control voltage, and the transistorized source electrode of the 3rd N-type is by a resistance eutral grounding.The drain electrode of the 3rd P transistor npn npn is connected with the transistorized drain electrode of the first N-type, the transistorized grid of the first N-type, the transistorized grid of the second N-type, the transistorized source electrode of the first N-type, the connected ground connection of the transistorized source electrode of the second N-type.
2. gate pole control voltage generation circuit as claimed in claim 1, it is characterized in that, the dimension width of a described P transistor npn npn is N: L with the ratio of the dimension width of described the 2nd P transistor npn npn and the dimension width of described the 3rd P transistor npn npn: (M+L), wherein M, L, N are greater than 0 number.
3. gate pole control voltage generation circuit as claimed in claim 1, is characterized in that, the transistorized dimension width of described the first N-type is A: B with the ratio of described the second N-type transistor size width, and wherein A, B are greater than 0 number.
4. gate pole control voltage generation circuit as claimed in claim 3, is characterized in that, the transistorized dimension width of described the first N-type equates with described the second N-type transistor size width, i.e. A=B.
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| CN201210532474.1A CN103871467B (en) | 2012-12-11 | 2012-12-11 | Gate pole control voltage generation circuit |
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| CN201210532474.1A CN103871467B (en) | 2012-12-11 | 2012-12-11 | Gate pole control voltage generation circuit |
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| CN103871467B CN103871467B (en) | 2017-08-08 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106875964A (en) * | 2017-02-08 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Sense amplifier clamp circuit with feedback function |
| CN111739576A (en) * | 2020-06-30 | 2020-10-02 | 西安易朴通讯技术有限公司 | Power supply bias voltage adjusting device, power supply device and electronic equipment |
| CN116865740A (en) * | 2023-08-31 | 2023-10-10 | 苏州锴威特半导体股份有限公司 | Analog multiplier circuit |
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| CN102156506A (en) * | 2010-02-11 | 2011-08-17 | 半导体元件工业有限责任公司 | Circuits and methods of producing a reference current or voltage |
| CN102194520A (en) * | 2010-03-11 | 2011-09-21 | 索尼公司 | Control voltage generation circuit and nonvolatile storage device having the same |
| CN102520756A (en) * | 2011-12-28 | 2012-06-27 | 南京邮电大学 | Bias current generating circuit |
| CN102594109A (en) * | 2011-01-05 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Current-limiting comparison circuit |
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2012
- 2012-12-11 CN CN201210532474.1A patent/CN103871467B/en active Active
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| CN1779861A (en) * | 2004-11-24 | 2006-05-31 | 上海华虹Nec电子有限公司 | Word-line boosting circuit for low-voltage non-volatile memory |
| US20090091995A1 (en) * | 2007-10-09 | 2009-04-09 | Hong-Ping Tsai | Sense amplifier circuit having current mirror architecture |
| CN102156506A (en) * | 2010-02-11 | 2011-08-17 | 半导体元件工业有限责任公司 | Circuits and methods of producing a reference current or voltage |
| CN102194520A (en) * | 2010-03-11 | 2011-09-21 | 索尼公司 | Control voltage generation circuit and nonvolatile storage device having the same |
| CN102594109A (en) * | 2011-01-05 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Current-limiting comparison circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106875964A (en) * | 2017-02-08 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Sense amplifier clamp circuit with feedback function |
| CN111739576A (en) * | 2020-06-30 | 2020-10-02 | 西安易朴通讯技术有限公司 | Power supply bias voltage adjusting device, power supply device and electronic equipment |
| CN116865740A (en) * | 2023-08-31 | 2023-10-10 | 苏州锴威特半导体股份有限公司 | Analog multiplier circuit |
| CN116865740B (en) * | 2023-08-31 | 2023-11-10 | 苏州锴威特半导体股份有限公司 | Analog multiplier circuit |
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