CN103843122B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN103843122B
CN103843122B CN201180073865.5A CN201180073865A CN103843122B CN 103843122 B CN103843122 B CN 103843122B CN 201180073865 A CN201180073865 A CN 201180073865A CN 103843122 B CN103843122 B CN 103843122B
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China
Prior art keywords
source
lead
semiconductor chip
junction type
mosfet
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CN201180073865.5A
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Chinese (zh)
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CN103843122A (en
Inventor
金泽孝光
秋山悟
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to CN201710264506.7A priority Critical patent/CN107104057B/en
Publication of CN103843122A publication Critical patent/CN103843122A/en
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Power Conversion In General (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Inverter Devices (AREA)
  • Electronic Switches (AREA)
  • Wire Bonding (AREA)

Abstract

A kind of technology of the reliability that can improve semiconductor device is provided.In the present invention, it is formed in semiconductor chip（CHP1）Surface gate pads（GPj）With compared to other leads（Drain lead（DL）And grid lead（GL））Closer to source lead（SL）Mode configure.Its result is, in accordance with the invention it is possible to shorten gate pads（GPj）With source lead（SL）The distance between, therefore, it is possible to shorten connection gate pads（GPj）And source lead（SL）Wire（Wgj）Length.It follows that in accordance with the invention it is possible to fully reducing being present in wire（Wgj）Stray inductance.

Description

Semiconductor device
Technical field
The present invention relates to semiconductor device, more particularly to suitable for the inverter for example in air-conditioning, the DC/ of computer power supply Effective skill of the power semiconductor used in inverter module of DC transducers, hybrid vehicle or electric automobile etc. Art.
Background technology
In Japanese Unexamined Patent Application Publication 2000-506313 publication（Patent documentation 1）Described in be provided with one kind while realizing low conducting The technology of the switch element of resistance and high withstand voltage.Specifically, recorded to carborundum in patent documentation 1（SiC）For material The junction type FET of material（Junction Field Effect Transistor：Junction field effect transistor）With with silicon（Si）For material The MOSFET of material（Metal Oxide Semiconductor Field Effect Transistor：MOS field-effect crystal Pipe）Cascaded（cascode）The structure of connection.
In Japanese Unexamined Patent Publication 2008-198735 publications（Patent documentation 2）In recorded following structure：In order to provide low conducting The element of voltage and high withstand voltage, the FET with SiC as material and the Diode series with Si as material are connected.
In Japanese Unexamined Patent Publication 2002-208673 publications（Patent documentation 3）In recorded and be constructed as below：In order to cut down power mould The area of block, makes switch element and diode be laminated across flat board connection terminal.
In Japanese Unexamined Patent Publication 2010-206100 publications（Patent documentation 4）In record it is normal with SiC as material by improving The threshold voltage of the junction type FET of closed form is preventing the technology of overdue arc.Specifically, on sic substrates configure junction type FET and MOSFET, and MOSFET is connected with diode fashion on the gate electrode of junction type FET.
Prior art literature
Patent documentation
Patent documentation 1：Japanese Unexamined Patent Application Publication 2000-506313 publication
Patent documentation 2：Japanese Unexamined Patent Publication 2008-198735 publications
Patent documentation 3：Japanese Unexamined Patent Publication 2002-208673 publications
Patent documentation 4：Japanese Unexamined Patent Publication 2010-206100 publications
The content of the invention
As the switch element for realizing that pressure raising and conducting resistance are reduced simultaneously, there is opening using cascade Connection mode Close element.Band gap will e.g. have been used using the switch element of cascade Connection mode（band gap）Compare silicon（Si）Big material Open type junction type FET（Junction Field Effect Transistor）, and used silicon（Si）Closed type MOSFET（Metal Oxide Semiconductor Field Effect Transistor）The structure being connected in series.According to The switch element of the cascade Connection mode, can be pressure to guarantee by the pressure big junction type FET that insulate, also, based on normally opened The junction type FET of type and reduce conducting resistance, reduce conducting resistance based on low pressure MOSFET, thereby, it is possible to obtain The switch element that pressure raising and conducting resistance are reduced is realized simultaneously.
In the mounting structure of the switch element of the cascade Connection, employ and junction type will be formed with by welding lead The semiconductor chip of FET and it is formed with the structure that the semiconductor chip of MOSFET is coupled together.The present inventor's new discovery, in the knot In the case of structure, the impact of the stray inductance due to being present in welding lead, the impact of the leakage current of junction type FET are being opened Guan Shi, can cause the voltage for designing pressure above size is applied between the source electrode of low pressure MOSFET and drain electrode.As this When sample, voltage more than design is applied with low pressure MOSFET is pressure, MOSFET may be breakdown, so as to cause partly The reliability decrease of conductor device.
It is an object of the invention to provide a kind of technology of the reliability that can improve semiconductor device.
The above-mentioned and other purposes and novel feature of the present invention can be become clear from from the description of this specification and accompanying drawing.
The summary of the representative scheme in invention disclosed herein is illustrated, it is as described below.
The semiconductor device of one embodiment is characterised by that the grid for being formed with the semiconductor chip of junction type FET is welded Disk with other leads（Grid lead and drain lead）The mode compared closer to source lead is configured.
Invention effect
The effect that simple declaration is obtained according to the representative scheme in invention disclosed herein, following institute State.
According to an embodiment, it is possible to increase the reliability of semiconductor device.In addition, semiconductor device can be realized The raising of electrical characteristics.
Description of the drawings
Fig. 1 is the circuit structure diagram for representing the switch element for employing cascade Connection mode.
Fig. 2's（a）It is the circuit for representing the inverter that the junction type FET and MOSFET of cascade Connection are used as switch element Figure.Fig. 2's（b）It is the figure of the waveform in the case of representing the switching elements ON of composition upper branch road, Fig. 2's（c）It is to represent The figure of the waveform in the case that the switch element for constituting upper branch road is disconnected.
Fig. 3 is the mounting structure figure of the semiconductor device for representing embodiments of the present invention 1.
Fig. 4 is the mounting structure figure of other semiconductor device for representing embodiment 1.
Fig. 5 is the mounting structure figure of the semiconductor device for representing variation 1.
Fig. 6 is the mounting structure figure of other semiconductor device for representing variation 1.
Fig. 7 is the mounting structure figure of other semiconductor device for representing variation 1.
Fig. 8 is the sectional view in a section for representing Fig. 7.
Fig. 9 is the mounting structure figure of other semiconductor device for representing variation 1.
Figure 10 is the sectional view in a section for representing Fig. 9.
Figure 11 is the mounting structure figure of other semiconductor device for representing variation 1.
Figure 12's（a）It is the circuit diagram of the existence position of the switch element and stray inductance that represent prior art, Figure 12's （b）It is the circuit diagram of the existence position of the switch element and stray inductance that represent embodiment 1.In addition, Figure 12（c）It is to represent The circuit diagram of the existence position of the switch element and stray inductance of this variation 1.
Figure 13 is the mounting structure figure of the semiconductor device for representing variation 2.
Figure 14 is the sectional view in a section for representing Figure 13.
Figure 15 is the mounting structure figure of other semiconductor device for representing variation 2.
Figure 16 is the sectional view in a section for representing Figure 15.
Figure 17 is the mounting structure figure of the semiconductor device for representing variation 3.
Figure 18 is the sectional view in a section for representing Figure 17.
Figure 19 is the mounting structure figure of other semiconductor device for representing variation 3.
Figure 20 is the sectional view in a section for representing Figure 19.
Figure 21 is the mounting structure figure of the semiconductor device for representing variation 4.
Figure 22 is the sectional view in a section for representing Figure 21.
Figure 23 is the mounting structure figure of other semiconductor device for representing variation 4.
Figure 24 is the sectional view in a section for representing Figure 23.
Figure 25 is the structure chart of the laminated semiconductor chip for representing embodiment 2.
Figure 26 is the figure of the other structures of the laminated semiconductor chip for representing embodiment 2.
Figure 27 is the sectional view of cutting at the line A-A of Figure 25 and Figure 26.
Figure 28 is the structure chart of the laminated semiconductor chip for representing variation.
Figure 29 is the figure of the other structures of the laminated semiconductor chip for representing variation.
Figure 30 is the sectional view of cutting at the line A-A of Figure 28 and Figure 29.
Figure 31 is the sectional view of the device configuration of the MOSFET for representing embodiment 2.
Figure 32 is the figure of the current path in the switch element for represent cascade Connection.Figure 32's（a）It is to represent connection When current path figure, Figure 32's（b）It is the figure of the current path of the leakage current flowed when representing disconnection.
Figure 33 is the sectional view of the device configuration of the junction type FET for representing embodiment 2.
Figure 34 is the sectional view of other device configurations of the junction type FET for representing embodiment 2.
Specific embodiment
In the following embodiments, for convenience, it is divided into some if necessary or embodiment is illustrated, but It, in addition to situation about especially expressing, is not what is had no bearing between them to be, but a side is the part or all of of the opposing party The relation such as variation, detailed, supplementary notes.
In addition, in the following embodiments, it is related to number of key element etc.（Comprising number, numerical value, amount, scope etc.）Situation Under, except situation of certain number etc. being expressly defined in the situation and principle especially expressed, be not limited to the certain number, can be special It more than fixed number can also be below certain number.
And, in the following embodiments, its structural element（Also comprising key element step etc.）Except situation about especially expressing with And think it is clearly necessary situation etc. in principle, need not to be certainly necessary.
Similarly, in the following embodiments, when being related to shape, position relationship of structural element etc. etc., except especially bright Situation about showing and think clearly invalid situation etc. in principle, also comprising substantially approximate with its shape etc. or similar feelings Condition etc..With regard to this point, above-mentioned numerical value and scope are also same.
In addition, in the whole accompanying drawings for illustrating embodiment, marking identical accompanying drawing in principle to identical part Labelling, and omit its explanation for repeating.Additionally, there are for ease of understanding accompanying drawing and be also labelled with hatching in a top view Situation.
（Embodiment 1）
The details ＞ of the technical task had found by ＜ the present inventor
In environment this great society trend of preserving our planet, the importance for reducing the electronic utility of environmental pressure gradually increases Plus.Wherein, power device（Power semiconductor）For rolling stock, hybrid vehicle, the inverter of electric automobile or The power supply of the civil equipments such as the inverter of air-conditioning, computer, the performance improvement of power device is for basic system and civil equipment Electrical efficiency improve tool and have very great help.Improve the energy money that electrical efficiency is meant to required for the work of reduction system Source, in other words, can cut down the discharge capacity of carbon dioxide, i.e. can reduce environmental pressure.Therefore, it is prevailing right in each company The research and development of the performance improvement of power device.
Generally, power device and large scale integrated circuit（LSI（Large Scale Integration））Similarly, with Silicon is material.But, in recent years, the band gap carborundum bigger than silicon（SiC）Just receive publicity.SiC is larger due to band gap, so absolutely Edge punctures pressure 10 times or so for silicon.It follows that the device with SiC as material can compared with the device with Si as material Make thickness relatively thin, its result is that resistance value during conducting is greatly reduced（Conduction resistance value）Ron.Therefore, with SiC as material The device of material can significantly cut down the conduction loss (Ron × i of the product representation with resistance value Ron Yu conducting electric current i2), can be right The improvement tool of electrical efficiency has very great help.It is conceived to such feature, at home and abroad, using bis- pole of MOSFET, Xiao Te of SiC The exploitation of pipe and junction type FET develops.
Especially, it is conceived to switching device, the junction type FET with SiC as material（JFET）Commercialization develop rapidly.The knot Type FET compared with the MOSFET with SiC as material, for example, due to the gate insulating film that need not be made up of silicon oxide film, so Can avoid with the defect on the interface of silicon oxide film and SiC and element characteristic associated therewith deteriorating the problem as representative.Separately Outward, junction type FET can control the on/off grown to control raceway groove of the depletion layer based on pn-junction, therefore, it is possible to easily divide Open the junction type FET of the junction type FET and open type that make closed type.Like this, the junction type FET with SiC as material with SiC as material The MOSFET of material is compared, also excellent in terms of long-term reliability, in addition, the feature with easy making devices.
In the junction type FET with SiC as material, the junction type FET of open type generally also makes raceway groove turn on and streaming current, When needing to make channel cutoff, negative voltage is applied to gate electrode, make depletion layer from pn-junction grow and by channel cutoff.Therefore, in knot In the case that type FET is damaged because of some reasons, raceway groove is in the conduction state and electric current constant flow.Generally, from safety（Therefore Barrier protection：fail safe）From the viewpoint of, expect not making electric current flowing in the case where junction type FET is damaged, but in open type Junction type FET in, even if the electric current also constant flow in the case where junction type FET is damaged, so purposes is limited to.Therefore, from From the viewpoint of error protection, the junction type FET of closed type is expected.
But, the junction type FET of closed type has following technical task.That is, the gate electrode of junction type FET and source region difference With by p-type semiconductor region（Gate electrode）And n-type semiconductor region（Source region）The pn-junction diode configuration of composition, because This, when the voltage between gate electrode and source region is 3V or so, the parasitic diode between gate electrode and source region is led It is logical.Its result is there is the flowing between gate electrode and source region to have the situation of high current, thus, causes junction type FET excessive Heating and may be breakdown.It follows that the switch element in order to junction type FET to be used as closed type, expects to limit grid voltage It is made as the low-voltage of 2.5V or so, and two in the state of parasitic diode is not turned on or between gate electrode and source region It is used in the state of pole pipe electric current is fully little.Additionally, in the common MOSFET with Si as material, apply 0 to 15V or The grid voltage of 20V or so.Therefore, for the junction type FET using closed type, need the raster data model electricity in existing MOSFET On the basis of road, the reduction voltage circuit of the voltage for generating 2.5V or so is added（DC/DC transducers）, and level shifting circuit etc..Should The additional cost increase that system can be caused overall of design alteration, i.e. part.It can thus be appreciated that, although junction type FET is with long-term The feature of excellent and easy to manufacture in terms of reliability, but due to drive grid voltage it is significantly different with common MOSFET, institute In the case where newly junction type FET is utilized, to need the larger design alteration comprising drive circuit etc., accordingly, there exist system The technical task of overall cost increase.
, there is cascade Connection mode in the method as the technical task is solved.The cascade Connection mode refers to and with SiC will be In the way of the junction type FET of the open type of material and the low pressure MOSFET by Si as material are connected in series.When being connected using such When connecing mode, gate driver circuit drives low pressure MOSFET, therefore need not change gate driver circuit.On the other hand, leak Pressure between pole and source electrode can be determined by the characteristic of junction type FET of insulation high pressure.And, carrying out cascade Connection In the case of, as the low on-resistance of the low on-resistance and low pressure MOSFET of junction type FET is connected in series, so also can be by The conducting resistance of the switch element of cascade Connection suppresses less.Like this, cascade Connection mode has and often can solve the problem that The probability of the problem points of the junction type FET of closed form.
Fig. 1 is the circuit structure diagram for representing the switch element for employing cascade Connection mode.As shown in figure 1, employing level The switch element of connection connected mode is the junction type FETQ1 and closed type that open type is connected in series between source S and drain D The structure of MOSFETQ2.Specifically, junction type FETQ1 is configured with drain D side, be configured with MOSFETQ2 in source S side.Also It is to say, source S j of junction type FETQ1 is connected with drain D m of MOSFETQ2, source S m of MOSFETQ2 and the source electrode of switch element S connects.In addition, the gate electrode Gj of junction type FETQ1 is connected with the source S of switch element, the gate electrode Gm of MOSFETQ2 and grid Drive circuit（It is not shown）Connection.
Additionally, as shown in figure 1, being connected with fly-wheel diode with MOSFETQ2 reverse parallel connections.The fly-wheel diode has Make reverse current backflow and the exergonic function in inductance will be accumulated.That is, in the switch element shown in Fig. 1 and comprising inductance Load connect in the case of, when switch element is disconnected, the inductance due to being contained in load is produced and the electricity of MOSFETQ2 Stream flow direction is rightabout reverse current.It follows that by two pole of afterflow is arranged with MOSFETQ2 reverse parallel connections Pipe, makes reverse current backflow and discharges the energy accumulated in inductance.
Such connected mode is cascade Connection mode, according to the switch element for employing cascade Connection mode, first, grid Pole drive circuit（It is not shown）The gate electrode Gm of MOSFETQ2 is driven, advantages below is accordingly, there exist：It is not needed upon MOSFET The change that monomer is used as the situation of switch element and carries out to gate driver circuit.
It is additionally, since junction type FETQ1 and compares silicon using band gap（Si）It is big with carborundum（SiC）For represent material as material Material, so the pressure increase of the insulation of junction type FETQ1.It follows that the switch element of cascade Connection is pressure main by tying The characteristic of type FETQ1 is determined.Therefore, it is possible to the resistance to pressure ratio of insulation for making to require the MOSFETQ2 being connected in series with junction type FETQ1 Switch element using MOSFET monomers is low.That is, even if in the case where needing insulation pressure as switch element, it is also possible to Will be low pressure（For example, tens of V or so）MOSFET be used as MOSFETQ2.Therefore, it is possible to reduce the conducting resistance of MOSFETQ2. It is additionally, since junction type FETQ1 to be made up of the junction type FET of open type, so can also reduce the conducting resistance of junction type FETQ1.Its As a result it is, according to the switch element of cascade engagement, there is the design alteration for not needing gate driver circuit, and And, the reduction guaranteed with conducting resistance of insulation patience can be realized simultaneously, thereby, it is possible to seek semiconductor element（Switch unit Part）Electrical characteristics raising.
In addition, as shown in figure 1, the junction type FETQ1 of cascade Connection for open type junction type FETQ1, junction type FETQ1 grid electricity Pole Gj is electrically connected with the source S of switch element.Its result is that the voltage between the gate electrode Gj of junction type FETQ1 and source S is being opened Guan Shi（During conducting）Also will not forward bias.It follows that in cascade Connection, having based on junction type FETQ1 due to flowing Parasitic diode high current, it is possible to suppress based on excessive heating and cause switch element to puncture.That is, in closed type In junction type FET, in switch（During conducting）, positive voltage is applied to gate electrode Gj relative to source S.Now, the source of junction type FETQ1 Polar region domain is formed by n-type semiconductor region, and gate electrode Gj is formed by p-type semiconductor region, accordingly, with respect to source S to grid electricity Pole Gj applies positive voltage it is meant that applying forward voltage between source region and gate electrode Gj（Forward bias）.Therefore, normal In the junction type FET of closed form, if excessively increasing forward voltage, two pole of parasitism being made up of source region and gate electrode Gj can be caused Pipe is turned on.Its result is there is the flowing between gate electrode Gj and source region to have the situation of high current, with junction type FET mistakes Degree generates heat and causes the probability of corrupted.In contrast, in the switch element of cascade Connection, using the junction type of open type FETQ1, gate electrode Gj are electrically connected with the source S of switch element.It follows that between the gate electrode Gj and source S of junction type FETQ1 Voltage switch when（During conducting）Also will not forward bias.Therefore, in cascade Connection, have based on junction type due to flowing The high current of the parasitic diode of FETQ1, it is possible to suppressing to cause switch element to puncture based on excessive heating.
Like this, the switch element of cascade Connection has above-mentioned various advantages, but studies through the present inventor, as a result New discovery techniques illustrated below problem.That is, in order to realize cascade Connection, need to be formed with junction type by welding lead The semiconductor chip of FETQ1 and it is formed with the semiconductor chip of low pressure MOSFETQ2 and couples together.Thus, for example, low resistance to Source S j of drain D m and junction type FETQ1 of the MOSFETQ2 of pressure connects via welding lead.In this case, the present inventor is new It was found that, the stray inductance based on welding lead is attached with source S j of junction type FETQ1.When being attached with such stray inductance When, big surge voltage is produced during switch, thus, the voltage being applied with low pressure MOSFETQ2 more than pressure.Its result For with avalanche mode action, the flowing in low pressure MOSFETQ2 is had and cannot be controlled with gate electrode Gm low pressure MOSFETQ2 The high current of system and component breakdown may be caused.Hereinafter, describe its mechanism in detail.
Mechanism of production ＞ of ＜ technical tasks
Fig. 2's（a）It is the circuit for representing the inverter that the junction type FET and MOSFET of cascade Connection are used as switch element Figure.Fig. 2's（a）Shown inverter is with the upper branch road being connected in series with power supply VCC and lower branch road.Upper route is in drain D 1 The switch element being connected between source S 1 is constituted.In composition the switch element of branch road by cascade Connection junction type FETQ1a and MOSFETQ2a is constituted.Specifically, drain D j1 of junction type FETQ1a is connected with the drain D 1 of switch element, junction type FETQ1a's Source S j1 is connected with drain D m1 of MOSFETQ2a.And, source S m1 of MOSFETQ2a is connected with the source S 1 of switch element Connect.In addition, the gate electrode Gj1 of junction type FETQ1a is connected with the source S 1 of switch element, MOSFETQ2a gate electrode Gm1 with Gate driver circuit is connected between the source S 1 of switch element（G/D）.
Here, existing based on welding lead between drain D m1 of source S j1 and MOSFETQ2a of junction type FETQ1a Stray inductance Lse1, is present based on welding lead between the source S 1 of the gate electrode Gj1 and switch element of junction type FETQ1a Stray inductance Lgi1.Additionally, Fig. 2's（a）In, by the voltage between the drain D 1 of the source S 1 and switch element of switch element Voltage Vdsu is defined as, the voltage between the source S 1 and drain D m1 of MOSFETQ2a of switch element is defined as into voltage Vdsmu。
Similarly, such as Fig. 2（a）Shown, lower route the switch element connected between drain D 2 and source S 2 and constitutes. The switch element for constituting lower branch road is made up of the junction type FETQ1b and MOSFETQ2b of cascade Connection.Specifically, junction type FETQ1b Drain D j2 be connected with the drain D 2 of switch element, source S j2 of junction type FETQ1b is connected with drain D m2 of MOSFETQ2b. And, source S m2 of MOSFETQ2b is connected with the source S 2 of switch element.In addition, the gate electrode Gj2 of junction type FETQ1b with open The source S 2 for closing element connects, and between the source S 2 of the gate electrode Gm2 and switch element of MOSFETQ2b is connected with raster data model Circuit（G/D）.And, load inductance LL is connected between the drain D 2 of the source S 2 and switch element of switch element.
Here, existing based on welding lead between drain D m2 of source S j2 and MOSFETQ2b of junction type FETQ1b Stray inductance Lse2, is present based on welding lead between the source S 2 of the gate electrode Gj2 and switch element of junction type FETQ1b Stray inductance Lgi2.Additionally, Fig. 2's（a）In, by the voltage between the drain D 2 of the source S 2 and switch element of switch element Voltage Vak is defined as, the voltage between the source S 2 and drain D m2 of MOSFETQ2b of switch element is defined as into voltage Vdsmd。
The inverter of the switch element of cascade Connection is make use of to constitute as described above, below, explanation should The action of inverter, illustrates the mechanism of production of technical task.First, illustrate the switching elements ON of composition upper branch road Situation.That is, explanation is by constituting the switching elements ON of upper branch road, on the other hand disconnecting the switch element for constituting lower branch road And to load（Comprising load inductance）Apply the situation of supply voltage.
Fig. 2's（b）Show the waveform in the case of by the switching elements ON of branch road in composition.Specifically, when During by constituting the switching elements ON of upper branch road, the junction type FETQ1a and MOSFETQ2a conducting due to constituting upper branch road, so returning Stream electric current in drain D j1 from junction type FETQ1a, drain D m1 via MOSFETQ2a and source S m1, flow through load inductance LL And flow in returning to the path of power supply VCC.Now, such as Fig. 2（b）Shown, it is left that voltage Vdsmu is changed to 0V from assigned voltage The right side, on the other hand, voltage Vak from the switch element by upper branch road disconnect when 0V rise to the voltage of supply voltage or so.Its As a result it is that the drain voltage of the MOSFETQ2b of lower branch road is that voltage Vdsmd is risen to the junction type FETQ1b cut-offs of lower branch road Voltage, after the junction type FETQ1b cut-offs of lower branch road, maintains certain constant voltage.The change of voltage Vdsmd is to can ignore that to post The change of the perfect condition of raw inductance, such as Fig. 2（b）Dotted line shown in.However, working as stray inductance Lse2 or stray inductance Lgi2 During increase, such as Fig. 2（b）It is shown in solid, voltage Vdsmd is drastically significantly gone up in the switching elements ON by upper branch road Rise.
On the other hand, Fig. 2（c）Show the waveform in the case that the switch element for constituting upper branch road is disconnected.Specifically For, when the switch element for constituting upper branch road is disconnected, such as Fig. 2（c）Shown, voltage Vdsmd is changed to from assigned voltage 0V or so, on the other hand, voltage Vdsu from switching elements ON by upper branch road when 0V rise to the electricity of supply voltage or so Pressure.Its result is that the drain voltage of the MOSFETQ2a of upper branch road is that voltage Vdsmu is risen to the junction type FETQ1a of upper branch road The voltage of cut-off, after the junction type FETQ1a cut-offs of upper branch road, maintains certain constant voltage.The change of voltage Vdsmu is can Ignore the change of the perfect condition of stray inductance, such as Fig. 2（c）Dotted line shown in.However, working as stray inductance Lse1 or parasitic electricity When sense Lgi1 increases, such as Fig. 2（c）It is shown in solid, voltage Vdsmu by upper branch road switch element disconnect when, drastically show Write ground to rise.
Like this, it is known that in the case of by the switching elements ON of upper branch road, the lower branch road of disconnection can be produced The drain voltage of MOSFETQ2b is the phenomenon that voltage Vdsmd steeply rises, in the situation that the switch element by upper branch road disconnects Under, the drain voltage phenomenon that i.e. voltage Vdsmu steeply rises of the MOSFETQ2a of the upper branch road of disconnection can be produced.Due to these The mechanism of production of phenomenon is identical, so below, is conceived to the situation of the switching elements ON of upper branch road, illustrates lower for disconnecting The drain voltage of the MOSFETQ2b on road is the mechanism of production of the phenomenon that voltage Vdsmd steeply rises.As the generation machine of the phenomenon Reason, it is considered to three kinds of mechanism shown below.
1st mechanism is, the phenomenon is by being present in source S j2 of the junction type FETQ1b for constituting lower branch road and constitute lower branch road MOSFETQ2b drain D m2 between stray inductance Lse2 cause.Specifically, the switch element of upper branch road is being connect When logical, the MOSFETQ2b cut-offs of lower branch road.Now, voltage Vak starts to increase from 0V or so, with the increase of voltage Vak, The drain voltage of the MOSFETQ2b of lower branch road is that voltage Vdsmd also begins to increase.But, in the initial rank that voltage Vdsmd increases Section, voltage Vdsmd will not go out more than setting than the grid voltage for putting on the gate electrode Gj2 of junction type FETQ1b greatly, therefore, knot Type FETQ1b will not end, and electric current flows from drain D j2 of junction type FETQ1b to source S j2.Its result is that electric current is flowed into Accumulation in drain D m2 of MOSFETQ2b has electric charge.It follows that the drain voltage of MOSFETQ2b is voltage Vdsmd rising. Then, voltage Vdsmd continues to rise, when the grid voltage than junction type FETQ1b goes out more than setting greatly, junction type FETQ1b Cut-off, electric current further will not be flowed.That is, the starting stage increased in voltage Vdsmd, electric current is junction type FETQ1b's Flow between drain D j2 and source S j2, the accumulation in drain D m2 of MOSFETQ2b has electric charge, therefore voltage Vdsmd increases. Then, with the increase of voltage Vdsmd, voltage Vdsmd is gone out greatly more than setting with the grid voltage become than junction type FETQ1b Size state be close to, therefore, the electric current flowed in drain D j2 and source S j2 of junction type FETQ1b is gradually decreased.So Afterwards, finally, voltage Vdsmd goes out greatly more than setting than the grid voltage of junction type FETQ1b, so as to junction type FETQ1b is ended. After junction type FETQ1b cut-offs, do not have electric charge to flow into drain D m2 of MOSFETQ2b, voltage Vdsmd constants.
Like this, in the switching elements ON by upper branch road, the MOSFETQ2b cut-offs of lower branch road, but in the stage, under The junction type FETQ1b of branch road will not be immediately turned off, and electric current flows from drain D j2 of junction type FETQ1b to source S j2.And, flow into Flow into drain D m2 of MOSFETQ2b to the electric current in source S j2 of junction type FETQ1b via stray inductance Lse2.Now, The starting point is that the electric current flowed to source S j2 from drain D j2 of the junction type FETQ1b of lower branch road is reduced.It means that to posting The electric current of raw inductance Lse2 flowings was reduced also with the time.Its result is cancellation current to be produced in stray inductance Lse2 and is subtracted Few such electromotive force.That is, stray inductance Lse2 is so that the electric current flowed from drain D j2 of junction type FETQ1b to source S j2 increases Plus mode function.Therefore, when stray inductance Lse2 increases, transiently drain D j2 from junction type FETQ1b is to source Sj2 flowings in pole have high current.Its result is that the electric charge flowed into drain D m2 of MOSFETQ2b is sharply increased, thus, voltage Vdsmd is sharply increased.Which is the 1st mechanism.
Then, the 2nd mechanism is, the phenomenon is by being present in the gate electrode Gj2 of the junction type FETQ1b for constituting lower branch road with What stray inductance Lgi2 between the source S 2 of branch road caused.Specifically, in the switching elements ON by upper branch road, lower The MOSFETQ2b cut-offs on road.Now, voltage Vak starts to increase from 0V or so, but for example, such as Fig. 2（b）It is shown, by upper The starting stage of the switching elements ON on road, voltage Vak are vibrated in the range of more than supply voltage.It is based on by with inverter The counter electromotive force that the load inductance LL included by the load of connection causes.Therefore, voltage Vak is initial when upper branch road is connected Stage changes.Here, being conceived to junction type FETQ1b, it is formed between drain D j2 and gate electrode Gj2 of junction type FETQ1b Parasitic capacitance, when voltage Vak changes, the voltage for putting on the parasitic capacitance also changes.It is additionally, since the parasitism The electrostatic capacitance value of electric capacity is than larger value, so the discharge and recharge electricity produced with the variation in voltage for putting on parasitic capacitance Stream also increases.The charging and discharging currents flow between the source S 2 of the gate electrode Gj2 and lower branch road of junction type FETQ1b.Now, fill Discharge current is time dependent electric current.Thus, for example, when the gate electrode Gj2 in junction type FETQ1b and the source electrode of lower branch road When there is stray inductance Lgi2 between S2, as time dependent charging and discharging currents flow in stray inductance Lgi2, so The size and discharge and recharge electricity with stray inductance Lgi2 is produced between the source S 2 of the gate electrode Gj2 and lower branch road of junction type FETQ1b The proportional resistance components of the product of the time diffusion of stream.Its result is, the source electrode of the gate electrode Gj2 of junction type FETQ1b and lower branch road S2 will not become same current potential, and the source S 2 for producing the gate electrode Gj2 of junction type FETQ1b relative to lower branch road is on positive voltage direction The pattern for rising.In this case, as the gate electrode Gj2 of junction type FETQ1b becomes positive voltage, so inhibiting from junction type FETQ1b Gate electrode Gj2 growth depletion layer, channel region width increase.Therefore, drain D j2 from junction type FETQ1b is to source electrode The current transition ground increase of Sj2 flowings.Its result is that the electric charge flowed into drain D m2 of MOSFETQ2b is sharply increased, by This, voltage Vdsmd is sharply increased.Which is the 2nd mechanism.And, according to the 2nd mechanism, due to the gate electrode Gj2 in junction type FETQ1b In be applied with positive voltage, so in order to junction type FETQ1b is ended, it is necessary to which source S j2 of junction type FETQ1b is applied to compare grid electricity Pole Gj2 applies the big voltage of situation of 0V.From this viewpoint, the voltage Vdsmd for rising before junction type FETQ1b cut-offs Increase.
And, the 3rd mechanism is, the phenomenon is by being present in the gate electrode Gj2 of the junction type FETQ1b for constituting lower branch road with What the dead resistance between the source S 2 of branch road caused.As the explanation in the 2nd mechanism, in the gate electrode of junction type FETQ1b Flowing between the source S 2 of Gj2 and lower branch road has charging and discharging currents.It follows that when junction type FETQ1b gate electrode Gj2 with When there is dead resistance between the source S 2 of lower branch road, the flowing in the dead resistance has charging and discharging currents, produces voltage and declines. Its result is that the source S 2 of the gate electrode Gj2 of junction type FETQ1b and lower branch road will not become same current potential, produce junction type FETQ1b's Source S 2 patterns that to positive voltage direction rise of the gate electrode Gj2 relative to lower branch road.Thus, in the 3rd mechanism, with the 2nd machine Manage similarly, as the gate electrode Gj2 of junction type FETQ1b becomes positive voltage, so also inhibits the gate electrode from junction type FETQ1b The depletion layer of Gj2 growths, the width increase of channel region.Therefore, flow from drain D j2 of junction type FETQ1b to source S j2 The increase of current transition ground.Its result is that the electric charge flowed into drain D m2 of MOSFETQ2b is sharply increased, thus, voltage Vdsmd is sharply increased.
As described above, according to 1st mechanism related to stray inductance Lse2, stray inductance Lgi2 and dead resistance to 3 mechanism, it is known that voltage Vdsmd is sharply increased.Like this, when stray inductance Lse2, stray inductance Lgi2 and dead resistance increase When, the drain voltage of the MOSFETQ2b of lower branch road is the pressure voltage above that voltage Vdsmd rises to MOSFETQ2b, by This, there is snowslide action in the MOSFETQ2b of lower branch road, finally, the MOSFETQ2b of lower branch road may be breakdown.
Specifically, when the voltage more than pressure is applied with MOSFETQ2b, in the inside of MOSFETQ2b, is produced from local The region that raw electric field is concentrated, produces the hole-electron pair based on ionization by collision in this region in a large number.By a large amount of generations Hole-electron pair, by source region（N-type semiconductor region）, channel formation region（P-type semiconductor region）And drift region（n Type semiconductor regions）The parasitic npn bipolar transistors conducting of formation.In the unit of parasitic npn bipolar transistors conducting （MOSFETQ2b）In, flowing has with the uncontrollable high currents of gate electrode Gm2 of MOSFETQ2b and generates heat.Now, due to sending out Thermal conductivity causes temperature to rise, and the resistance of semiconductor regions reduces, therefore causes the positive feedback of more high current flowing.Its result is, office Portion's flowing has high current, causes MOSFETQ2b breakdown.The phenomenon is avalanche breakdown.As occurring during avalanche breakdown, meeting The reliability of semiconductor device is caused to reduce.
Therefore, in present embodiment 1, in order to suppress the reason for becoming avalanche breakdown insulation it is pressure more than voltage to The applying of MOSFET, implements research in terms of stray inductance and dead resistance is reduced.Hereinafter, illustrate to implement this reality of the research Apply the technological thought of mode 1.In present embodiment 1, the aspect for implementing research in the mounting structure to semiconductor device has Feature, illustrates the mounting structure of the semiconductor device comprising this feature point.
The mounting structure ＞ of the semiconductor device of ＜ present embodiments 1
Fig. 3 is the encapsulation for representing present embodiment 1（Semiconductor device）The mounting structure figure of PKG1.As shown in figure 3, this reality The encapsulation PKG1 for applying mode 1 has two chip carrying portions PLT1 and chip carrying portion PLT2 of electrically insulated from one another.In figure 3, The metallic plate for being configured in right side constitutes chip carrying portion PLT1, and the metallic plate for being configured in left side constitutes chip carrying portion PLT2.Core Piece equipped section PLT1 is integrally formed in the way of being linked with drain lead DL, and chip carrying portion PLT1 and drain lead DL are electrically connected Connect.And, by separate and across drain lead DL in the way of be configured with source lead SL and grid lead GL.Specifically, As shown in figure 3, source lead SL is configured with the right side of drain lead DL, be configured with grid lead on the left of drain lead DL GL.These drain leads DL, source lead SL and grid lead GL electrically insulated from one another.And, in the leading section of source lead SL, The source lead post portion SPST being made up of wide cut region is formed with, in the leading section of grid lead GL, is formed with by wide cut region The grid lead post portion GPST of composition.
Next, in chip carrying portion PLT1, for example, via the conductive adhesive material being made up of silver soldering agent or scolding tin And it is equipped with semiconductor chip CHP1.On semiconductor chip CHP1, for example, it is formed with the junction type FET with SiC as material. And, the back side of semiconductor chip CHP1 becomes drain electrode, on the surface of semiconductor chip CHP1（Interarea）On be formed with source electrode Pad SPj and gate pads GPj.That is, composition is formed with semiconductor chip CHP1 being connected in cascade Connection mode Switch element a part junction type FET, the drain electrode electrically connected with the drain electrode of junction type FET is formed in semiconductor chip The back side of CHP1, source pad SPj electrically connected with the source electrode of junction type FET and the grid electrically connected with the gate electrode of junction type FET Pad GPj is formed in the surface of semiconductor chip CHP1.
Then, in chip carrying portion PLT2, for example, via the conductive adhesive material being made up of silver soldering agent or scolding tin It is equipped with semiconductor chip CHP2.On semiconductor chip CHP2, for example, it is formed with the MOSFET with Si as material.Now, The back side of semiconductor chip CHP2 becomes drain electrode, on the surface of semiconductor chip CHP2（Interarea）On be formed with source pad SPm and gate pads GPm.That is, composition is formed with semiconductor chip CHP2 with opening that cascade Connection mode connects The MOSFET of a part for element is closed, the drain electrode electrically connected with the drain electrode of the MOSFET is formed in the back of the body of semiconductor chip CHP2 Face, source pad SPm electrically connected with the source electrode of MOSFET and gate pads GPm electrically connected with the gate electrode of MOSFET are formed On the surface of semiconductor chip CHP2.
And, the semiconductor chip CHP1 that is mounted in chip carrying portion PLT1 and it is mounted in chip carrying portion PLT2 Semiconductor chip CHP2 connected by welding lead, thereby, it is possible to constitute the switch element of cascade Connection.Specifically, As shown in figure 3, being formed in gate pads GPj on the surface of semiconductor chip CHP1 and being formed in the leading section of source lead SL Source lead post portion SPST electrically connected by wire Wgj.In addition, being formed in the source electrode weldering on the surface of semiconductor chip CHP1 Disk SPj and chip carrying portion PLT2 are electrically connected by wire Wds.And, it is formed in the source on the surface of semiconductor chip CHP2 The source lead post portion SPST of pole pad SPm and the leading section for being formed in source lead SL is electrically connected by wire Wsm.Separately Outward, the grid of gate pads GPm and the leading section for being formed in grid lead GL that are formed in the surface of semiconductor chip CHP2 draws Terminal portion GPST is electrically connected by wire Wgm.Here is configured to, and source lead post portion SPST's is connected with wire Wgj and leads The region of line Wsm and the region for being connected with wire Wgm of grid lead post portion GPST are positioned at the upper table than chip carrying portion PLT1 The high position of the upper surface of face and chip carrying portion PLT2.
Further, since semiconductor chip CHP1 is mounted in chip carrying portion PLT1 via conductive adhesive material, institute Electrically connected with chip carrying portion PLT1 with the drain electrode for being formed in the back side of semiconductor chip CHP1.Further, since semiconductor core Piece CHP2 is mounted in chip carrying portion PLT2 via conductive adhesive material, so being formed in the back of the body of semiconductor chip CHP2 The drain electrode in face is electrically connected with chip carrying portion PLT2.
In such encapsulation PKG1 for constituting, at least semiconductor chip CHP1, semiconductor chip CHP2, chip carrying portion A part of PLT1, a part for chip carrying portion PLT2, a part of drain lead DL, a part for source lead SL, grid A part and wire Wgj, Wds, Wgm, Wsm of pole lead GL is by sealing body sealing.Therefore, chip carrying portion PLT1 with A part for sealing body is configured between chip carrying portion PLT2, thus, chip carrying portion PLT1 and chip carrying portion PLT2 are logical Cross sealing body and be electrically insulated.In addition it is also possible to be configured under the lower surface and chip carrying portion PLT2 of chip carrying portion PLT1 Expose from sealing body on surface.In this case, the heat produced by semiconductor chip CHP1 and semiconductor chip CHP2 can be made from core The lower surface of the lower surface and chip carrying portion PLT2 of piece equipped section PLT1 is efficiently dissipated.
The sealing body is in for example rectangular shape, with the 1st side and 2nd side relative with the 1st side.The situation Under, for example, a part of drain lead DL, a part for source lead SL, a part of grid lead GL are from the 1st of sealing body Side projects.A part of these drain lead DL for projecting, a part for source lead SL, the part work of grid lead GL The function for external connection terminals.
Here, in the switch element of cascade Connection, due to carrying semiconductor chip CHP1 and semiconductor chip CHP2 the two semiconductor chips, so the existing general envelope of the only one of which chip carrying portion in encapsulation directly cannot be borrowed Dress.For example, it is also contemplated that use under the big rated current of several more than A, so that being formed on semiconductor chip CHP1 Junction type FET and the MOSFET that is formed on semiconductor chip CHP2 are using the institute at the back side of semiconductor chip with drain electrode Meaning longitudinal type construction.In this case, in the switch element of cascade Connection mode, it is impossible to will be formed in the back of the body of semiconductor chip CHP1 The drain electrode at the drain electrode in face and the back side for being formed in semiconductor chip CHP2 is electrically connected.It follows that there was only one in encapsulation In the existing generic encapsulation of individual chip carrying portion, when configuring semiconductor chip CHP1 and quasiconductor in a chip carrying portion During chip CHP2, can result in the back side of semiconductor chip CHP1 drain electrode and be formed in semiconductor chip CHP2's The drain electrode at the back side is electrically connected and cannot realize cascade Connection mode.
Therefore, in present embodiment 1, as shown in figure 3, by outer shape it is identical with generic encapsulation premised on, with envelope Solid interior arranges the mode of two chip carrying portions PLT1 and chip carrying portion PLT2 of electrically insulated from one another and constitutes encapsulation PKG1. Then, semiconductor chip CHP1 is mounted in chip carrying portion PLT1, and semiconductor chip CHP2 is mounted in into chip takes Mode on load portion PLT2 constitutes encapsulation PKG1.That is, by electric insulation two chip carrying portions PLT1 and chip carrying Portion PLT2 is arranged in encapsulation PKG1, by semiconductor chip CHP1 and semiconductor chip CHP2 planar configurations, and will by wire The semiconductor chip CHP1 and semiconductor chip CHP2 of planar configuration is coupled together, and thus achieves cascade Connection.
Therefore, the encapsulation PKG1 according to present embodiment 1, for example, can will be provided with what is utilized in power circuit etc. The existing generic encapsulation of switch element is substituted for the encapsulation PKG1 of overall dimensions identical present embodiment 1.Especially, according to this The encapsulation PKG1 of embodiment 1, due to configuration and the generic encapsulation phase of drain lead DL, source lead SL and grid lead GL Together, it is possible to by the encapsulation PKG1 of generic encapsulation alternative costs embodiment 1, it is not necessary to other drive circuits or print base Wiring of plate etc. is designed change.Therefore, according to present embodiment 1, easily change from the switch element using generic encapsulation It is the switch element of the high performance cascade Connection mode of encapsulation PKG1 using present embodiment 1, with can not carry out The advantage of high performance power-supply system is significantly provided in the case of design alteration.
Hereinafter, illustrate the characteristic point of the encapsulation PKG1 of present embodiment 1.First, the 1st characteristic point of present embodiment 1 exists In as shown in figure 3, so that the surface for being arranged on the semiconductor chip CHP1 for being formed with junction type FET is configured as close possible in the way of Gate pads GPj and source lead SL.Specifically, in present embodiment 1, the core of semiconductor chip CHP1 will be carried Piece equipped section PLT1 is configured in the same side of the configuration side of source lead SL relative to drain lead DL.Thereby, it is possible to make chip Equipped section PLT1 is close to source lead SL.This means can be by the semiconductor chip CHP1 being mounted in chip carrying portion PLT1 Configured in the way of being close to source lead SL.And, in present embodiment 1, it is not to be mounted in chip carrying portion PLT1 Semiconductor chip CHP1 be configured in the central part of chip carrying portion PLT1, but be close to chip carrying portion PLT1 and source electrode The mode configuring semiconductor chip CHP1 on lead SL nearest side.Thereby, it is possible to configure in the way of closest to source lead SL Semiconductor chip CHP1.And, in present embodiment 1, by semiconductor chip CHP1 with as close possible to source lead SL Mode is configured, and in the way of making gate pads GPj on the surface for being formed in semiconductor chip CHP1 be close to source lead SL Configuration.Like this, in present embodiment 1, first, the chip carried by the semiconductor chip CHP1 for being formed with junction type FET Equipped section PLT1 is configured in the position nearer with source lead SL, then, semiconductor chip CHP1 is mounted in chip carrying portion The region nearer with source lead SL in interior zone in PLT1.On this basis, in present embodiment 1, so that shape The mode that source lead SL is close to into gate pads GPj on the surface of semiconductor chip CHP1 configures gate pads GPj.By This, gate pads GPj and source lead SL for being formed in the surface of semiconductor chip CHP1 are close to.In other words, in this embodiment party In formula 1, be formed in semiconductor chip CHP1 surface gate pads GPj with other leads（Drain lead DL and grid draw Line GL）The mode compared closer to source lead SL is configured.Its result is, according to present embodiment 1, can shorten gate pads The distance between GPj and source lead SL, therefore, it is possible to shorten the wire Wgj's of connection gate pads GPj and source lead SL Length.Especially, in present embodiment 1, due to adopt in source lead SL be present in it is nearer with gate pads GPj The structure of connecting wire Wgj at the source lead post portion SPST of the wide cut of leading section, it is possible to further shortening wire Wgj's Length.The length of wire Wgj can be shortened it is meant that can reduce being present in the stray inductance of wire Wgj（The Lgi1 of Fig. 2 and Lgi2）.That is, according to present embodiment 1, fully can reduce being present in the stray inductance of wire Wgj.Thus may be used Know, can suppress based on above-mentioned 2nd mechanism, applying of the pressure voltage above to MOSFET of insulating, thereby, it is possible to effectively Suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to present embodiment 1, can seek semiconductor device Reliability is improved.
Then, illustrate the 2nd characteristic point of present embodiment 1.2nd characteristic point of present embodiment 1 is, as shown in figure 3, By configure as close possible in the way of the surface for being arranged on the semiconductor chip CHP2 for being formed with MOSFET gate pads GPm, With grid lead GL.Specifically, in present embodiment 1, the chip carrying portion PLT2 phase of semiconductor chip CHP2 will be carried For the same side for the configuration side that drain lead DL is configured in grid lead GL.Thereby, it is possible to be close to chip carrying portion PLT2 Grid lead GL.This means can be by the semiconductor chip CHP2 being mounted in chip carrying portion PLT2 to be close to grid lead The mode of GL is configured.And, in present embodiment 1, it is not to be mounted in the semiconductor chip in chip carrying portion PLT2 CHP2 is configured in the central part of chip carrying portion PLT2, but to be close to the nearest with grid lead GL of chip carrying portion PLT2 The mode configuring semiconductor chip CHP2 on side.Thereby, it is possible to the configuring semiconductor chip in the way of closest to grid lead GL CHP2.And, in present embodiment 1, semiconductor chip CHP2 is configured in the way of as close possible to grid lead GL, and And configured in the way of making gate pads GPm on the surface for being formed in semiconductor chip CHP2 be close to grid lead GL.Like this, In present embodiment 1, first, the chip carrying portion PLT2 configuration semiconductor chip CHP2 for being formed with MOSFET carried In the position nearer with grid lead GL, then, inner area semiconductor chip CHP2 being mounted in chip carrying portion PLT2 The region nearer with grid lead GL in domain.On this basis, in present embodiment 1, so as to be formed in semiconductor chip Gate pads GPm on the surface of CHP2 are close to the mode of grid lead GL and configure gate pads GPm.Thus, it is formed in quasiconductor Gate pads GPm and grid lead GL on the surface of chip CHP2 are close to.In other words, in present embodiment 1, it is formed in and partly leads Gate pads GPm on the surface of body chip CHP2 with other leads（Drain lead DL and source lead SL）Compare closer to grid The mode of pole lead GL is configured.Its result is, according to present embodiment 1, can shorten gate pads GPm and grid lead GL it Between distance, therefore, it is possible to shorten connection gate pads GPm and grid lead GL wire Wgm length.Especially, at this Grid in embodiment 1, due to adopting the wide cut for being present in the leading section nearer with gate pads GPm in grid lead GL The structure of connecting wire Wgm at pole stem portion GPST, it is possible to further shortening the length of wire Wgm.Thus, according to this Embodiment 1, can reduce the stray inductance of wire Wgm.Although the stray inductance that wire Wgm can be reduced is favorably improved The electrical characteristics of the switch element of cascade Connection, but it is no straight to the applying of MOSFET with the pressure voltage above of insulation is suppressed Connect relation.According to the structure of the 2nd characteristic point of present embodiment 1, can not be directly but suppress indirectly insulation pressure Applying of the voltage above to MOSFET.
Hereinafter, illustrate this aspect.As shown in figure 3, the 2nd characteristic point of present embodiment 1 is, with as close possible to grid The mode of lead GL configures the semiconductor chip CHP2 for being formed with MOSFET.It means that as shown in figure 3, deflection chip carrying The nearby side of portion PLT2 and configuring semiconductor chip CHP2, in other words, can be formed in the inner side of chip carrying portion PLT2 does not have Carry the large space of semiconductor chip CHP2.Like this, in present embodiment 1, it is able to ensure that in chip carrying portion PLT2 The aspect for not carrying the large space of semiconductor chip CHP2 has indirect feature.Specifically, according to this feature, such as Fig. 3 institutes Show, can fully guarantee the source electrode weldering on the surface of the semiconductor chip CHP1 that will be formed in being mounted in chip carrying portion PLT1 Disk SPj and the lead connecting region of chip carrying portion PLT2 electrical connection.Its result is, as shown in figure 3, can be led by a plurality of Line Wds connects source pad SPj and chip carrying portion PLT2.Here, chip carrying portion PLT2 be formed in partly leading of being carried The drain electrode electrical connection at the back side of body chip CHP2, therefore according to present embodiment 1, can be connected by a plurality of wire Wds The drain electrode of MOSFET and the source electrode of junction type FET.This means to reduce to connect the source electrode of the drain electrode of MOSFET and junction type FET The stray inductance of wire Wds（Lse1, Lse2 of Fig. 2）.That is, according to present embodiment 1, by using a plurality of wire Wds, can fully reduce the stray inductance between the drain electrode of MOSFET and the source electrode of junction type FET.
And, as shown in figure 3, expecting to configure in the way of as close possible to chip carrying portion PLT2 to be formed in semiconductor core The forming position of source pad SPj on the surface of piece CHP1.Its reason is, by being configured so that source pad SPj, Neng Goujin The length of the wire Wds of connection source pad SPj and chip carrying portion PLT2 may be shortened.Thus, it is also possible to reduce connection The stray inductance of the wire Wds of the drain electrode of MOSFET and the source electrode of junction type FET（Lse1, Lse2 of Fig. 2）.
By more than, according to the 2nd characteristic point of present embodiment 1, can suppress based on above-mentioned 1st mechanism, exhausted Applying of the voltage more than edge is pressure to MOSFET, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection. Its result is, according to present embodiment 1, the reliability of semiconductor device can be sought to improve.
Additionally, in present embodiment 1, as shown in figure 3, gate pads GPj are electric with source lead SL by wire Wgj Connect, also, gate pads GPm are electrically connected with grid lead GL by wire Wgm.Now, expect the thickness of wire Wgj （Width）It is configured the thickness than wire Wgm（Width）Slightly.Its reason is, if being present in the dead resistance increase of wire Wgj, Then according to the 3rd mechanism, cause to MOSFET apply insulation it is pressure more than voltage.Therefore, it is present in posting for wire Wgj from reduction From the viewpoint of raw resistance, the thickness of the wire Wgj structure thicker than other wires is desirably employed.Thus, as knot can be reduced The gate electrode of type FET and the source electrode of switch element（The source electrode of MOSFET can be also referred to as）Between dead resistance, it is possible to Suppress based on above-mentioned 3rd mechanism, applying of the pressure voltage above to MOSFET of insulating, thereby, it is possible to effectively killer stage The avalanche breakdown of the MOSFET of connection connection.Its result is, according to present embodiment 1, can to seek the reliability of semiconductor device Improve.
Next, the 3rd characteristic point of explanation present embodiment 1.3rd characteristic point of present embodiment 1 is, such as Fig. 3 institutes Show, by a plurality of wire Wsm by be arranged on the surface of the semiconductor chip CHP2 for being formed with MOSFET source pad SPm and Source lead SL（Source lead post portion SPST）Couple together.Thereby, it is possible to reduce the source electrode of MOSFET and source lead SL it Between dead resistance and stray inductance.Its result is the current potential of the source electrode that can suppress MOSFET from being supplied by source lead SL GND current potentials（Reference potential）Change, the source electrode of MOSFET can be firmly secured to GND current potentials.It is additionally, since drop Dead resistance between the source electrode and source lead SL of low MOSFET, so can also reduce the switch unit of cascade Connection The conducting resistance of part.Like this, the 3rd characteristic point according to present embodiment 1, can seek the cascade being formed in encapsulation PKG1 The raising of the electrical characteristics of the switch element being formed by connecting.
As described above, the encapsulation PKG1 according to present embodiment 1（Semiconductor device）, due to above-mentioned 1st feature Point and the 2nd characteristic point, can suppress applying of the pressure voltage above to MOSFET of insulating, thereby, it is possible to effectively killer stage The avalanche breakdown of the MOSFET of connection connection.Its result is that the reliability that can seek semiconductor device is improved.It is additionally, since this The encapsulation PKG1 of embodiment 1（Semiconductor device）With above-mentioned 3rd characteristic point, so can also seek dead resistance and parasitism The reduction of inductance, therefore, it is possible to seek the raising of the electrical characteristics of semiconductor device.
In addition, as the incidental concrete effects of encapsulation PKG1 of present embodiment 1, due to the encapsulation of present embodiment 1 PKG1 is employed the semiconductor chip CHP1 for being formed with junction type FET and the semiconductor chip CHP2 planes for being formed with MOSFET The structure of configuration, it is possible to freely designing the chip area of semiconductor chip CHP1 and semiconductor chip CHP2.It follows that The design of low on-resistance and the design of conducting current density also become easy, can realize the switch element of all size.
Then, illustrate one of other mounting means of the switch element of present embodiment 1.Fig. 4 is to represent this embodiment party The mounting structure figure of the encapsulation PKG2 of formula 1.Differences of the encapsulation PKG2 shown in Fig. 4 from the encapsulation PKG1 shown in Fig. 3 be, source Pole lead SL is different with the forming position of drain lead DL.Specifically, in the encapsulation PKG1 shown in Fig. 3, grid lead GL The leftmost side is configured in, drain lead DL is configured in center, and source lead SL is configured in the rightmost side.In contrast, shown in Fig. 4 In encapsulation PKG2, grid lead GL is configured in the leftmost side, and source lead SL is configured in center, and drain lead DL is configured in most right Side.In this case, as shown in figure 4, the change of allocation position with source lead SL, is formed in the table of semiconductor chip CHP1 The forming position of gate pads GPj in face is also to change in the way of closer source lead SL compared with other leads.Its result To encapsulate in PKG2 shown in Fig. 4, it is also possible to shorten the distance between gate pads GPj and source lead SL.Therefore, it is possible to Shorten the length of the wire Wgj of connection gate pads GPj and source lead SL.That is, in the encapsulation PKG2 shown in Fig. 4 In, it is also possible to fully reduce being present in the stray inductance of wire Wgj.It follows that can suppress based on above-mentioned 2nd mechanism , insulate it is pressure more than applying from voltage to MOSFET, thereby, it is possible to effectively suppress the snowslide of the MOSFET of cascade Connection Puncture.Its result is, in the encapsulation PKG2 shown in Fig. 4, it is also possible to seek the reliability of semiconductor device to improve.
And, as characteristic point specific to the encapsulation PKG2 shown in Fig. 4, compared with the encapsulation PKG1 shown in Fig. 3, can Fully shorten the wire of the source pad SPm and source lead SL electrical connection on the surface that will be formed in semiconductor chip CHP2 The length of Wsm.Therefore, PKG2, the dead resistance and stray inductance as wire Wsm can be reduced, institute are encapsulated according to Fig. 4 So that the electrical characteristics of the switch element of present embodiment 1 can be improved.Especially, obtain with regard to the contraction in length based on wire Wsm The effect for arriving, substantially changes at the aspect of the conducting resistance of the switch element for reducing present embodiment 1.
1 ＞ of ＜ variations
Next, illustrating the mounting structure of the encapsulation PKG3 of this variation 1.In this variation 1, explanation will be formed with knot The semiconductor chip of type FET and be formed with MOSFET semiconductor chip stacking structure.
Fig. 5 is the mounting structure figure of the encapsulation PKG3 for representing this variation 1.In Figure 5, the encapsulation PKG3 of this variation 1 With chip carrying portion PLT being for example made up of the metallic plate of rectangular shaped.Chip carrying portion PLT with drain lead DL The mode of link is integrally formed, and chip carrying portion PLT and drain lead DL are electrically connected.And, with separation and across the drain electrode The mode of lead DL is configured with source lead SL and grid lead GL.Specifically, as shown in figure 5, on the right side of drain lead DL Side is configured with source lead SL, on the left of drain lead DL is configured with grid lead GL.These drain leads DL, source lead SL and grid lead GL electrically insulated from one another.And, the source electrode being made up of wide cut region is formed with the leading section of source lead SL Stem portion SPST, is formed with the grid lead post portion GPST being made up of wide cut region in the leading section of grid lead GL.
Next, in chip carrying portion PLT, for example, via the conductive adhesive material being made up of silver soldering agent or scolding tin And it is equipped with semiconductor chip CHP1.On semiconductor chip CHP1, for example, it is formed with the junction type FET with SiC as material. And, the back side of semiconductor chip CHP1 becomes drain electrode, on the surface of semiconductor chip CHP1（Interarea）On be formed with source electrode Pad SPj and gate pads GPj.That is, on semiconductor chip CHP1, being formed with composition and being connected in cascade Connection mode Switch element a part junction type FET, the drain electrode electrically connected with the drain electrode of junction type FET is formed in semiconductor chip The back side of CHP1, source pad SPj electrically connected with the source electrode of junction type FET and the grid electrically connected with the gate electrode of junction type FET Pole pad GPj is formed in the surface of semiconductor chip CHP1.
Next, on semiconductor chip CHP1, for example, via the conductive adhesive material being made up of silver soldering agent or scolding tin Expect and be equipped with semiconductor chip CHP2.On semiconductor chip CHP2, for example, it is formed with the MOSFET with Si as material. Now, the back side of semiconductor chip CHP2 becomes drain electrode, on the surface of semiconductor chip CHP1（Interarea）On be formed with source electrode Pad SPm and gate pads GPm.That is, on semiconductor chip CHP2, being formed with composition and being connected in cascade Connection mode Switch element a part MOSFET, the drain electrode electrically connected with the drain electrode of the MOSFET is formed in semiconductor chip CHP2 The back side, source pad SPm electrically connected with the source electrode of MOSFET and the gate pads electrically connected with the gate electrode of MOSFET GPm is formed in the surface of semiconductor chip CHP2.
Like this, in this variation 1, semiconductor chip CHP2 is equipped with semiconductor chip CHP1, especially, Semiconductor chip CHP2 is equipped with source pad SPj on the surface for being formed at semiconductor chip CHP1.Thus, it is formed in and partly leads Source pad SPj on the drain electrode at the back side of body chip CHP2 and the surface for being formed in semiconductor chip CHP1 is electrically connected.Its knot Fruit is the source electrode and the MOSFET being formed on semiconductor chip CHP2 of the junction type FET being formed on semiconductor chip CHP1 Drain electrode electrical connection.It follows that semiconductor chip CHP2 needs to be formed on semiconductor chip CHP1's under top view Source pad SPj on surface is enclosed in interior mode and is formed.That is, in this variation 1, needing to make semiconductor chip The size for being smaller in size than semiconductor chip CHP1 of CHP2, furthermore, needs to make being smaller in size than for semiconductor chip CHP2 The size of source pad SPj.
Then, as shown in figure 5, being formed in gate pads GPj on the surface of semiconductor chip CHP1 and being formed in source electrode and draw The source lead post portion SPST of the leading section of line SL is electrically connected by wire Wgj.And, it is formed in semiconductor chip CHP2's The source lead post portion SPST of source pad SPm on surface and the leading section for being formed in source lead SL is electric by wire Wsm Connection.In addition, being formed in gate pads GPm on the surface of semiconductor chip CHP2 and being formed in the leading section of grid lead GL Grid lead post portion GPST electrically connected by wire Wgm.Here is configured to, and source lead post portion SPST's is connected with wire The region of Wgj and wire Wsm and the region for being connected with wire Wgm of grid lead post portion GPST are positioned at than chip carrying portion The high position of the upper surface of the upper surface and chip carrying portion PLT2 of PLT1.
In such encapsulation PKG3 for constituting, at least semiconductor chip CHP1, semiconductor chip CHP2, chip carrying portion A part of PLT, a part of drain lead DL, a part for source lead SL, a part of grid lead GL and wire Wgj, Wgm, Wsm are by sealing body sealing.In addition it is also possible to the lower surface for being configured to chip carrying portion PLT exposes from sealing body.Should In the case of, the heat produced by semiconductor chip CHP1 and semiconductor chip CHP2 can be efficiently made from chip carrying portion PLT Lower surface is dissipated.
The sealing body is in for example rectangular shape, with the 1st side and 2nd side relative with the 1st side.The situation Under, for example, a part of drain lead DL, a part for source lead SL, a part of grid lead GL are from the 1st of sealing body Side projects.A part of these drain lead DL for projecting, a part for source lead SL, the part work of grid lead GL The function for external connection terminals.
The encapsulation PKG3 of this variation 1 is constituted as described above, below, illustrates the feature of the encapsulation PKG3 of this variation 1 Point.First, as shown in figure 5, the characteristic point of this variation 1 is, knot is formed with to configure to be arranged on as close possible in the way of Gate pads GPj and source lead SL on the surface of the semiconductor chip CHP1 of type FET.Specifically, in this variation 1, Semiconductor chip CHP1 is configured in the same side of the configuration side of source lead SL relative to drain lead DL.That is, half Conductor chip CHP1 is relative to the centrage a-a ' deflections right side configuration shown in Fig. 5.Thereby, it is possible to connect semiconductor chip CHP1 Nearly source lead SL.And, in this variation 1, it is not semiconductor chip CHP1 to be configured in the central authorities of chip carrying portion PLT Portion, but the configuring semiconductor chip CHP1 in the way of the side nearest with source lead SL for being close to chip carrying portion PLT.Also It is to say, semiconductor chip CHP1 is partial to nearby side relative to the centrage b-b ' shown in Fig. 5（Downside）Configuration.Thereby, it is possible to Closest to the mode configuring semiconductor chip CHP1 of source lead SL.In other words, in this variation 1, it is formed in semiconductor core Gate pads GPj on the surface of piece CHP1 with other leads（Drain lead DL and grid lead GL）Compare closer to source electrode and draw The mode of line SL is configured.Its result is, according to this variation 1, due to shortening between gate pads GPj and source lead SL Distance, it is possible to shorten connection gate pads GPj and source lead SL wire Wgj length.Especially, in this deformation Source lead in example 1, due to adopting the wide cut for being present in the leading section nearer with gate pads GPj in source lead SL The structure of connecting wire Wgj at post portion SPST, it is possible to further shortening the length of wire Wgj.Can shorten wire Wgj's Length is it is meant that can reduce being present in the stray inductance of wire Wgj（The Lgi1 and Lgi2 of Fig. 2）.That is, according to this variation 1, Fully can reduce being present in the stray inductance of wire Wgj.It follows that can suppress based on above-mentioned 2nd mechanism, insulation Applying of the voltage more than pressure to MOSFET, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its As a result it is, according to this variation 1, the reliability of semiconductor device can be sought to improve.
Here, from from the viewpoint of the length of wire Wgj for shortening connection gate pads GPj and source lead SL, it is considered to Gate pads GPj are partial to into the avris nearest with source lead SL of semiconductor chip CHP1 and are configured.However, in this variation In 1, as shown in figure 5, configuring grid in the way of symmetrical along the right side of semiconductor chip CHP1 and relative to the right central part Pole pad GPj.The reasons why which is based on shown below.That is, gate pads GPj by grid wiring be formed in semiconductor chip Each gate electrode connection of multiple junction type FET of the inside of CHP1.It follows that for example, by with relative to the right central part pair The mode of title configures gate pads GPj, the grid of each gate electrode and gate pads GPj that can suppress to connect multiple junction type FET The range deviation of wiring.It means that, can as one man using the spy of the multiple junction type FET being formed in semiconductor chip CHP1 Property.For this reason, in this variation 1, in the way of the right central part relative to semiconductor chip CHP1 is symmetrical Configuration gate pads GPj.
Additionally, in this variation 1, as shown in figure 5, gate pads GPj are electrically connected with source lead SL by wire Wgj Connect, also, gate pads GPm are electrically connected with grid lead GL by wire Wgm.Now, expect the thickness of wire Wgj（It is wide Degree）It is configured the thickness than wire Wgm（Width）Slightly.Its reason is, if being present in the dead resistance increase of wire Wgj, According to the 3rd mechanism, can cause to MOSFET apply insulation it is pressure more than voltage.Therefore, it is present in posting for wire Wgj from reduction From the viewpoint of raw resistance, expect to take the structure for making the thickness of wire Wgj thicker than other wires.Thus, due to reducing The gate electrode of junction type FET and the source electrode of switch element（The source electrode of MOSFET can be also referred to as）Between dead resistance, so energy It is enough to suppress based on above-mentioned 3rd mechanism, applying of the pressure voltage above to MOSFET of insulating, thereby, it is possible to effectively suppress The avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to this variation 1, can to seek the reliability of semiconductor device Improve.
Next, illustrating the further feature point of this variation 1.As shown in figure 5, the further spy of this variation 1 Levy and be a little, the source pad on the surface of the semiconductor chip CHP2 for being formed with MOSFET will be arranged on by a plurality of wire Wsm SPm and source lead SL（Source lead post portion SPST）Couple together.Draw with source electrode thereby, it is possible to reduce the source electrode of MOSFET Dead resistance and stray inductance between line SL.Its result is the current potential of the source electrode that can suppress MOSFET from by source lead The GND current potentials of SL supplies（Reference potential）Change, the source electrode of MOSFET can be firmly secured to GND current potentials.And, Due to reducing the dead resistance between the source electrode of MOSFET and source lead SL, so can also reduce cascade Connection The conducting resistance of switch element.Like this, the further feature point according to this variation 1, can seek to be formed in encapsulation The raising of the electrical characteristics of the switch element of the cascade Connection in PKG3.
Then, illustrate characteristic point specific to this variation 1.As shown in figure 5, characteristic point specific to this variation 1 exists In being formed with the semiconductor chip CHP1 of junction type FET, be equipped with being formed with the semiconductor chip CHP2 of MOSFET.Thus, Source pad SPj that the surface of semiconductor chip CHP1 can be will be formed in and the back side that is formed in semiconductor chip CHP2 Drain electrode is directly connected to.That is, according to this variation 1, wire can not be used by the source electrode and MOSFET of junction type FET Drain electrode be directly connected to.It means that, almost entirely can remove folder be stored in the source electrode of junction type FET and MOSFET drain electrode it Between stray inductance.That is, characteristic point specific to this variation 1 is directly to be equipped with semiconductor chip CHP1 and partly lead Body chip CHP2, according to the structure, it is not necessary to for connecting the wire of the drain electrode of the source electrode and MOSFET of junction type FET.Using In the case of wire, the stray inductance for being present in wire becomes problem, but according to this variation 1, as wire can not be used Ground the drain electrode of the source electrode and MOSFET of junction type FET is directly connected to, it is possible to almost entirely remove MOSFET drain electrode with Stray inductance between the source electrode of junction type FET（Lse1, Lse2 of Fig. 2）.As known from the above, according to specific to this variation 1 Characteristic point, can suppress based on above-mentioned 1st mechanism, applying of the pressure voltage above to MOSFET of insulating, thereby, it is possible to have Effect ground suppresses the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to this variation 1, can seek semiconductor device Reliability improve.
According to the encapsulation PKG3 of this variation 1, the stacking ground configuring semiconductor chip CHP1 and half in chip carrying portion PLT Conductor chip CHP2.It follows that in the encapsulation PKG3 of this variation 1, can be that there is in encapsulation a chip carrying The construction of portion PLT, therefore, it is possible to directly borrow the existing generic encapsulation only in encapsulation with a chip carrying portion.That is, root According to the encapsulation PKG3 of this variation 1, so-called cheap generic encapsulation can be directly borrowed, be connected therefore, it is possible to inexpensively provide cascade The high performance switch element for connecing.In other words, according to this variation 1, can seek to be formed with the height of cascade Connection The cost cutting of the encapsulation PKG3 of the switch element of performance.
In addition, according to this variation 1, due to being formed with the semiconductor chip CHP1 of junction type FET and being formed with MOSFET Semiconductor chip CHP2 stackings, so the advantage of the erection space for also obtaining reducing semiconductor chip.Especially, the feelings Under condition, as shown in figure 5, as large space can be guaranteed in chip carrying portion PLT, so also can efficiently by semiconductor core Heat bulk storage produced by piece CHP1 and semiconductor chip CHP2.And, according to this variation 1, as switch element can be reduced Erection space, so also obtain can be by the past fly-wheel diode of the configuration on the printed board of package outside（Backflow two Pole pipe）The advantage in same encapsulation is arranged on switch element.Its result is, according to this variation 1, it is also possible to contribute to printing The erection space of substrate is cut down, thereby, it is possible to the cost cutting for seeking the system with power-supply system as representative overall.
Then, illustrate one of other mounting means of the switch element of this variation 1.Fig. 6 represents this variation 1 The mounting structure figure of encapsulation PKG4.Differences of the encapsulation PKG4 shown in Fig. 6 from the encapsulation PKG3 shown in Fig. 5 is to be formed in The allocation position of gate pads GPj on the surface of semiconductor chip CHP1 is different.Specifically, in the encapsulation PKG3 shown in Fig. 5 In, gate pads GPj are configured in the way of symmetrical along the right side of semiconductor chip CHP1 and relative to the right central part. In contrast, in the encapsulation PKG4 shown in Fig. 6, gate pads GPj deflection semiconductor chip CHP1 with source lead SL most Near avris and configure.In this case, the distance from gate pads GPj to source lead SL can be made most short.Therefore, according to figure Encapsulation PKG4 shown in 6, can make the length of the wire Wgj of connection gate pads GPj and source lead SL most short, thus, energy Enough minimize the stray inductance for being present in wire Wgj.It follows that can suppress based on above-mentioned 2nd mechanism, insulate it is pressure Applying of the voltage above to MOSFET, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result For in the encapsulation PKG4 shown in Fig. 6, it is also possible to seek the reliability of semiconductor device to improve.
Illustrate one of other mounting means of the switch element of this variation 1.Fig. 7 is the encapsulation for representing this variation 1 The mounting structure figure of PKG5.In the encapsulation PKG5 shown in Fig. 7, in the connection of gate pads GPj and source lead SL, and In the connection of source pad SPm and source lead SL, for example, using by copper coin（Metallic plate）The clip CLP of composition.Like this, By using copper coin, conductor resistance reduces compared with wire, therefore, it is possible to seek the reduction of stray inductance.That is, passing through The clip CLP constructed using metallic plate, the stray inductance that can reduce being present between gate pads GPj and source lead SL, And the stray inductance being present between source pad SPm and source lead SL.
Especially, the encapsulation PKG5 according to Fig. 7, due to reducing being present in gate pads GPj and source lead Stray inductance between SL, it is possible to suppressing based on above-mentioned 2nd mechanism, pressure voltage applying to MOSFET above of insulating Plus, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, the encapsulation according to Fig. 7 PKG5, can seek the reliability of semiconductor device to improve.And, the encapsulation PKG5 according to Fig. 7, due to can also reduce The stray inductance being present between source pad SPm and source lead SL, so can also seek the electrical characteristics of semiconductor device Raising.
Additionally, Fig. 8 is the figure in a section of the encapsulation PKG5 for representing this variation 1.As shown in figure 8, in chip carrying On portion PLT, semiconductor chip CHP1 is equipped with via conductive adhesive material PST, on semiconductor chip CHP1, via Conductive adhesive material（It is not shown）And it is equipped with semiconductor chip CHP2.And, semiconductor chip CHP1（Gate pads）With Source lead SL and semiconductor chip CHP2（Source pad）Electrically connected by clip CLP with source lead SL.Additionally, Dotted line part represents the part covered by sealing body.
Then, illustrate one of other mounting means of the switch element of this variation 1.Fig. 9 represents this variation 1 The mounting structure figure of encapsulation PKG6.Differences of the encapsulation PKG6 shown in Fig. 9 from the encapsulation PKG3 shown in Fig. 5 is that source electrode draws Line SL is different with the forming position of drain lead DL.Specifically, in the encapsulation PKG3 shown in Fig. 5, grid lead GL configurations In the leftmost side, drain lead DL is configured in center, and source lead SL is configured in the rightmost side.In contrast, in the encapsulation shown in Fig. 9 In PKG6, grid lead GL is configured in the leftmost side, and source lead SL is configured in center, and drain lead DL is configured in the rightmost side.Should In the case of, as shown in figure 9, the change of the allocation position with source lead SL, the quasiconductor being mounted in chip carrying portion PLT The loading position change of chip CHP1.That is, the allocation position of semiconductor chip CHP1 is more connecing compared with other leads The mode of nearly source lead SL is changed.Specifically, semiconductor chip CHP1 is with symmetrical relative to the centrage a-a ' shown in Fig. 9 Mode configure, also, to be partial to nearby side relative to centrage b-b '（Downside）Mode configure.Its result is, in Fig. 9 institutes In the encapsulation PKG6 for showing, it is also possible to shorten the distance between gate pads GPj and source lead SL.Therefore, it is possible to shorten connection The length of the wire Wgj of gate pads GPj and source lead SL.That is, in the encapsulation PKG6 shown in Fig. 9, it is also possible to Fully reduce being present in the stray inductance of wire Wgj.It follows that can suppress based on above-mentioned 2nd mechanism, insulate it is pressure Applying of the voltage above to MOSFET, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result For in the encapsulation PKG6 shown in Fig. 9, it is also possible to seek the reliability of semiconductor device to improve.
And, as characteristic point specific to the encapsulation PKG6 shown in Fig. 9, compared with the encapsulation PKG3 shown in Fig. 5, can Fully shorten the wire of the gate pads GPm and grid lead GL electrical connection on the surface that will be formed in semiconductor chip CHP2 The length of Wgm.Therefore, the encapsulation PKG6 according to Fig. 9, the dead resistance and stray inductance as wire Wgm can be reduced, It is possible to improving the electrical characteristics of the switch element of this variation 1.
Additionally, Figure 10 is the figure in a section of the encapsulation PKG6 for representing this variation 1.As shown in Figure 10, take in chip On load portion PLT, semiconductor chip CHP1 is equipped with via conductive adhesive material PST, on semiconductor chip CHP1, Jing By conductive adhesive material（It is not shown）And it is equipped with semiconductor chip CHP2.And, semiconductor chip CHP2（Source pad） Electrically connected by wire Wsm with source lead SL.Additionally, dotted line part represents the part covered by sealing body.
Next, illustrating of other mounting means of the switch element of this variation 1.Figure 11 is to represent this variation The mounting structure figure of 1 encapsulation PKG7.Differences of the encapsulation PKG7 shown in Figure 11 from the encapsulation PKG6 shown in Fig. 9 be, shape Allocation position into gate pads GPj on the surface of semiconductor chip CHP1 is different.Specifically, in the encapsulation shown in Fig. 9 In PKG6, gate pads are configured in the way of symmetrical along the right side of semiconductor chip CHP1 and relative to the right central part GPj.In contrast, in the encapsulation PKG7 shown in Figure 11, gate pads GPj deflection semiconductor chip be CHP1's and source lead SL nearest avris and configure.In this case, the distance from gate pads GPj to source lead SL can be made most short.Therefore, root According to the encapsulation PKG7 shown in Figure 11, the length of the wire Wgj of connection gate pads GPj and source lead SL can be made most short, by This, minimizes can the stray inductance that be present in wire Wgj.It follows that can suppress based on above-mentioned 2nd mechanism, exhausted Applying of the voltage more than edge is pressure to MOSFET, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection. Its result is, in the encapsulation PKG7 shown in Figure 11, it is also possible to seek the reliability of semiconductor device to improve.
Then, for being present in the stray inductance of the switch element of the switch element and this variation of present embodiment 1, with The stray inductance for being present in the switch element of prior art is contrasted and is illustrated.Figure 12 is the switch for representing cascade Connection The figure of the circuit diagram and stray inductance of element.Specifically, Figure 12（a）It is the switch element and parasitism electricity for representing prior art The circuit diagram of the existence position of sense, Figure 12's（b）It is the existence position of the switch element and stray inductance that represent present embodiment 1 Circuit diagram.In addition, Figure 12（c）It is the circuit diagram of the existence position of the switch element and stray inductance that represent this variation 1.
First, as from Figure 12（a）Learn like that, in the switch element of the cascade Connection of prior art, even There is stray inductance Lse in the intermediate node Se of the drain electrode of the source electrode and MOSFETQ2 of binding type FETQ1, in the source electrode of MOSFETQ2 There is stray inductance Ls and the source S of switch element between.In addition, junction type FET gate electrode and switch element source S it Between there is stray inductance Lgi, there is stray inductance in the gate electrode Gm of MOSFET.
In contrast, such as Figure 12（b）It is shown, in the switch element of the cascade Connection of present embodiment 1, with figure 12（a）The switch element of the cascade Connection of shown prior art is compared, and reduces stray inductance Lse, stray inductance Ls and stray inductance Lgi.Which is based on following aspect and realizes：For example, as shown in figure 3, in present embodiment 1, by core The allocation position of the allocation position, the allocation position of semiconductor chip CHP1 and gate pads GPj of piece equipped section PLT1 is implemented to grind Study carefully, using the structure of the wire Wgj for shortening connection gate pads GPj and source lead SL；With make connection source pad SPj and core The wire Wds of piece equipped section PLT2 is made up of a plurality of.Thus, according to present embodiment 1, the pressure electricity above that insulate can be suppressed The applying of MOSFET is pressed to, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to Present embodiment 1, can seek the reliability of semiconductor device to improve.
In addition, such as Figure 12（c）It is shown, in the switch element of the cascade Connection of this variation 1, with this embodiment party Formula 1 similarly, with Figure 12's（a）The switch element of the cascade Connection of shown prior art is compared, and can reduce parasitism Inductance Ls and stray inductance Lgi.And, in this variation 1, can almost entirely remove and be present in connection junction type FETQ1 Source electrode and MOSFETQ2 drain electrode intermediate node Se stray inductance Lse.Its reason is, for example, as shown in figure 5, It is formed with the semiconductor chip CHP1 of junction type FET, is equipped with being formed with the semiconductor chip CHP2 of MOSFET.Thereby, it is possible to Source pad SPj that will be formed in the surface of semiconductor chip CHP1 and the electric leakage at the back side for being formed in semiconductor chip CHP2 Pole is directly connected to.That is, according to this variation 1, wire can not be used by the leakage of the source electrode and MOSFET of junction type FET Pole is directly connected to.Therefore, according to this variation 1, can almost entirely remove folder and the source electrode of junction type FET is stored in MOSFET's Stray inductance between drain electrode.Thus, according to this variation 1, pressure voltage applying to MOSFET above of insulating can be suppressed Plus, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to this variation 1, can The reliability of semiconductor device is sought to improve.
2 ＞ of ＜ variations
Next, illustrating the mounting structure of the encapsulation PKG8 of this variation 2.Figure 13 is the encapsulation for representing this variation 2 The mounting structure figure of PKG8.The structure of the encapsulation PKG8 shown in Figure 13 is roughly the same with the structure of the encapsulation PKG1 shown in Fig. 3.No It is the outer shape of encapsulation with point.Like this, technological thought of the invention can be applied not only to the encapsulation shown in Fig. 3 PKG1, it is also possible to suitable for encapsulation PKG8 as shown in Figure 13.That is, in the encapsulation that switch element is installed composition In, there are various generic encapsulations, the technological thought of the present invention for example can be to shown in the encapsulation PKG1 and Figure 13 shown in Fig. 3 Encapsulation PKG8 is that the various generic encapsulations of representative are improved and realize.Specifically, in the encapsulation shown in Figure 13 In PKG8, for example, it is also possible to shorten the distance between gate pads GPj and source lead SL, therefore, it is possible to shorten connection grid The length of the wire Wgj of pad GPj and source lead SL.It follows that in the encapsulation PKG8 shown in Figure 13, it is also possible to fully Ground reduces the stray inductance for being present in wire Wgj.It follows that pressure voltage applying to MOSFET above of insulating can be suppressed Plus, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, in the encapsulation shown in Figure 13 In PKG8, it is also possible to seek the reliability of semiconductor device to improve.
Additionally, Figure 14 is the figure in a section of the encapsulation PKG8 for representing this variation 2.As shown in figure 14, take in chip On load portion PLT2, semiconductor chip CHP2 is equipped with via conductive adhesive material PST.And, for example, semiconductor chip CHP2（Gate pads）With grid lead GL（Grid lead post portion GPST）Electrically connect via wire Wgm.Additionally, dotted line part table Show the part covered by sealing body.
Then, illustrate one of other mounting means of the switch element of this variation 2.Figure 15 is to represent this variation 2 Encapsulation PKG9 mounting structure figure.The structure of the structure of the encapsulation PKG9 shown in Figure 15 and the encapsulation PKG3 shown in Fig. 5 is substantially It is identical.Difference is the outer shape of encapsulation.Like this, technological thought of the invention is can be applied not only to shown in Fig. 5 Encapsulation PKG3, it is also possible to suitable for encapsulation PKG9 as shown in Figure 15.That is, in the envelope that switch element is installed composition In dress, there are various generic encapsulations, the technological thought of the present invention can be applied to for example with the encapsulation PKG3 and Figure 15 shown in Fig. 5 Shown encapsulation PKG9 is the various generic encapsulations of representative.Specifically, the encapsulation PKG9 according to Figure 15, in shape Into on the semiconductor chip CHP1 for having junction type FET, also it is equipped with being formed with the semiconductor chip CHP2 of MOSFET, therefore, it is possible to The drain electrode of source pad SPj and the back side for being formed in semiconductor chip CHP2 is directly connected to.It follows that according to Figure 15 institutes The encapsulation PKG9 for showing, due to the drain electrode of the source electrode and MOSFET of junction type FET being directly connected to can not also using wire, so The stray inductance between the drain electrode of MOSFET and the source electrode of junction type FET can almost entirely be removed（Lse1, Lse2 of Fig. 2）. Therefore, the encapsulation PKG9 according to Figure 15, it is also possible to suppress applying of the pressure voltage above of insulation to MOSFET, thus, The avalanche breakdown of the MOSFET of cascade Connection can effectively be suppressed.Its result is, according to this variation 2, can seek partly to lead The reliability of body device is improved.
Additionally, Figure 16 is the figure in a section of the encapsulation PKG9 for representing this variation 2.As shown in figure 16, take in chip On load portion PLT, semiconductor chip CHP1 is equipped with via conductive adhesive material PST, on semiconductor chip CHP1, Jing By conductive adhesive material（It is not shown）And it is equipped with semiconductor chip CHP2.And, for example, semiconductor chip CHP2（Grid Pad）With grid lead GL（Grid lead post portion GPST）Electrically connected by wire Wgm.Additionally, dotted line part is represented by sealing The part that body is covered.
3 ＞ of ＜ variations
Next, illustrating the mounting structure of the encapsulation PKG10 of this variation 3.Figure 17 is the encapsulation for representing this variation 3 The mounting structure figure of PKG10.The structure of the encapsulation PKG10 shown in Figure 17 is roughly the same with the structure of the encapsulation PKG1 shown in Fig. 3. Difference is the outer shape of encapsulation.Like this, technological thought of the invention can be applied not only to the encapsulation shown in Fig. 3 PKG1, it is also possible to suitable for encapsulation PKG10 as shown in Figure 17.That is, in the encapsulation that switch element is installed composition In, there are various generic encapsulations, the technological thought of the present invention for example can be to shown in the encapsulation PKG1 and Figure 17 shown in Fig. 3 Encapsulation PKG10 is that the various generic encapsulations of representative are improved and realize.Specifically, in the encapsulation shown in Figure 17 In PKG10, for example, it is also possible to shorten the distance between gate pads GPj and source lead SL, therefore, it is possible to shorten connection grid The length of the wire Wgj of pole pad GPj and source lead SL.It follows that in the encapsulation PKG10 shown in Figure 17, it is also possible to Fully reduce being present in the stray inductance of wire Wgj.It follows that can suppress to insulate it is pressure more than voltage to MOSFET Applying, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, in the envelope shown in Figure 17 In dress PKG10, it is also possible to seek the reliability of semiconductor device to improve.
Additionally, Figure 18 is the figure in a section of the encapsulation PKG10 for representing this variation 3.As shown in figure 18, take in chip On load portion PLT1, semiconductor chip CHP1 is equipped with via conductive adhesive material PST.And, for example, semiconductor chip CHP1（Gate pads GPj）With source lead SL（Source lead post portion SPST）Electrically connected by wire Wgj.Additionally, dotted line Portion represents the part covered by sealing body.
Then, illustrate one of other mounting means of the switch element of this variation 3.Figure 19 is to represent this variation 3 Encapsulation PKG11 mounting structure figure.The structure of the encapsulation PKG11 shown in Figure 19 is big with the structure of the encapsulation PKG3 shown in Fig. 5 Cause identical.Difference is the outer shape of encapsulation.Like this, technological thought of the invention is can be applied not only to shown in Fig. 5 Encapsulation PKG3, it is also possible to suitable for encapsulation PKG11 as shown in Figure 19.That is, constituting switch element is installed Encapsulation in, there are various generic encapsulations, the technological thought of the present invention for example can suitable for the encapsulation PKG3 shown in Fig. 5 and Encapsulation PKG11 shown in Figure 19 is the various generic encapsulations of representative.Specifically, the encapsulation according to Figure 19 PKG11, is being formed with the semiconductor chip CHP1 of junction type FET, is also being equipped with being formed with the semiconductor chip CHP2 of MOSFET, Therefore, it is possible to the drain electrode of source pad SPj and the back side for being formed in semiconductor chip CHP2 is directly connected to.It follows that Encapsulation PKG11 according to Figure 19, due to can not also using wire will be the drain electrode of the source electrode and MOSFET of junction type FET straight Connect in succession, it is possible to almost entirely removing the stray inductance between the drain electrode of MOSFET and the source electrode of junction type FET（Fig. 2's Lse1、Lse2）.Therefore, the encapsulation PKG11 according to Figure 19, it is also possible to suppress the pressure voltage above of insulation to MOSFET Applying, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to this variation 3, The reliability of semiconductor device can be sought to improve.
Additionally, Figure 20 is the figure in a section of the encapsulation PKG11 for representing this variation 3.As shown in figure 20, take in chip On load portion PLT, semiconductor chip CHP1 is equipped with via conductive adhesive material PST, on semiconductor chip CHP1, Jing By conductive adhesive material（It is not shown）And it is equipped with semiconductor chip CHP2.And, for example, semiconductor chip CHP2（Grid Pad）With grid lead GL（Grid lead post portion GPST）Electrically connected by wire Wsm.Additionally, dotted line part is represented by sealing The part that body is covered.
4 ＞ of ＜ variations
Next, illustrating the mounting structure of the encapsulation PKG12 of this variation 4.Figure 21 is the encapsulation for representing this variation 4 The mounting structure figure of PKG12.The structure of the encapsulation PKG12 shown in Figure 21 is roughly the same with the structure of the encapsulation PKG1 shown in Fig. 3. Difference is the outer shape of encapsulation.Specifically, the packaged type of the encapsulation PKG12 of this variation 4 is SOP（Small Outline Package：Small-sized package）.Like this, technological thought of the invention can be applied not only to the envelope shown in Fig. 3 Dress PKG1, it is also possible to suitable for encapsulation PKG12 as shown in Figure 21.That is, in the envelope that switch element is installed composition In dress, there are various generic encapsulations, the technological thought of the present invention for example can be to shown in the encapsulation PKG1 and Figure 21 shown in Fig. 3 Encapsulation PKG12 be that the various generic encapsulations of representative are improved and realize.Specifically, in the encapsulation shown in Figure 21 In PKG12, for example, it is also possible to shorten the distance between gate pads GPj and source lead SL, therefore, it is possible to shorten connection grid The length of the wire Wgj of pole pad GPj and source lead SL.It follows that in the encapsulation PKG12 shown in Figure 21, it is also possible to Fully reduce being present in the stray inductance of wire Wgj.It follows that can suppress to insulate it is pressure more than voltage to MOSFET Applying, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, in the envelope shown in Figure 21 In dress PKG12, it is also possible to seek the reliability of semiconductor device to improve.
Additionally, Figure 22 is the figure in a section of the encapsulation PKG12 for representing this variation 4.As shown in figure 22, take in chip On load portion PLT1, via conductive adhesive material（It is not shown）And it is equipped with semiconductor chip CHP1.And, for example, quasiconductor Chip CHP1（Gate pads GPj）With source lead SL（Source lead post portion SPST）Electrically connected by wire Wgj.Additionally, In this variation 4, for example, as shown in figure 22, the one of chip carrying portion PLT1, semiconductor chip CHP1, wire Wgj and lead The sealing body MR sealing is made up of resin by part etc..Now, if analogizing like that from Figure 21 and Figure 22, in encapsulation PKG12 （SOP is encapsulated）In, sealing body MR is in approximately parallelepiped body shape, with the 1st side and 2nd side relative with the 1st side.And And, grid lead GL and source lead SL are constituted in the way of projecting from the 1st side of sealing body MR, and drain lead DL is with from envelope The mode that 2nd side of solid MR projects is constituted.
Then, illustrate one of other mounting means of the switch element of this variation 4.Figure 23 is to represent this variation 4 Encapsulation PKG13 mounting structure figure.The structure of the encapsulation PKG13 shown in Figure 23 is big with the structure of the encapsulation PKG3 shown in Fig. 5 Cause identical.Difference is the outer shape of encapsulation.Specifically, the packaged type of the encapsulation PKG13 of this variation 4 is SOP （Small Outline Package）.Like this, technological thought of the invention can be applied not only to the encapsulation shown in Fig. 5 PKG3, it is also possible to suitable for encapsulation PKG13 as shown in Figure 23.That is, in the encapsulation that switch element is installed composition In, there are various generic encapsulations, the technological thought of the present invention for example can be suitable for the encapsulation PKG3 and Figure 23 institutes shown in Fig. 5 The encapsulation PKG13 for showing is the various generic encapsulations of representative.Specifically, the encapsulation PKG13 according to Figure 23, in shape Into on the semiconductor chip CHP1 for having junction type FET, also it is equipped with being formed with the semiconductor chip CHP2 of MOSFET, therefore, it is possible to The drain electrode of source pad SPj and the back side for being formed at semiconductor chip CHP2 is directly connected to.It follows that according to Figure 23 institutes The encapsulation PKG13 for showing, due to the drain electrode of the source electrode and MOSFET of junction type FET being directly connected to can not also using wire, institute Can almost entirely remove the stray inductance between the drain electrode of MOSFET and the source electrode of junction type FET（The Lse1 of Fig. 2, Lse2）.Therefore, the encapsulation PKG13 according to Figure 23, it is also possible to suppress pressure voltage the applying to MOSFET above of insulation Plus, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to this variation 4, can The reliability of semiconductor device is sought to improve.
Additionally, Figure 24 is the figure in a section of the encapsulation PKG13 for representing this variation 4.As shown in figure 24, take in chip On load portion PLT, via conductive adhesive material（It is not shown）And semiconductor chip CHP1 is equipped with, in semiconductor chip CHP1 On, via conductive adhesive material（It is not shown）And it is equipped with semiconductor chip CHP2.And, for example, semiconductor chip CHP1 （Gate pads GPj）With source lead SL（Source lead post portion SPST）Electrically connected by wire Wgj.Additionally, in this deformation In example 4, for example, as shown in figure 24, chip carrying portion PLT, semiconductor chip CHP1, semiconductor chip CHP2, wire Wgj and draw The sealing body MR sealing is made up of resin by part of line etc..Now, side of the part for lead from sealing body MR both sides It is prominent.
（Embodiment 2）
In above-mentioned embodiment 1, the research point related to packaging structure is illustrated, but in present embodiment 2, explanation The research point related to device configuration.
The layout structure ＞ of ＜ laminated semiconductor chips
Figure 25 is the layout structure figure of the semiconductor chip for representing present embodiment 2.Semiconductor chip shown below Layout structure, for example, illustrates will be with carborundum（Si）Band gap to represent compares silicon（Si）Formation of the big material as material Have on the semiconductor chip CHP1 of junction type FET, stacking ground is carried with silicon（Si）Formation for material has the semiconductor core of MOSFET The example of piece CHP2.In fig. 25, semiconductor chip CHP1 rectangular shapeds, in the semiconductor chip CHP1 of the rectangular shape Outer region is formed with terminating region TMj.Terminating region TMj be in order to ensure it is pressure and arrange region.And, termination area The inside region of domain TMj becomes active（active）Region ACTj.Multiple junction type FET are formed with active region ACTj.
Terminating region TMj is arranged on the outer region of semiconductor chip CHP1, but in being partly into of terminating region TMj Portion, and gate pads GPj are formed with the region.Gate pads GPj via grid wiring be formed in active region Each gate electrode connection of the multiple junction type FET in ACTj.Here, in fig. 25, gate pads GPj are configured in semiconductor chip The right central part of CHP1.In other words, gate pads GPj deflection the right configuration, and with relative to the center extended along left and right The symmetrical mode of line is configured.Thereby, it is possible to suppress the grid cloth of each gate electrode and gate pads GPj that connect multiple junction type FET The range deviation of line.Therefore, the layout structure according to Figure 25, obtaining can as one man using being formed in semiconductor chip The advantage of the characteristic of the multiple junction type FET in CHP1.
Source pad SPj is formed with the active region ACTj of semiconductor chip CHP1.Source pad SPj and formation The source region electrical connection of the junction type FET in active region ACTj.And, it is equipped with source pad SPj rectangular The semiconductor chip CHP2 of shape.Multiple MOSFET are formed with semiconductor chip CHP2, semiconductor chip CHP2's Source pad SPm and gate pads GPm are formed with interarea.Source pad SPm is electrically connected with the source region of MOSFET, grid Pad GPj is electrically connected with the gate electrode of MOSFET.
Figure 26 is the figure of other layout structures of the laminated semiconductor chip for representing present embodiment 2.Cloth shown in Figure 26 Office's structure is roughly the same with the layout structure shown in Figure 25.The difference of Figure 26 and Figure 25 is to tie in the layout shown in Figure 25 In structure, gate pads GPj are configured in the right central part, in contrast, in the layout structure shown in Figure 26, gate pads GPj It is partial to the lower right corner of semiconductor chip CHP1 and configures.Like this, in fig. 26, by being configured in semiconductor chip CHP1's Lower right corner, for example, as shown in fig. 6, the distance from gate pads GPj to source lead SL can be made most short.That is, logical Cross using the layout structure shown in Figure 26, the length of wire Wgj of connection gate pads GPj and source lead SL can be made most It is short, thereby, it is possible to minimize the stray inductance for being present in wire Wgj.
Then, Figure 27 is the sectional view of cutting at the line A-A of Figure 25 and Figure 26.As shown in figure 27, in quasiconductor The back side of substrate S UBj is formed with drain electrode DEj, in the interarea of Semiconductor substrate SUBj（Surface）On be formed with drift layer DFTj. And, active region ACTj is formed with drift layer DFTj, the gate electrode of junction type FET is formed with active region ACTj And source region.In the end of active region ACTj, it is formed with for guaranteeing pressure terminating region TMj, in active region Source pad SPj is formed with ACTj.It is formed with the way of the end for covering source pad SPj for example by silicon oxide film structure Into dielectric film IL1.Structure before this is the construction of the semiconductor chip CHP1 for being formed with junction type FET, is formed with this On the semiconductor chip CHP1 of junction type FET, it is equipped with being formed with the semiconductor chip CHP2 of MOSFET.
Specifically, in source pad SPj exposed, for example, via conductive adhesive material（It is not shown）And with leakage Electrode DEm is contacted.Drain electrode DEm is formed in the back side of Semiconductor substrate SUBm, in Semiconductor substrate SUBm with the back side is The interarea of opposition side（Surface）On, it is formed with drift layer DFTm.And, active region ACTm is formed with drift layer DFTm, At the both ends of active region ACTm, it is formed with for guaranteeing pressure terminating region TMm.Formed in active region ACTm There are gate electrode and the source region of MOSFET.Source electrode weldering is formed with the way of across active region ACTm and terminating region TMm Disk SPm.It is formed with dielectric film IL2 in the way of the end for covering source pad SPm, but source pad SPm is most Surface region is exposed from dielectric film IL2.Thus, it is being formed with the semiconductor chip CHP1 of junction type FET, is being equipped with being formed with The semiconductor chip CHP2 of MOSFET.
As shown in figure 27, in be enclosed in by source pad SPj in the way of semiconductor chip CHP2 is mounted in into quasiconductor On chip CHP1.Therefore, be formed in semiconductor chip CHP2 the back side drain electrode DEm be formed in semiconductor chip CHP1's Source pad SPj on surface passes through conductive adhesive material not via wire（It is not shown）Directly contact.It means that, can Stray inductance between the drain electrode of source electrode and MOSFET that folder has junction type FET is removed almost entirely.I.e., as shown in figure 27, By the structure for directly carrying semiconductor chip CHP2 on semiconductor chip CHP1, it is not necessary to for connecting the source of junction type FET The wire of the drain electrode of pole and MOSFET.In the case of using wire, the stray inductance for being present in wire becomes problem, but according to The drain electrode of the source electrode and MOSFET of junction type FET is directly connected to by the layout structure of present embodiment 2 in which can not use wire. It follows that the stray inductance between the drain electrode of MOSFET and the source electrode of junction type FET almost entirely can be removed（Fig. 2's Lse1、Lse2）.It will be apparent from the above that, according to present embodiment 2, pressure voltage applying to MOSFET above of insulating can be suppressed Plus, thereby, it is possible to effectively suppress the avalanche breakdown of the MOSFET of cascade Connection.Its result is, according to present embodiment 2, energy The reliability of semiconductor device is enough sought to improve.
In addition, as shown in figure 27, according to the layout structure of present embodiment 2, due to being configured with active region ACTj Source pad SPj, it is possible to the electric current that increase is flowed in junction type FET.And, in this case, due to can also realize source The large area of pole pad SPj, so can also increase the area of the semiconductor chip CHP2 being mounted in source pad SPj. That is, the area that can increase semiconductor chip CHP2 means, by increasing capacitance it is possible to increase the MOSFET being formed in semiconductor chip CHP2 Quantity, its result is to increase the electric current flowed in multiple MOSFET entirety.Like this, according to present embodiment 2 Layout structure, as the electric current and the flowing in multiple MOSFET entirety that flow in multiple junction type FET entirety can be increased Electric current, it is possible to easily realizing the high current of the switch element of junction type FET and MOSFET cascade Connection.And And, according to present embodiment 2, due to using using the carbon that high withstand voltage and low on-resistance can be realized in the principle compared with silicon The junction type FET of SiClx, it is possible to provide the switch element for realizing high current, high withstand voltage and low on-resistance simultaneously.
Variation ＞ of ＜ layout structures
Then, other layout structures of the laminated semiconductor chip of present embodiment 2 are illustrated.Figure 28 is to represent this variation Laminated semiconductor chip layout structure figure.As shown in figure 28, semiconductor chip CHP1 rectangular shapeds, in the rectangular shape The outer region of semiconductor chip CHP1 be formed with terminating region TMj.And, in terminating region, the inside region of TMj is formed There are active region ACTj, gate pads GPj and source pad SPj.Here, this variation is characterised by, active region ACTj, Gate pads GPj and source pad SPj are configured in the way of the coincidence of not plane.That is, as shown in figure 28, being formed with junction type The active region ACTj of FET is configured in the way of avoiding gate pads GPj and source pad SPj.And, in source pad SPj On be equipped with semiconductor chip CHP2.
In addition, Figure 29 is the figure of other layout structures of the laminated semiconductor chip for representing this variation.Shown in Figure 29 Layout structure is roughly the same with the layout structure shown in Figure 28.The difference of Figure 29 and Figure 28 is, in the layout shown in Figure 28 In structure, gate pads GPj are configured in the right central part, in contrast, in the layout structure shown in Figure 29, gate pads GPj is partial to the lower right corner of semiconductor chip CHP1 and configures.
Next, Figure 30 is the sectional view of cutting at the line A-A of Figure 28 and Figure 29.As shown in figure 30, partly leading The back side of body substrate S UBj is formed with drain electrode DEj, in the interarea of Semiconductor substrate SUBj（Surface）On be formed with drift layer DFTj.Active region ACTj is formed with drift layer DFTj, termination area is formed with the exterior lateral area of active region ACTj Domain TMj.The gate electrode GE and source region SR of junction type FET are formed with active region ACTj.And, in active region ACTj Dielectric film IL1 is formed with upper and terminating region TMj, source pad SPj is formed with dielectric film IL1.Here, in this change In shape example, vital point is that source pad SPj is not formed in active region ACTj, and is formed on the TMj of termination area domain. That is, in this variation, in top view, active region ACTj and source pad SPj are configured in the way of misaligned, source electrode Pad SPj is configured on the TMj of terminating region.Additionally, in fig. 30, eliminate the semiconductor core being configured in source pad SPj The diagram of piece CHP2.That is, in fig. 30, also in the same manner as Figure 27, semiconductor chip is equipped with source pad SPj CHP2, as its structure is identical, so in fig. 30, eliminates the semiconductor chip CHP2's that is configured in source pad SPj Diagram.
According to such this variation for constituting, effect shown below can be obtained.That is, carry in source pad SPj Semiconductor chip CHP2.In this case, in source pad SPj, effect has stress.But, in this variation, it is formed with knot What the active region ACTj of type FET was not formed in source pad SPj just descends region, therefore, it is possible to prevent in active region Stress is applied with ACTj.That is, according to this variation, it is unnecessary to be prevented from being applied with active region ACTj Stress, the mechanical damage of the junction type FET therefore, it is possible to prevent from being formed in active region ACTj.
In addition, on the surface of the semiconductor chip CHP2 being equipped in source pad SPj, be formed with gate pads GPm and Source pad SPm, is welded by wire on these pads and is connected with wire.Also producing in the wire welding sequence should Power, but in this variation, as semiconductor chip CHP2 and active region ACTj is configured in the way of the coincidence of not plane, so The stress for being prevented from producing in wire welding sequence is directly delivered to active region ACTj.Its result is, according to this deformation Example laminated semiconductor chip layout structure, can suppress in the carrying of semiconductor chip CHP2 or wire weld when produce Stress impact is brought on the characteristic of the junction type FET in the active region ACTj for being formed in semiconductor chip CHP1.That is, according to this Variation, using the teaching of the invention it is possible to provide assembly yield height and the high semiconductor device of reliability.
The device configuration ＞ of ＜ MOSFET
Next, explanation is formed in of the device configuration of the MOSFET on semiconductor chip CHP2.Figure 31 is to represent The sectional view of of the device configuration of the MOSFET of present embodiment 2.As shown in figure 31, for example, by being imported with p-type impurity The back side of Semiconductor substrate SUBm that constitutes of silicon, on the other hand for example, be formed with the drain electrode DEm being made up of golden film, half The interarea side of conductor substrate S UBm, is formed with the drift layer DFTm being made up of n-type semiconductor region.Formed on drift layer DFTm Have body region PR being made up of p-type semiconductor region, in be enclosed in by body region PR in the way of be formed with by N-shaped half The source region SR that conductive region is constituted.The surface region of body region PR clamped by source region SR and drift layer DFTm The function as channel formation region.And, the shape in the way of electrically connecting with source region SR and body region PR both sides Into active electrode SE.And, the surface of the drift layer DFTm on comprising channel formation region for example, is formed with by oxygen The gate insulating film GOX that SiClx film is constituted, is formed with gate electrode G on gate insulating film GOX.
In such MOSFET for constituting, for example, it is configured to, electronics is passed through body region PR from source region SR Surface channel formation region, and from drift layer DFTm to the drain electrode DEm at the back side for being formed in Semiconductor substrate SUBm flow It is dynamic, it is the so-called construction for being referred to as longitudinal type MOSFET.The advantage of longitudinal type MOSFET is, due to being formed in high-density On semiconductor chip CHP2, so becoming the big MOSFET of electric current density.Therefore, by utilizing in the switch element of the present invention Longitudinal type MOSFET, can realize the big switch element of electric current density.
For example, in the case of the layout structure shown in Figure 28 and Figure 29, can be effectively prevented based on to being formed in The stress of the junction type FET in source region ACTj and caused deterioration in characteristics, on the other hand, the area of source pad SPj is less.Should In the case of, the formation being configured in source pad SPj has the area of the semiconductor chip CHP2 of MOSFET also less, but as shape Into the MOSFET in semiconductor chip CHP2, as long as using the longitudinal type MOSFET shown in Figure 31, even less chip face Product, it is also possible to realize the MOSFET of larger current density.Its result is the switch element entirety that can increase cascade Connection Electric current density.That is, by especially taking the layout structure shown in Figure 28 or Figure 29, using the teaching of the invention it is possible to provide following high performance Switch element, though be formed with the area of semiconductor chip CHP2 of MOSFET it is less in the case of, it is also possible to by using Longitudinal type MOSFET shown in Figure 31 is effectively prevented based on the stress to the junction type FET being formed in active region ACTj and causes Deterioration in characteristics, and be able to ensure that high current.
The technical task ＞ had found by ＜ the present inventor
Next, the new technique problem had found by explanation the present inventor.Figure 32 is the switch unit for representing cascade Connection The figure of the current path in part.Figure 32's（a）It is the figure of current path when representing connection, Figure 32's（b）When being to represent disconnection The figure of the current path of the leakage current of flowing.Such as Figure 32（a）It is shown, when connecting, leakage of rated current Id from junction type FETQ1 Flow to the source electrode of MOSFETQ2 pole.That is, rated current Id is from the drain D of the switch element of cascade Connection to source S stream It is dynamic.Now, the drain voltage of the MOSFETQ2 before MOSFETQ2 cut-offs（The voltage of intermediate node Se）Can be according to MOSFETQ2 The product of conducting resistance and rated current Id obtain.For example, if conducting resistance is 10m Ω and rated current Id is 40A, in the middle of The voltage of node Se is 0.4V.Drain voltage of the voltage of intermediate node Se for MOSFETQ2, and also for junction type FETQ1's Source voltage, therefore, the grid voltage of the junction type FETQ1 on the basis of the source voltage of junction type FETQ1 be voltage Vgs for- 0.4V。
In the case where the switch element for making cascade Connection changes from on-state to off-state, such as Figure 32 （a）It is shown, apply the state of 15V from the gate electrode Gm to MOSFETQ2, such as Figure 32（b）Shown, to MOSFETQ2 grid electricity Pole Gm applies 0V.MOSFETQ2 is due to the MOSFET for closed type, so ending when 0V is applied to gate electrode Gm.
During MOSFETQ2 is ended, in the starting stage, raceway groove fades away, therefore, the drain electrode of MOSFETQ2 Conducting resistance between source electrode is gradually increasing.Junction type FETQ1 used in the switch element of cascade Connection is normally opened Type, in the starting stage for ending MOSFETQ2, as the voltage Vgs of junction type FETQ1 is -0.4V, so junction type FETQ1 is maintained Conducting state.It follows that drain electrode of the electric current from junction type FETQ1（For example, in the application of supply voltage 300V, drain voltage For 300V or so）Flow to the source electrode of junction type FETQ1.Therefore, because the drain voltage of MOSFETQ2（The electricity of intermediate node Se Pressure）It is the product of the drain current that the conducting resistance that increases with the disappearance of raceway groove and the drain electrode from junction type FETQ1 are flowed into, institute With the drain voltage of MOSFETQ2（The voltage of intermediate node Se）It is gradually increasing from 0.4V.
Then, when the raceway groove of MOSFETQ2 is wholly absent MOSFETQ2 is completely switched off when, by from junction type FETQ1 flow into Electric current and intermediate node Se accumulation have electric charge, therefore, the drain voltage of MOSFETQ2（The voltage of intermediate node Se）Enter one Step rises, and rises to the blanking voltage of junction type FETQ1（For example, 5V～15V or so）.When the state is become, junction type FETQ1 cuts Only, the drain current of junction type FETQ1 does not flow.That is, the drain voltage of MOSFETQ2（The voltage of intermediate node Se）Stop rising, And maintain the state.
But, the inventors discovered that, in the switch element of cascade Connection, even if in the voltage Vgs of junction type FETQ1 For -5V～-15V or so when, there is also the situation that leakage current Idl flows between the drain electrode of junction type FETQ1 and source electrode.When the leakage When electric current Idl flows, there is electric charge in intermediate node Se accumulations, therefore, the drain voltage of MOSFETQ2（The electricity of intermediate node Se Pressure）Rise.It follows that when above-mentioned leakage current Idl increases, the drain voltage of MOSFETQ2（The voltage of intermediate node Se）Can Can become MOSFETQ2 it is pressure more than（For example, more than 30V）Voltage.Its result is that MOSFETQ2 occurs snowslide action, most MOSFETQ2 may be caused breakdown eventually.As its countermeasure, as long as using the high-withstand voltage MOSFET of high pressure, it becomes possible to prevent The probability for stating the avalanche breakdown of MOSFET is raised, but in the case of the MOSFET using high withstand voltage, in order to ensure pressure Need to be designed to drift layer thicker.Like this, if thickening the thickness of the drift layer of low concentration, cause the electric conduction of MOSFET Resistance increases, therefore, the problem points that the conduction loss during connection of the switch element that can produce cascade Connection increases.Namely Say, in order to ensure the high performance of the switch element of cascade Connection, and prevent the avalanche breakdown of MOSFET, need to thickening Beyond the structure of the drift layer of low concentration, aspect implements research.Therefore, in present embodiment 2, in order to ensure cascade Connection Switch element high performance, and prevent the avalanche breakdown of MOSFET, research implemented to the device configuration of junction type FET. Hereinafter, illustrate the device configuration of the junction type FET of the present embodiment 2 obtained from applying research.
The device configuration ＞ of ＜ junction type FET
Figure 33 is the sectional view of the device configuration of the junction type FET for representing present embodiment 2.As shown in figure 33, this embodiment party The junction type FET of formula 2 has Semiconductor substrate SUBj, is formed with drain electrode DEj at the back side of Semiconductor substrate SUBj.The opposing party Face, is formed with drift layer DFTj in the interarea side with the back side for opposition side of Semiconductor substrate SUBj, on drift layer DFTj It is formed with multiple grooves（trench）TR.And, in the respective side and bottom surface of multiple groove TR, it is formed with gate electrode GE（ Referred to as area of grid）, it is formed with the way of being clamped between the gate electrode GE of the side and bottom surface that are formed at adjacent trenches TR Channel formation region.Source region SR is formed with the top of the channel formation region.In such junction type FET for constituting, lead to The voltage for suppressing to apply to gate electrode GE is crossed, growth of the depletion layer from gate electrode GE is controlled.Thus, when from grid electricity adjacent to each other On the other hand when the depletion layer of pole GE growths is connected, channel formation region disappears and realizes cut-off state, from adjacent to each other In the case that the depletion layer of gate electrode GE growth is not connected, forms channel formation region and realize conducting state.
Here, the characteristic point of the junction type FET of present embodiment 2 is, the long CL of raceway groove of channel formation region be 1 μm with On.In other words, the characteristic point of present embodiment 2 is that the distance between bottom and bottom of gate electrode GE of source region SR is More than 1 μm.Thus, as the raceway groove that can extend channel formation region is long, it is possible to improving raceway groove when junction type FET is turned on Electrostatic potential in forming region.It follows that according to present embodiment 2, with the device structure using a length of 0.5 μm or so of raceway groove Situation about making is compared, and the drain current suppressing for flowing can be obtained less between the drain electrode of junction type FET and source electrode.Like this, make The long CL of raceway groove be more than 1 μm of advantage be that it is possible to improve cut-off when channel formation region in electrostatic potential and can drop Low-leakage current, but think that the prolongation of the long CL of raceway groove itself also contributes to the reduction of leakage current.
And, in the case of the device configuration of the junction type FET shown in Figure 33, and Semiconductor substrate SUBj for becoming drain electrode Compared with the distance between source region SR, Semiconductor substrate SUBj is less with the distance between gate electrode GE.And, in junction type In the state of FET cut-offs, backward voltage is applied with drift layer DFTj in gate electrode GE（Reverse bias）.Its result thinks, closes The leakage current that flows in junction type FET when cut-off, and between Semiconductor substrate SUBj separated by a distance and source region SR Mobile phase ratio, mainly as the reverse current between short Semiconductor substrate SUBj and gate electrode GE（Leakage current）And flow It is dynamic.Therefore, according to present embodiment 2, after junction type FET cut-offs, can be greatly reduced between the drain electrode of junction type FET and source electrode The leakage current of flowing.It follows that according to present embodiment 2, can suppress by drain electrode and the source electrode in junction type FET when ending Between the leakage current for flowing and the drain voltage that causes MOSFET rise to voltage more than pressure, thereby, it is possible to effectively prevent Only there is snowslide action and to ultimately result in MOSFET breakdown in MOSFET.Additionally, the junction type of the groove construction according to Figure 33 FET, as junction type FET can be formed to high-density, so the big switch element of electric current density can be realized certainly.
Then, Figure 34 is the sectional view of other device configurations of the junction type FET for representing present embodiment 2.As shown in figure 34, Other junction types FET of present embodiment 2 has Semiconductor substrate SUBj, is formed with electric leakage at the back side of Semiconductor substrate SUBj Pole DEj.On the other hand, in Semiconductor substrate SUBj and the main surface side that the back side is opposition side, drift layer DFTj is formed with, On drift layer DFTj, multiple gate electrode GEs are formed with the way of separating and imbed.And, between adjacent gate electrode GE The surface of drift layer DFTj be formed with source region SR.The junction type FET shown in Figure 34 for so constituting is not for groove structure The so-called longitudinal type junction type FET for making.
In the junction type FET having configuration which, characteristic point lie also in channel formation region the long CL of raceway groove be 1 μm with On.In other words, characteristic point is the distance between bottom of bottom and the gate electrode GE of source region SR（The long CL of raceway groove）For 1 μm More than.Thus, as the raceway groove that can extend channel formation region is long, even if so in the junction type FET shown in Figure 34, also can Electrostatic potential in enough channel formation regions improved when ending.It follows that in the junction type FET shown in Figure 34, with use The situation of the device configuration that a length of 0.5 μm or so of raceway groove is compared, it is also possible to by what is flowed between the drain electrode of junction type FET and source electrode Drain current suppressing obtains less.Like this, the advantage for making the long CL of raceway groove be more than 1 μm is, due to improving ditch during cut-off Electrostatic potential in road forming region and leakage current can be reduced, furthermore, it is believed that the long CL of raceway groove prolongations of itself are also contributed to Lou The reduction of electric current.
The advantage of the junction type FET shown in Figure 34 is that device configuration simply can reduce manufacturing cost.And, in figure In junction type FET shown in 33, need to be formed in the side of raceway groove TR by methods such as highly difficult angle-tilt ion injection techniques and lead Electric type impurity（N-type impurity）, in contrast, in the junction type FET shown in Figure 34, it is not necessary to use to form gate electrode GE Highly difficult angle-tilt ion injection technique, has the advantages that to gate electrode GE the Impurity Distribution high precision for importing.That is, root According to the junction type FET shown in Figure 34, obtain being able to easily form the advantage of the consistent junction type FET of characteristic.
More than, the invention completed by the present inventor is specifically understood based on embodiment, but the present invention is not limited to Embodiment is stated, various changes can be carried out in the range of without departing from its main idea certainly.
For example, in the above-described embodiment, illustrate by gate driver circuit（Gate drivers）To drive MOSFET Gate electrode example, but it is also possible to be configured to by gate driver circuit while driving the gate electrode of junction type FET.The situation Under, by the gate electrode that junction type FET is controlled with gate driver circuit, the source voltage of junction type FET can be controlled into desired Level, accordingly, it is capable to access the effect of the surge voltage that can suppress intermediate node.In the case of such a construction, although terminal Quantity increases, but obtains providing the advantage of more low-loss switch element.
In addition, with regard to the packaged type illustrated in embodiment 1, lead-line configuration is also not limited to this.That is, grid The allocation position of pole lead, drain lead and source lead can carry out various changes.For example, encapsulation can be installed on During fitted lining bottom, the lead-line configuration for encapsulating is determined in the way of it can borrow existing lead-line configuration.In this case, it is not necessary to change peace Fitted lining bottom, it is also possible to suppress the caused cost with design alteration to increase.
And, the layout structure of laminated semiconductor chip is also not limited to the layout knot for especially illustrating in the description Structure, the shape of each semiconductor chip, the shape of pad, the shape in terminating region etc. are also not particularly limited.In addition, junction type FET Also do not limit with the construction of MOSFET, various existing constructions can be suitable for.And, the Impurity Distribution of device also can Freely change.For example, in a mosfet, it is also possible to make the impurity concentration on surface less to prevent punch-through, also, with depth Direction and be gradually increased the mode implanted dopant of impurity concentration.
Additionally, above-mentioned MOSFET is not limited to the situation for making gate insulating film be formed by oxide-film, it is contemplated that also comprising expansion Big gate insulating film and the MISFET that formed by dielectric film（Metal Insulator Semiconductor Field Effect Transistor：Conductor insulator semiconductor fet）.That is, in this bright book, using for ease of explanation The term of MOSFET, but the MOSFET used as the term for being intended to encompass MISFET in this bright book.
In addition, as the metal material of above-mentioned each wire, it is possible to use gold（Au）, billon, copper（Cu）, copper alloy, Aluminum（Al）, aluminium alloy etc..
The switch element of the present invention can for example be applied to power circuit, but be not limited to this, for example, it is also possible to be applied to Inverter, the computer of the inverter of idle call, the power governor of solar power system, hybrid electric vehicle or electric automobile Power module, the various equipment such as the inverter of White LED.
Industrial applicibility
The present invention can widely be used in the manufacturing industry of manufacture semiconductor device.
Description of reference numerals
ACTj active regions
ACTm active regions
CHP1 semiconductor chips
CHP2 semiconductor chips
CL raceway grooves are long
CLP clips
D drains
D1 drains
D2 drains
DEj drain electrodes
DEm drain electrodes
DFTj drift layers
DFTm drift layers
Dj1 drains
Dj2 drains
DL drain leads
Dm drains
Dm1 drains
Dm2 drains
G gate electrodes
GE gate electrodes
Gj gate electrodes
Gj1 gate electrodes
Gj2 gate electrodes
GL grid leads
Gm gate electrodes
Gm1 gate electrodes
Gm2 gate electrodes
GOX gate insulating films
GPj gate pads
GPm gate pads
GPST grid lead posts portion
Id rated current
Idl leakage currents
IL1 dielectric films
IL2 dielectric films
Lgi1 stray inductances
Lgi2 stray inductances
LL load inductances
Ls stray inductances
Lse1 stray inductances
Lse2 stray inductances
MR sealing body
PKG1 is encapsulated
PKG2 is encapsulated
PKG3 is encapsulated
PKG4 is encapsulated
PKG5 is encapsulated
PKG6 is encapsulated
PKG7 is encapsulated
PKG8 is encapsulated
PKG9 is encapsulated
PKG10 is encapsulated
PKG11 is encapsulated
PKG12 is encapsulated
PKG13 is encapsulated
PLT chip carrying portions
PLT1 chip carrying portions
PLT2 chip carrying portions
PR body regions
Q1 junction type FET
Q1a junction type FET
Q1b junction type FET
Q2 MOSFET
Q2a MOSFET
Q2b MOSFET
S source electrodes
S1 source electrodes
S2 source electrodes
SE source electrodes
Se intermediate nodes
Sj source electrodes
Sj1 source electrodes
Sj2 source electrodes
SL source leads
Sm source electrodes
Sm1 source electrodes
Sm2 source electrodes
SPj source pads
SPm source pads
SPST source lead posts portion
SR source regions
SUBj Semiconductor substrates
SUBm Semiconductor substrates
TMj terminating region
TMm terminating region
TR grooves
Vak voltages
Vdsu voltages
Vdsmu voltages
Vdsmd voltages
Wds wires
Wgj wires
Wgm wires
Wsm wires

Claims (26)

1. a kind of semiconductor device, including：
The junction type FET of open type, which is leaked with the band gap material bigger than silicon as material with the 1st gate electrode, the 1st source electrode and the 1st Pole；With
The MOSFET of closed type, which drains with silicon as material with the 2nd gate electrode, the 2nd source electrode and the 2nd,
The 2nd drain electrode electrical connection of the 1st source electrode and the MOSFET of the junction type FET, also, the junction type FET The 1st gate electrode and the MOSFET the 2nd source electrode electrical connection, so as to form cascade Connection,
The semiconductor device is characterised by, including：
(a) the 1st semiconductor chip, its have the 1st surface and with the 1st surface for opposition side the 1st back side, wherein, in institute State be formed with the 1st surface the 1st source pad that electrically connects with the 1st source electrode of the junction type FET and with the junction type 1st gate pads of the 1st gate electrode electrical connection of FET, the 1st back side are electric with the 1st drain electrode of the junction type FET Connection；
(b) the 2nd semiconductor chip, its have the 2nd surface and with the 2nd surface for opposition side the 2nd back side, wherein, in institute State be formed with the 2nd surface the 2nd source pad that electrically connects with the 2nd source electrode of the MOSFET and with the MOSFET The 2nd gate electrode electrical connection the 2nd gate pads, the 2nd back side is electrically connected with the 2nd drain electrode of the MOSFET Connect；
C () the 1st chip carrying portion, which has via the 1st conductive adhesive material and carries the 1st of the 1st semiconductor chip Upper surface；
D () drain lead, which is linked with the 1st chip carrying portion；
E () source lead, which is electrically insulated with the drain lead；
F () grid lead, which is electrically insulated with the drain lead and the source lead；
G () the 1st metallic conductor, the 1st gate pads and the source lead of the 1st semiconductor chip are electrically connected by which Connect；With
(h) sealing body, its by the 1st semiconductor chip, the 2nd semiconductor chip, one of the 1st chip carrying portion Point, a part for the drain lead, a part for the source lead, a part for the grid lead and the described 1st Metallic conductor sealing,
2nd back side electrical connection of the 1st source pad and the 2nd semiconductor chip of the 1st semiconductor chip,
2nd gate pads of the 2nd semiconductor chip and grid lead electrical connection,
2nd source pad of the 2nd semiconductor chip and source lead electrical connection,
1st gate pads of the 1st semiconductor chip with compared to other leads closer to the source lead side Formula is configured.
2. semiconductor device as claimed in claim 1, it is characterised in that
2nd gate pads and the grid lead of the 2nd semiconductor chip are electrically connected by the 2nd metallic conductor,
2nd gate pads of the 2nd semiconductor chip are drawn with the closer grid compared with the 2nd source pad The mode of line is configured.
3. semiconductor device as claimed in claim 2, it is characterised in that
Conductor width of the conductor width of the 1st metallic conductor more than the 2nd metallic conductor.
4. semiconductor device as claimed in claim 2, it is characterised in that
So that the 1st source pad phase of the 2nd back side of the 2nd semiconductor chip and the 1st semiconductor chip To mode, via the 2nd conductive adhesive material by the 2nd semiconductor-chip-mounting the 1st semiconductor chip institute State in the 1st source pad.
5. semiconductor device as claimed in claim 4, it is characterised in that
1st semiconductor chip by compared to other leads closer to being configured in the 1st core in the way of the source lead On piece equipped section.
6. semiconductor device as claimed in claim 4, it is characterised in that
2nd source pad and the source lead of the 2nd semiconductor chip is electrically connected by the 3rd metallic conductor.
7. semiconductor device as claimed in claim 6, it is characterised in that
1st metallic conductor, the 2nd metallic conductor and the 3rd metallic conductor are respectively welding lead.
8. semiconductor device as claimed in claim 7, it is characterised in that
For welding lead the 3rd metallic conductor exist it is a plurality of.
9. semiconductor device as claimed in claim 4, it is characterised in that
The 1st conductive adhesive material and the 2nd conductive adhesive material are any one in silver soldering agent and scolding tin.
10. semiconductor device as claimed in claim 6, it is characterised in that
The source lead has source lead post portion,
The grid lead has grid lead post portion,
1st metallic conductor and the 3rd metallic conductor are connected with the source lead post portion,
2nd metallic conductor is connected with the grid lead post portion.
11. semiconductor device as claimed in claim 10, it is characterised in that
The region and the grid that are connected with the 1st metallic conductor and the 3rd metallic conductor in the source lead post portion The region for being connected with the 2nd metallic conductor in stem portion, positioned at the 1st upper surface than the 1st chip carrying portion High position.
12. semiconductor device as claimed in claim 1, it is characterised in that
The sealing body has the 1st side and 2nd side relative with the 1st side,
The drain lead, the grid lead and the source lead are projected from the 1st side of the sealing body.
13. semiconductor device as claimed in claim 12, it is characterised in that
The drain lead is configured between the grid lead and the source lead.
14. semiconductor device as claimed in claim 1, it is characterised in that
Also include the 2nd chip carrying portion, which has the 2nd upper surface for carrying the 2nd semiconductor chip, with the 1st chip Equipped section is electrically insulated,
2nd back side of the 2nd semiconductor chip and the 2nd upper surface of the 2nd chip carrying portion are led via the 3rd Electrically binding material and electrically connect,
2nd upper surface of the 1st source pad and the 2nd chip carrying portion of the 1st semiconductor chip passes through 4th metallic conductor and electrically connect.
15. semiconductor device as claimed in claim 14, it is characterised in that
4th metallic conductor is welding lead.
16. semiconductor device as claimed in claim 14, it is characterised in that
Between the 1st chip carrying portion and the 2nd chip carrying portion, a part for the sealing body is configured with.
17. semiconductor device as claimed in claim 1, it is characterised in that
1st chip carrying portion also with the 1st upper surface for opposition side the 1st lower surface,
1st lower surface of the 1st chip carrying portion exposes from the sealing body.
18. semiconductor device as claimed in claim 1, it is characterised in that
The sealing body has the 1st side and 2nd side relative with the 1st side,
The grid lead and the source lead are projected from the 1st side of the sealing body,
The drain lead is projected from the 2nd side of the sealing body.
19. semiconductor device as claimed in claim 1, it is characterised in that
1st metallic conductor is also electrically connected with the 2nd source pad of the 2nd semiconductor chip,
1st metallic conductor is metallic plate.
20. semiconductor device as claimed in claim 19, it is characterised in that
The metallic plate is made up of copper product.
21. semiconductor device as claimed in claim 1, it is characterised in that
The junction type FET is with carborundum as material.
22. semiconductor device as claimed in claim 1, it is characterised in that
The junction type FET has：
Become the Semiconductor substrate of the 1st drain electrode；
The drift layer being formed on the interarea of the Semiconductor substrate；
It is formed in multiple grooves of the drift layer；
The 1st gate electrode being formed on the side and bottom surface of each groove of the plurality of groove；
The channel formation region being clamped between the gate electrode being formed on the side and bottom surface of adjacent trenches；With
The 1st source electrode being formed on the channel formation region,
The length of the channel formation region is more than 1 μm.
23. semiconductor device as claimed in claim 1, it is characterised in that
The junction type FET has：
Become the Semiconductor substrate of the 1st drain electrode；
The drift layer being formed on the interarea of the Semiconductor substrate；
It is formed in multiple grooves of the drift layer；
The 1st gate electrode being formed on the side and bottom surface of each groove of the plurality of groove；
The channel formation region being clamped between the gate electrode being formed on the side and bottom surface of the adjacent groove；With
The 1st source electrode being formed on the channel formation region,
The distance between the bottom of the 1st source electrode and bottom of the 1st gate electrode are more than 1 μm.
24. semiconductor device as claimed in claim 1, it is characterised in that
The junction type FET has：
Become the Semiconductor substrate of the 1st drain electrode；
The drift layer being formed on the interarea of the Semiconductor substrate；
Multiple described 1st gate electrode being formed on the drift layer separated from each other；With
The 1st source electrode that the surface of the drift layer between the 1st gate electrode being formed separately is formed,
The distance between the bottom of the 1st source electrode and bottom of the 1st gate electrode are more than 1 μm.
A kind of 25. semiconductor device, including：
The junction type FET of open type, which is leaked with the band gap material bigger than silicon as material with the 1st gate electrode, the 1st source electrode and the 1st Pole；With
The MOSFET of closed type, which drains with silicon as material with the 2nd gate electrode, the 2nd source electrode and the 2nd,
The 2nd drain electrode electrical connection of the 1st source electrode and the MOSFET of the junction type FET, also, the junction type FET The 1st gate electrode and the MOSFET the 2nd source electrode electrical connection, so as to form cascade Connection,
The semiconductor device is characterised by, including：
(a) the 1st semiconductor chip, its have the 1st surface and with the 1st surface for opposition side the 1st back side, wherein, in institute State be formed with the 1st surface the 1st source pad that electrically connects with the 1st source electrode of the junction type FET and with the junction type 1st gate pads of the 1st gate electrode electrical connection of FET, the 1st back side are electric with the 1st drain electrode of the junction type FET Connection；
(b) the 2nd semiconductor chip, its have the 2nd surface and with the 2nd surface for opposition side the 2nd back side, wherein, in institute State be formed with the 2nd surface the 2nd source pad that electrically connects with the 2nd source electrode of the MOSFET and with the MOSFET The 2nd gate electrode electrical connection the 2nd gate pads, the 2nd back side is electrically connected with the 2nd drain electrode of the MOSFET Connect；
C () the 1st chip carrying portion, which has via the 1st conductive adhesive material and carries the 1st of the 1st semiconductor chip Upper surface；
D () drain lead, which is linked with the 1st chip carrying portion；
E () source lead, which is electrically insulated with the drain lead；
F () grid lead, which is electrically insulated with the drain lead and the source lead；
G () the 1st metallic conductor, the 1st gate pads and the source lead of the 1st semiconductor chip are electrically connected by which Connect；
H () the 2nd metallic conductor, the 2nd gate pads and the grid lead of the 2nd semiconductor chip are electrically connected by which Connect,
I () the 3rd metallic conductor, the 2nd source pad and the source lead of the 2nd semiconductor chip are electrically connected by which Connect；With
(j) sealing body, its by the 1st semiconductor chip, the 2nd semiconductor chip, one of the 1st chip carrying portion Point, a part for the drain lead, a part for the source lead, a part for the grid lead, the 1st metal Conductor, the 2nd metallic conductor and the 3rd metallic conductor sealing,
So that the 1st source pad phase of the 2nd back side of the 2nd semiconductor chip and the 1st semiconductor chip To mode, via the 2nd conductive adhesive material by the 2nd semiconductor-chip-mounting the 1st semiconductor chip institute State in the 1st source pad,
1st gate pads of the 1st semiconductor chip with compared to other leads closer to the source lead side Formula is configured.
A kind of 26. semiconductor device, including：
The junction type FET of open type, which is leaked with the band gap material bigger than silicon as material with the 1st gate electrode, the 1st source electrode and the 1st Pole；With
The MOSFET of closed type, which drains with silicon as material with the 2nd gate electrode, the 2nd source electrode and the 2nd,
The 2nd drain electrode electrical connection of the 1st source electrode and the MOSFET of the junction type FET, also, the junction type FET The 1st gate electrode and the MOSFET the 2nd source electrode electrical connection, so as to form cascade Connection,
The semiconductor device is characterised by, including：
(a) the 1st semiconductor chip, its have the 1st surface and with the 1st surface for opposition side the 1st back side, wherein, in institute State be formed with the 1st surface the 1st source pad that electrically connects with the 1st source electrode of the junction type FET and with the junction type 1st gate pads of the 1st gate electrode electrical connection of FET, the 1st back side are electric with the 1st drain electrode of the junction type FET Connection；
(b) the 2nd semiconductor chip, its have the 2nd surface and with the 2nd surface for opposition side the 2nd back side, wherein, in institute State be formed with the 2nd surface the 2nd source pad that electrically connects with the 2nd source electrode of the MOSFET and with the MOSFET The 2nd gate electrode electrical connection the 2nd gate pads, the 2nd back side is electrically connected with the 2nd drain electrode of the MOSFET Connect；
C () the 1st chip carrying portion, which has via the 1st conductive adhesive material and carries the 1st of the 1st semiconductor chip Upper surface；
D () the 2nd chip carrying portion, which has via the 2nd conductive adhesive material and carries the 2nd of the 2nd semiconductor chip Upper surface, is electrically insulated with the 1st chip carrying portion；
E () drain lead, which is linked with the 1st chip carrying portion；
F () source lead, which is electrically insulated with the drain lead；
G () grid lead, which is electrically insulated with the drain lead and the source lead；
H () the 1st metallic conductor, the 1st gate pads and the source lead of the 1st semiconductor chip are electrically connected by which Connect；
I () the 2nd metallic conductor, the 2nd gate pads and the grid lead of the 2nd semiconductor chip are electrically connected by which Connect；
J () the 3rd metallic conductor, the 2nd source pad and the source lead of the 2nd semiconductor chip are electrically connected by which Connect；
K () the 4th metallic conductor, which is by the 1st source pad and the 2nd chip carrying portion of the 1st semiconductor chip The 2nd upper surface electrical connection；With
(l) sealing body, its by the 1st semiconductor chip, the 2nd semiconductor chip, one of the 1st chip carrying portion Point, a part for the 2nd chip carrying portion, a part for the drain lead, a part for the source lead, the grid A part for pole lead, the 1st metallic conductor, the 2nd metallic conductor, the 3rd metallic conductor and the 4th gold medal Category conductor sealing,
1st gate pads of the 1st semiconductor chip with compared to other leads closer to the source lead side Formula is configured.
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