JP5824135B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a power semiconductor device used in, for example, an inverter of an air conditioner, a DC / DC converter of a computer power supply, an inverter module of a hybrid vehicle or an electric vehicle.

Japanese Translation of PCT International Publication No. 2000-506313 (Patent Document 1) describes a technique for providing a switching element that achieves both low on-resistance and high breakdown voltage. Specifically, in Patent Document 1, a junction FET (Junction Field Effect Transistor) made of silicon carbide (SiC) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of silicon (Si) are cascode-connected. The configuration is described.

  Japanese Laid-Open Patent Publication No. 2008-198735 (Patent Document 2) has a configuration in which an FET made of SiC and a diode made of Si are connected in series in order to provide an element having a low on-voltage and a high withstand voltage. Have been described.

  Japanese Patent Laid-Open No. 2002-208673 (Patent Document 3) describes a structure in which a switching element and a diode are stacked with a flat plate connection terminal interposed therebetween in order to reduce the area of a power module.

  Japanese Patent Laying-Open No. 2010-206100 (Patent Document 4) describes a technique for preventing false spot-off by increasing the threshold voltage of a normally-off junction FET made of SiC. Specifically, the junction FET and the MOSFET are arranged on the SiC substrate, and the MOSFET is diode-connected to the gate electrode of the junction FET.

JP 2000-506313 A JP 2008-198735 A JP 2002-208673 A JP 2010-206100 A

  There is a switching element that uses a cascode connection method as a switching element that achieves both improvement in breakdown voltage and reduction in on-resistance. Switching elements using the cascode connection method are, for example, normally-on junction field effect transistors (FETs) that use a material with a larger band gap than silicon (Si), and normally-off types that use silicon (Si). A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is connected in series. According to this cascode connection type switching element, the withstand voltage can be secured by a junction FET having a large withstand voltage, and the on-resistance is reduced by a normally-on type junction FET and the on-resistance is reduced by a low withstand voltage MOSFET. A switching element that achieves both improvement and reduction in on-resistance can be obtained.

  In this cascode-connected switching element mounting configuration, a configuration in which a semiconductor chip in which a junction FET is formed and a semiconductor chip in which a MOSFET is formed is connected by a bonding wire is employed. In this configuration, due to the influence of the parasitic inductance existing in the bonding wire and the influence of the leakage current of the junction FET, a voltage larger than the design withstand voltage is applied between the source and drain of the MOSFET with a low withstand voltage during switching. The present inventor has newly found out. As described above, when a voltage higher than the design withstand voltage is applied to the MOSFET having a low withstand voltage, the MOSFET may be destroyed, leading to a decrease in reliability of the semiconductor device.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment is characterized in that a gate pad of a semiconductor chip on which a junction FET is formed is arranged so as to be closer to a source lead than other leads (gate lead or drain lead) It is.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one embodiment, the reliability of a semiconductor device can be improved. In addition, the electrical characteristics of the semiconductor device can be improved.

It is a figure which shows the circuit structure of the switching element which employ | adopted the cascode connection system. (A) It is a circuit diagram which shows the inverter using junction FET and MOSFET which were cascode-connected as a switching element. (B) is a figure which shows the waveform at the time of turning on the switching element which comprises an upper arm, (c) is a figure which shows the waveform at the time of turning off the switching element which comprises an upper arm. It is a figure which shows the mounting structure of the semiconductor device in Embodiment 1 of this invention. FIG. 10 is a diagram showing a mounting configuration of another semiconductor device according to the first embodiment. 10 is a diagram illustrating a mounting configuration of a semiconductor device according to Modification 1. FIG. FIG. 10 is a diagram illustrating a mounting configuration of another semiconductor device according to Modification 1. FIG. 10 is a diagram illustrating a mounting configuration of another semiconductor device according to Modification 1. It is sectional drawing which shows one cross section of FIG. FIG. 10 is a diagram illustrating a mounting configuration of another semiconductor device according to Modification 1. FIG. 10 is a cross-sectional view showing one cross section of FIG. 9. FIG. 10 is a diagram illustrating a mounting configuration of another semiconductor device according to Modification 1. (A) is a circuit diagram which shows the presence position of a parasitic inductance with the switching element in a prior art, (b) is a circuit diagram which shows the presence position of a parasitic inductance with the switching element in Embodiment 1. FIG. Moreover, (c) is a circuit diagram showing the presence position of the parasitic inductance together with the switching element in the first modification. FIG. 11 is a diagram illustrating a mounting configuration of a semiconductor device according to Modification 2. It is sectional drawing which shows one cross section of FIG. FIG. 10 is a diagram illustrating a mounting configuration of another semiconductor device according to Modification 2. It is sectional drawing which shows one cross section of FIG. FIG. 11 is a diagram illustrating a mounting configuration of a semiconductor device according to Modification 3. It is sectional drawing which shows one cross section of FIG. It is a figure which shows the mounting structure of the other semiconductor device in the modification 3. FIG. 20 is a cross-sectional view showing one cross section of FIG. 19. It is a figure which shows the mounting structure of the semiconductor device in the modification 4. It is sectional drawing which shows one cross section of FIG. It is a figure which shows the mounting structure of the other semiconductor device in the modification 4. It is sectional drawing which shows one cross section of FIG. 5 is a diagram showing a configuration of a laminated semiconductor chip in a second embodiment. FIG. FIG. 10 is a diagram showing another configuration of the laminated semiconductor chip in the second embodiment. It is sectional drawing cut | disconnected by the AA line of FIG. 25 and FIG. It is a figure which shows the structure of the laminated semiconductor chip in a modification. It is a figure which shows the other structure of the laminated semiconductor chip in a modification. It is sectional drawing cut | disconnected by the AA line of FIG. 28 and FIG. 7 is a cross-sectional view showing a device structure of a MOSFET in a second embodiment. FIG. It is a figure which shows the electric current path | route in the switching element connected in cascode. (A) is a figure which shows the electric current path at the time of ON, (b) is a figure which shows the electric current path of the leakage current which flows at the time of OFF. 6 is a cross-sectional view showing a device structure of a junction FET in Embodiment 2. FIG. It is sectional drawing which shows the other device structure of junction FET in Embodiment 2. FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Details of problems found by the inventor>
The importance of the electronics business to reduce environmental impact is increasing in the great social trend of global environmental conservation. In particular, power devices (power semiconductor devices) are used as power sources for consumer devices such as inverters for railway vehicles, hybrid vehicles, electric vehicles, inverters for air conditioners, and personal computers. Improvements in performance of power devices include infrastructure systems and consumer devices. Greatly contributes to the improvement of power efficiency. Improving power efficiency means that energy resources necessary for system operation can be reduced. In other words, carbon dioxide emissions can be reduced, that is, the environmental load can be reduced. For this reason, research and development for improving the performance of power devices has been actively conducted by each company.

Generally, a power device is made of silicon as in a large scale integrated circuit (LSI (Large Scale Integration)). However, in recent years, silicon carbide (SiC), which has a larger band gap than silicon, has attracted attention. Since SiC has a large band gap, its breakdown voltage is about 10 times that of silicon. From this, a device made of SiC can be made thinner than a device made of Si, and as a result, the resistance value (on-resistance value) Ron during conduction can be greatly reduced. Therefore, a device made of SiC can significantly reduce the conduction loss (Ron × i ² ) represented by the product of the resistance value Ron and the conduction current i, and can greatly contribute to the improvement of power efficiency. Focusing on these features, development of MOSFETs, Schottky diodes, and junction FETs using SiC has been underway in Japan and overseas.

  In particular, focusing on switching devices, the commercialization of junction FETs (JFETs) using SiC as a material has been advanced rapidly. This junction FET does not require, for example, a gate insulating film made of a silicon oxide film as compared with a MOSFET made of SiC. The problems represented can be avoided. In addition, since this junction FET can control the on / off of the channel by controlling the extension of the depletion layer due to the pn junction, it is possible to easily create a normally-off junction FET and a normally-on junction FET. . As described above, a junction FET made of SiC is superior in long-term reliability and has a feature that a device can be easily manufactured as compared with a MOSFET made of SiC.

  Among the junction FETs using SiC as a material, normally-on type junction FETs usually have a channel turned on and a current flows. When a channel needs to be turned off, a negative voltage is applied to the gate electrode to pn. The channel is turned off by extending the depletion layer from the junction. Therefore, if the junction FET is broken for some reason, the current continues to flow with the channel turned on. Normally, it is desirable from the viewpoint of safety (fail-safe) that the current does not flow when the junction FET is broken. However, in the normally-on type junction FET, the current continues to flow even when the junction FET is broken, so that the application can be used. Limited. Therefore, a normally-off type junction FET is desired from the viewpoint of fail-safe.

  However, normally-off type junction FETs have the following problems. That is, the gate electrode and the source region of the junction FET have a pn junction diode structure composed of a p-type semiconductor region (gate electrode) and an n-type semiconductor region (source region), respectively, and therefore, between the gate electrode and the source region. When the voltage becomes about 3V, the parasitic diode between the gate electrode and the source region is turned on. As a result, a large current may flow between the gate electrode and the source region, which may cause the junction FET to generate heat excessively and be destroyed. Therefore, in order to use the junction FET as a normally-off type switching element, the gate voltage is limited to a voltage as low as about 2.5 V, or the parasitic diode is not turned on, or between the gate electrode and the source region. It is desirable to use the diode in a state where the diode current is sufficiently small. In a normal MOSFET made of Si, a gate voltage of 0 to 15V or 20V is applied. Therefore, in order to use a normally-off type junction FET, in addition to the existing MOSFET gate drive circuit, a step-down circuit (DC / DC converter) that generates a voltage of about 2.5 V, a level conversion circuit, etc. Need to add. This design change, that is, the addition of parts, increases the cost of the entire system. From this, it is a junction FET that has the characteristics of excellent long-term reliability and easy to make, but the gate voltage for driving is greatly different from general MOSFETs, so when using a junction FET newly Therefore, a large design change including the drive circuit and the like is necessary, and there is a problem that the cost of the entire system increases.

  As a method for solving this problem, there is a cascode connection method. This cascode connection system is a system in which a normally-on junction FET made of SiC and a low voltage MOSFET made of Si are connected in series. When such a connection method is adopted, the gate drive circuit drives the low breakdown voltage MOSFET, so that it is not necessary to change the gate drive circuit. On the other hand, the breakdown voltage between the drain and the source can be determined by the characteristics of the junction FET having a high withstand voltage. Furthermore, even in the case of cascode connection, since the on-resistance of the junction FET and the low on-resistance of the low breakdown voltage MOSFET are connected in series, the on-resistance of the cascode-connected switching element can be kept relatively small. As described above, the cascode connection method may solve the problem of the normally-off type junction FET.

  FIG. 1 is a diagram showing a circuit configuration of a switching element employing a cascode connection method. As shown in FIG. 1, the switching element employing the cascode connection method has a configuration in which a normally-on junction FET Q1 and a normally-off MOSFET Q2 are connected in series between a source S and a drain D. Specifically, the junction FET Q1 is disposed on the drain D side, and the MOSFET Q2 is disposed on the source S side. That is, the source Sj of the junction FET Q1 is connected to the drain Dm of the MOSFET Q2, and the source Sm of the MOSFET Q2 is connected to the source S of the switching element. The gate electrode Gj of the junction FET Q1 is connected to the source S of the switching element, and the gate electrode Gm of the MOSFET Q2 is connected to a gate drive circuit (not shown).

  As shown in FIG. 1, a free wheel diode is connected in reverse parallel to the MOSFET Q2. This free wheel diode has a function of releasing the energy accumulated in the inductance by circulating the reverse current. That is, when the switching element shown in FIG. 1 is connected to a load including an inductance, when the switching element is turned off, a reverse current in a direction opposite to the direction in which the current of the MOSFET Q2 flows is generated by the inductance included in the load. For this reason, by providing a free wheel diode in anti-parallel with the MOSFET Q2, the reverse current is circulated to release the energy accumulated in the inductance.

  Such a connection method is a cascode connection method, and according to the switching element adopting the cascode connection method, first, a gate drive circuit (not shown) drives the gate electrode Gm of the MOSFET Q2. There is an advantage that it is not necessary to change the gate drive circuit from the case where a single unit is used as a switching element.

  Furthermore, since the junction FET Q1 uses a material typified by silicon carbide (SiC) having a larger band gap than silicon (Si) as a material, the withstand voltage of the junction FET Q1 increases. From this, the withstand voltage of the cascode-connected switching element is mainly determined by the characteristics of the junction FET Q1. Therefore, the withstand voltage required for MOSFET Q2 connected in series with junction FET Q1 can be made lower than that of a switching element using a single MOSFET. That is, even when a withstand voltage is required as the switching element, a MOSFET having a low withstand voltage (for example, about several tens of volts) can be used as the MOSFET Q2. For this reason, the on-resistance of MOSFET Q2 can be reduced. Furthermore, since the junction FET Q1 is composed of a normally-on type junction FET, the on-resistance of the junction FET Q1 can also be reduced. As a result, according to the cascode-bonded switching element, there is an advantage that the design change of the gate drive circuit is not required, and it is possible to achieve both the insulation resistance and the reduction of the on-resistance. The electrical characteristics of the (switching element) can be improved.

  As shown in FIG. 1, the cascode-connected junction FET Q1 is a normally-on junction FET Q1, and the gate electrode Gj of the junction FET Q1 is electrically connected to the source S of the switching element. As a result, the voltage between the gate electrode Gj and the source S of the junction FET Q1 is not forward-biased even during switching (on time). Therefore, in the cascode connection, since a large current due to the parasitic diode of the junction FET Q1 does not flow, it is possible to suppress the destruction of the switching element due to excessive heat generation. That is, in the normally-off type junction FET, a positive voltage is applied to the gate electrode Gj with respect to the source S at the time of switching (on time). At this time, since the source region of the junction FET Q1 is formed of an n-type semiconductor region and the gate electrode Gj is formed of a p-type semiconductor region, applying a positive voltage to the gate electrode Gj with respect to the source S means that This means that a forward voltage (forward bias) is applied between the source region and the gate electrode Gj. For this reason, in a normally-off junction FET, if the forward voltage is excessively increased, a parasitic diode composed of the source region and the gate electrode Gj is turned on. As a result, a large current may flow between the gate electrode Gj and the source region, and the junction FET may excessively generate heat and may be destroyed. On the other hand, the switching element connected in cascode uses a normally-on junction FET Q1, and the gate electrode Gj is electrically connected to the source S of the switching element. For this reason, the voltage between the gate electrode Gj and the source S of the junction FET Q1 is not forward-biased even at the time of switching (on time). Therefore, in the cascode connection, since a large current due to the parasitic diode of the junction FET Q1 does not flow, it is possible to suppress the destruction of the switching element due to excessive heat generation.

  The cascode-connected switching element as described above has the above-described various advantages, but as a result of investigation by the present inventor, the following problems have been newly found. That is, in order to realize the cascode connection, it is necessary to connect the semiconductor chip on which the junction FET Q1 is formed and the semiconductor chip on which the low breakdown voltage MOSFET Q2 is formed with a bonding wire. For this reason, for example, the drain Dm of the low-voltage MOSFET Q2 and the source Sj of the junction FET Q1 are connected via a bonding wire. In this case, parasitic inductance due to the bonding wire is added to the source Sj of the junction FET Q1. When such a parasitic inductance is added, a large surge voltage is generated at the time of switching, whereby a voltage higher than the breakdown voltage is applied to the low breakdown voltage MOSFET Q2. As a result, the present inventor newly found out that the low breakdown voltage MOSFET Q2 operates in the avalanche mode, and a large current that cannot be controlled by the gate electrode Gm may flow into the low breakdown voltage MOSFET Q2 to cause element destruction. . This mechanism will be described in detail below.

<Mechanism of issue>
FIG. 2A is a circuit diagram showing an inverter using a cascode-connected junction FET and a MOSFET as switching elements. The inverter shown in FIG. 2A has an upper arm and a lower arm connected in series to the power supply VCC. The upper arm is composed of a switching element connected between the drain D1 and the source S1. The switching element constituting the upper arm is constituted by a cascode-connected junction FET Q1a and MOSFET Q2a. Specifically, the drain Dj1 of the junction FET Q1a is connected to the drain D1 of the switching element, and the source Sj1 of the junction FET Q1a is connected to the drain Dm1 of the MOSFET Q2a. The source Sm1 of the MOSFET Q2a is connected to the source S1 of the switching element. The gate electrode Gj1 of the junction FET Q1a is connected to the source S1 of the switching element, and a gate drive circuit (G / D) is connected between the gate electrode Gm1 of the MOSFET Q2a and the source S1 of the switching element.

  Here, a parasitic inductance Lse1 based on a bonding wire exists between the source Sj1 of the junction FET Q1a and the drain Dm1 of the MOSFET Q2a, and bonding between the gate electrode Gj1 of the junction FET Q1a and the source S1 of the switching element. There is a parasitic inductance Lgi1 based on the wire. In FIG. 2A, a voltage between the source S1 of the switching element and the drain D1 of the switching element is defined as a voltage Vdsu, and a voltage between the source S1 of the switching element and the drain Dm1 of the MOSFET Q2a is a voltage. It is defined as Vdsmu.

  Similarly, as shown in FIG. 2A, the lower arm is composed of a switching element connected between the drain D2 and the source S2. The switching element constituting the lower arm is composed of a cascode-connected junction FET Q1b and MOSFET Q2b. Specifically, the drain Dj2 of the junction FET Q1b is connected to the drain D2 of the switching element, and the source Sj2 of the junction FET Q1b is connected to the drain Dm2 of the MOSFET Q2b. The source Sm2 of the MOSFET Q2b is connected to the source S2 of the switching element. The gate electrode Gj2 of the junction FET Q1b is connected to the source S2 of the switching element, and a gate drive circuit (G / D) is connected between the gate electrode Gm2 of the MOSFET Q2b and the source S2 of the switching element. Further, a load inductance LL is connected between the source S2 of the switching element and the drain D2 of the switching element.

  Here, a parasitic inductance Lse2 based on the bonding wire exists between the source Sj2 of the junction FET Q1b and the drain Dm2 of the MOSFET Q2b, and bonding between the gate electrode Gj2 of the junction FET Q1b and the source S2 of the switching element. There is a parasitic inductance Lgi2 based on the wire. In FIG. 2A, the voltage between the source S2 of the switching element and the drain D2 of the switching element is defined as a voltage Vak, and the voltage between the source S2 of the switching element and the drain Dm2 of the MOSFET Q2b is defined as a voltage. It is defined as Vdsmd.

  An inverter using a cascode-connected switching element is configured as described above, and a mechanism in which a problem occurs will be described below while explaining the operation of the inverter. First, the case where the switching element which comprises an upper arm is turned on is demonstrated. That is, a case will be described in which the power supply voltage is applied to the load (including the load inductance) by turning on the switching element constituting the upper arm and turning off the switching element constituting the lower arm.

  FIG. 2B shows a waveform when the switching element constituting the upper arm is turned on. Specifically, when the switching element constituting the upper arm is turned on, the junction FET Q1a and the MOSFET Q2a constituting the upper arm are turned on, so that the load inductance is passed from the drain Dj1 of the junction FET Q1a via the drain Dm1 and the source Sm1 of the MOSFET Q2a. A return current flows through a path that passes through LL and returns to the power supply VCC. At this time, as shown in FIG. 2B, the voltage Vdsmu changes from a predetermined voltage to about 0 V, while the voltage Vak is about 0 V to a power supply voltage when the upper arm switching element is turned off. To rise. As a result, the voltage Vdsmd, which is the drain voltage of the lower arm MOSFET Q2b, rises to a voltage that cuts off the lower arm junction FET Q1b, and maintains a certain voltage after the lower arm junction FET Q1b is turned off. The change in the voltage Vdsmd is a change in an ideal state where the parasitic inductance can be ignored, and is indicated by a broken line in FIG. However, when the parasitic inductance Lse2 and the parasitic inductance Lgi2 increase, the voltage Vdsmd rapidly increases greatly when the upper arm switching element is turned on, as shown by the solid line in FIG.

  On the other hand, FIG.2 (c) has shown the waveform at the time of turning off the switching element which comprises an upper arm. Specifically, when the switching element constituting the upper arm is turned off, as shown in FIG. 2C, the voltage Vdsmd changes from a predetermined voltage to about 0 V, while the voltage Vdsu turns on the switching element of the upper arm. The voltage rises from 0V during the operation to a voltage of about the power supply voltage. As a result, the voltage Vdsmu, which is the drain voltage of the upper arm MOSFET Q2a, rises to a voltage that cuts off the upper arm junction FET Q1a and maintains a certain voltage after the upper arm junction FET Q1a is turned off. This change in the voltage Vdsmu is a change in an ideal state in which the parasitic inductance can be ignored, and is indicated by a broken line in FIG. However, when the parasitic inductance Lse1 and the parasitic inductance Lgi1 increase, the voltage Vdsmu rapidly increases greatly when the upper arm switching element is turned off, as shown by the solid line in FIG.

  Thus, when the upper arm switching element is turned on, a phenomenon occurs in which the voltage Vdsmd, which is the drain voltage of the lower arm MOSFET Q2b to be turned off, rapidly increases, and when the upper arm switching element is turned off, It can be seen that a phenomenon occurs in which the voltage Vdsmu, which is the drain voltage of the upper-arm MOSFET Q2a that is turned off, rapidly increases. Since the mechanism in which these phenomena occur is the same, in the following, focusing on the case where the upper arm switching element is turned on, a phenomenon occurs in which the voltage Vdsmd, which is the drain voltage of the lower arm MOSFET Q2b to be turned off, suddenly increases. The mechanism will be described. The following three mechanisms can be considered as a mechanism for causing this phenomenon.

  The first mechanism is caused by the parasitic inductance Lse2 existing between the source Sj2 of the junction FET Q1b constituting the lower arm and the drain Dm2 of the MOSFET Q2b constituting the lower arm. Specifically, when the upper arm switching element is turned on, the lower arm MOSFET Q2b is turned off. At this time, the voltage Vak starts to increase from about 0 V, and the voltage Vdsmd, which is the drain voltage of the lower arm MOSFET Q2b, also starts to increase with the increase of the voltage Vak. However, in the initial stage in which the voltage Vdsmd increases, the voltage Vdsmd is not greater than a predetermined value than the gate voltage applied to the gate electrode Gj2 of the junction FET Q1b, so the junction FET Q1b is not cut off and the junction FET Q1b. Current flows from the drain Dj2 to the source Sj2. As a result, a current flows into the drain Dm2 of the MOSFET Q2b and charges are accumulated. As a result, the voltage Vdsmd which is the drain voltage of the MOSFET Q2b increases. When the voltage Vdsmd continues to increase and becomes higher than the gate voltage of the junction FET Q1b by a predetermined value or more, the junction FET Q1b is cut off and no more current flows. That is, in the initial stage where the voltage Vdsmd increases, a current flows between the drain Dj2 and the source Sj2 of the junction FET Q1b and charges are accumulated in the drain Dm2 of the MOSFET Q2b, so the voltage Vdsmd increases. After that, as the voltage Vdsmd increases, the voltage Vdsmd approaches a state of a predetermined value or higher than the gate voltage of the junction FET Q1b, so that the current flowing through the drain Dj2 and the source Sj2 of the junction FET Q1b gradually decreases. Go. Finally, the voltage Vdsmd is greater than the gate voltage of the junction FET Q1b by a predetermined value or more, so that the junction FET Q1b is cut off. After the junction FET Q1b is cut off, there is no charge flowing into the drain Dm2 of the MOSFET Q2b, so the voltage Vdsmd is substantially constant.

  As described above, when the upper arm switching element is turned on, the lower arm MOSFET Q2b is turned off. At this stage, the lower arm junction FET Q1b is not immediately cut off, and a current flows from the drain Dj2 to the source Sj2 of the junction FET Q1b. Flows. The current flowing into the source Sj2 of the junction FET Q1b flows into the drain Dm2 of the MOSFET Q2b via the parasitic inductance Lse2. At this time, the point to be noted is that the current flowing from the drain Dj2 to the source Sj2 of the junction FET Q1b of the lower arm decreases. This means that the current flowing through the parasitic inductance Lse2 also decreases with time. As a result, in the parasitic inductance Lse2, an electromotive force that cancels the decrease in current is generated. That is, the parasitic inductance Lse2 functions to increase the current flowing from the drain Dj2 to the source Sj2 of the junction FET Q1b. For this reason, when the parasitic inductance Lse2 increases, a large current flows transiently from the drain Dj2 of the junction FET Q1b to the source Sj2. As a result, the charge flowing into the drain Dm2 of the MOSFET Q2b increases rapidly, and thereby the voltage Vdsmd increases rapidly. This is the first mechanism.

  Subsequently, the second mechanism is caused by the parasitic inductance Lgi2 existing between the gate electrode Gj2 of the junction FET Q1b constituting the lower arm and the source S2 of the lower arm. Specifically, when the upper arm switching element is turned on, the lower arm MOSFET Q2b is turned off. At this time, the voltage Vak starts to increase from about 0 V. For example, as shown in FIG. 2B, the voltage Vak oscillates to a range exceeding the power supply voltage at the initial stage when the switching element of the upper arm is turned on. This is based on the back electromotive force caused by the load inductance LL included in the load connected to the inverter. Therefore, the voltage Vak varies at an initial stage when the upper arm is turned on. Here, focusing on the junction FET Q1b, a parasitic capacitance is formed between the drain Dj2 and the gate electrode Gj2 of the junction FET Q1b. When the voltage Vak changes, the voltage applied to the parasitic capacitance also changes. And since the electrostatic capacitance value of this parasitic capacitance becomes a comparatively large value, the charging / discharging current which generate | occur | produces with the voltage fluctuation applied to parasitic capacitance also becomes large. This charge / discharge current flows between the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm. At this time, the charge / discharge current is a current that changes over time. For this reason, for example, if the parasitic inductance Lgi2 exists between the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm, the charge / discharge current that changes with time flows through the parasitic inductance Lgi2, and thus the magnitude of the parasitic inductance Lgi2 A resistance component proportional to the product of the time differentiation of the charge / discharge current is generated between the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm. As a result, a mode occurs in which the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm are not at the same potential, and the gate electrode Gj2 of the junction FET Q1b rises in the positive voltage direction with respect to the source S2 of the lower arm. In this case, since the gate electrode Gj2 of the junction FET Q1b has a positive voltage, the depletion layer extending from the gate electrode Gj2 of the junction FET Q1b is suppressed, and the width of the channel region is increased. For this reason, the current flowing from the drain Dj2 to the source Sj2 of the junction FET Q1b transiently increases. As a result, the charge flowing into the drain Dm2 of the MOSFET Q2b increases rapidly, and thereby the voltage Vdsmd increases rapidly. This is the second mechanism. Furthermore, according to the second mechanism, since a positive voltage is applied to the gate electrode Gj2 of the junction FET Q1b, in order to cut off the junction FET Q1b, it is larger than when 0V is applied to the gate electrode Gj2. A voltage must be applied to the source Sj2 of the junction FET Q1b. Also from this viewpoint, the voltage Vdsmd that increases until the junction FET Q1b is cut off increases.

  Further, the third mechanism is caused by a parasitic resistance existing between the gate electrode Gj2 of the junction FET Q1b constituting the lower arm and the source S2 of the lower arm. As described in the second mechanism, the charge / discharge current flows between the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm. Therefore, if a parasitic resistance exists between the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm, a charge / discharge current flows through the parasitic resistance, and a voltage drop occurs. As a result, a mode occurs in which the gate electrode Gj2 of the junction FET Q1b and the source S2 of the lower arm are not at the same potential, and the gate electrode Gj2 of the junction FET Q1b rises in the positive voltage direction with respect to the source S2 of the lower arm. As a result, in the third mechanism as well as the second mechanism, the gate electrode Gj2 of the junction FET Q1b becomes a positive voltage, so that the depletion layer extending from the gate electrode Gj2 of the junction FET Q1b is suppressed, and the width of the channel region is reduced. growing. Therefore, the current flowing from the drain Dj2 to the source Sj2 of the junction FET Q1b increases transiently. As a result, the charge flowing into the drain Dm2 of the MOSFET Q2b increases rapidly, and thereby the voltage Vdsmd increases rapidly.

  As described above, it can be seen that the voltage Vdsmd rapidly increases by the first mechanism to the third mechanism related to the parasitic inductance Lse2, the parasitic inductance Lgi2, and the parasitic resistance. As described above, when the parasitic inductance Lse2, the parasitic inductance Lgi2, and the parasitic resistance increase, the voltage Vdsmd, which is the drain voltage of the lower arm MOSFET Q2b, rises to a voltage higher than or equal to the withstand voltage of the MOSFET Q2b. There is a risk that the lower arm MOSFET Q2b will be destroyed eventually.

  Specifically, when a voltage higher than the withstand voltage is applied to MOSFET Q2b, a region where the electric field concentrates locally occurs in MOSFET Q2b, and a large number of hole electron pairs are generated in this region due to impact ionization. Due to the large number of hole electron pairs, the parasitic npn bipolar transistor formed by the source region (n-type semiconductor region), the channel formation region (p-type semiconductor region) and the drift region (n-type semiconductor region) is turned on. In the cell (MOSFET Q2b) in which the parasitic npn bipolar transistor is turned on, a large current that cannot be controlled by the gate electrode Gm2 of the MOSFET Q2b flows and generates heat. At this time, since the electrical resistance of the semiconductor region decreases due to the temperature rise due to heat generation, positive feedback occurs in which a larger current flows. As a result, a large current flows locally and the MOSFET Q2b is destroyed. This phenomenon is avalanche destruction. When such avalanche breakdown occurs, the reliability of the semiconductor device is reduced.

  Therefore, in the first embodiment, in order to suppress the voltage application to the MOSFET that causes the avalanche breakdown to the voltage higher than the withstand voltage, a device for reducing the parasitic inductance and the parasitic resistance is taken. Below, the technical idea in this Embodiment 1 which gave this device is demonstrated. The first embodiment is characterized in that the mounting configuration of the semiconductor device is devised, and the mounting configuration of the semiconductor device including this characteristic point will be described.

<Mounting Configuration of Semiconductor Device in First Embodiment>
FIG. 3 is a diagram showing a mounting configuration of the package (semiconductor device) PKG1 in the first embodiment. As shown in FIG. 3, the package PKG1 in the first embodiment has two chip mounting portions PLT1 and PLT2 that are electrically insulated from each other. In FIG. 3, the metal plate arranged on the right side constitutes the chip mounting part PLT1, and the metal plate arranged on the left side constitutes the chip mounting part PLT2. The chip mounting part PLT1 is integrally formed so as to be connected to the drain lead DL, and the chip mounting part PLT1 and the drain lead DL are electrically connected. The source lead SL and the gate lead GL are arranged so as to sandwich the drain lead DL. Specifically, as shown in FIG. 3, the source lead SL is disposed on the right side of the drain lead DL, and the gate lead GL is disposed on the left side of the drain lead DL. The drain lead DL, the source lead SL, and the gate lead GL are electrically insulated from each other. A source lead post portion SPST made of a wide region is formed at the tip portion of the source lead SL, and a gate lead post portion GPST made of a wide region is formed at the tip portion of the gate lead GL.

  Next, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive made of, for example, silver paste or solder. For example, a junction FET made of SiC is formed on the semiconductor chip CHP1. The back surface of the semiconductor chip CHP1 serves as a drain electrode, and the source pad SPj and the gate pad GPj are formed on the front surface (main surface) of the semiconductor chip CHP1. In other words, the semiconductor chip CHP1 is formed with a junction FET that constitutes a part of a cascode-connected switching element, and a drain electrode electrically connected to the drain of the junction FET is formed on the back surface of the semiconductor chip CHP1. A source pad SPj formed and electrically connected to the source of the junction FET and a gate pad GPj electrically connected to the gate electrode of the junction FET are formed on the surface of the semiconductor chip CHP1.

Subsequently, the semiconductor chip CHP2 is mounted on the chip mounting portion PLT2 via a conductive adhesive made of, for example, silver paste or solder. For example, a MOSFET made of Si is formed on the semiconductor chip CHP2. At this time, the back surface of the semiconductor chip CHP2 serves as a drain electrode, and the source pad SPm and the gate pad GPm are formed on the front surface (main surface) of the semiconductor chip CHP2 . In other words, the semiconductor chip CHP2 is formed with a MOSFET that constitutes a part of the switching element using the cascode connection method, and a drain electrode that is electrically connected to the drain of the MOSFET is formed on the back surface of the semiconductor chip CHP2. A source pad SPm electrically connected to the source of the MOSFET and a gate pad GPm electrically connected to the gate electrode of the MOSFET are formed on the surface of the semiconductor chip CHP2.

  A cascode-connected switching element can be configured by connecting the semiconductor chip CHP1 mounted on the chip mounting portion PLT1 and the semiconductor chip CHP2 mounted on the chip mounting portion PLT2 with bonding wires. . Specifically, as shown in FIG. 3, the gate pad GPj formed on the surface of the semiconductor chip CHP1 and the source lead post part SPST formed at the tip of the source lead SL are electrically connected by a wire Wgj. It is connected. Further, the source pad SPj formed on the surface of the semiconductor chip CHP1 and the chip mounting part PLT2 are electrically connected by a wire Wds. Further, the source pad SPm formed on the surface of the semiconductor chip CHP2 and the source lead post portion SPST formed at the tip of the source lead SL are electrically connected by a wire Wsm. Further, the gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead post part GPST formed at the tip of the gate lead GL are electrically connected by a wire Wgm. Here, the region where the wire Wgj and the wire Wsm of the source lead post part SPST are connected and the region where the wire Wgm of the gate lead post part GPST is connected are the upper surface of the chip mounting part PLT1 and the chip mounting part PLT2. It is comprised so that it may be located in a position higher than an upper surface.

  Since the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive, the drain electrode formed on the back surface of the semiconductor chip CHP1 is electrically connected to the chip mounting portion PLT1. Has been. Further, since the semiconductor chip CHP2 is mounted on the chip mounting portion PLT2 via a conductive adhesive, the drain electrode formed on the back surface of the semiconductor chip CHP2 is electrically connected to the chip mounting portion PLT2. Will be.

  In the package PKG1 configured in this way, the semiconductor chip CHP1, the semiconductor chip CHP2, a part of the chip mounting part PLT1, a part of the chip mounting part PLT2, a part of the drain lead DL, a part of the source lead SL, A part of the gate lead GL and the wires Wgj, Wds, Wgm, Wsm are at least sealed with a sealing body. Therefore, a part of the sealing body is arranged between the chip mounting part PLT1 and the chip mounting part PLT2, and thereby the chip mounting part PLT1 and the chip mounting part PLT2 are electrically connected by the sealing body. Will be electrically insulated. Note that the lower surface of the chip mounting portion PLT1 and the lower surface of the chip mounting portion PLT2 may be configured to be exposed from the sealing body. In this case, the heat generated in the semiconductor chip CHP1 and the semiconductor chip CHP2 can be efficiently dissipated from the lower surface of the chip mounting part PLT1 and the lower surface of the chip mounting part PLT2.

  The sealing body has, for example, a rectangular parallelepiped shape, and has a first side surface and a second side surface facing the first side surface. In this case, for example, a part of the drain lead DL, a part of the source lead SL, and a part of the gate lead GL protrude from the first side surface of the sealing body. A part of the protruding drain lead DL, a part of the source lead SL, and a part of the gate lead GL function as external connection terminals.

  Here, in the cascode-connected switching element, since two semiconductor chips, the semiconductor chip CHP1 and the semiconductor chip CHP2, are mounted, it is not possible to divert an existing general-purpose package having only one chip mounting portion in the package as it is. Can not. For example, considering the use with a large rated current of several A or more, the junction FET formed on the semiconductor chip CHP1 and the MOSFET formed on the semiconductor chip CHP2 have a drain electrode on the back surface of the so-called semiconductor chip. Vertical structure is adopted. In this case, in the cascode connection type switching element, the drain electrode formed on the back surface of the semiconductor chip CHP1 cannot be electrically connected to the drain electrode formed on the back surface of the semiconductor chip CHP2. For this reason, in the existing general-purpose package having only one chip mounting portion in the package, when the semiconductor chip CHP1 and the semiconductor chip CHP2 are arranged in this one chip mounting portion, they are formed on the back surface of the semiconductor chip CHP1. The drain electrode formed on the back surface of the semiconductor chip CHP2 is electrically connected to the cascode connection method.

  Therefore, in the first embodiment, as shown in FIG. 3, two chip mounting portions PLT1 that are electrically insulated from each other inside the sealing body on the assumption that the outer shape is equivalent to that of the general-purpose package. The package PKG1 is configured so as to provide the chip mounting portion PLT2. The package PKG1 is configured such that the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1, and the semiconductor chip CHP2 is mounted on the chip mounting portion PLT2. That is, two chip mounting portions PLT1 and PLT2 that are electrically insulated are provided in the package PKG1, the semiconductor chip CHP1 and the semiconductor chip CHP2 are arranged in a plane, and the semiconductor chip CHP1 arranged in a plane is arranged. The cascode connection is realized by connecting the semiconductor chip CHP2 to the semiconductor chip CHP2.

  Therefore, according to the package PKG1 in the first embodiment, for example, an existing general-purpose package in which a switching element used for a power supply circuit or the like is mounted is replaced with a package in the first embodiment having the same outer dimensions. It can be replaced with PKG1. In particular, according to the package PKG1 in the first embodiment, since the arrangement of the drain lead DL, the source lead SL, and the gate lead GL is the same as that of the general-purpose package, the general-purpose package is changed to the package PKG1 in the first embodiment. It is possible to replace them, and it is not necessary to change the design of other driving circuits and printed circuit board wiring. Therefore, according to the first embodiment, it is easy to change from a switching element using a general-purpose package to a high-performance cascode connection switching element using the package PKG1 of the first embodiment. This has the advantage that a high-performance power supply system can be provided without significant design changes.

  Below, the feature point of package PKG1 in this Embodiment 1 is demonstrated. First, as shown in FIG. 3, the first feature point of the first embodiment is that the gate pad GPj provided on the surface of the semiconductor chip CHP1 on which the junction FET is formed and the source lead SL are as close as possible. The point is to place. Specifically, in the first embodiment, the chip mounting part PLT1 on which the semiconductor chip CHP1 is mounted is disposed on the same side as the side on which the source lead SL is disposed with respect to the drain lead DL. Thereby, the chip mounting part PLT1 can be brought close to the source lead SL. This means that the semiconductor chip CHP1 mounted on the chip mounting portion PLT1 can be arranged so as to be close to the source lead SL. In the first embodiment, the semiconductor chip CHP1 mounted on the chip mounting unit PLT1 is not arranged at the center of the chip mounting unit PLT1, but approaches the side closest to the source lead SL of the chip mounting unit PLT1. Thus, the semiconductor chip CHP1 is arranged. Thereby, the semiconductor chip CHP1 can be arranged so as to be closest to the source lead SL. Furthermore, in the first embodiment, the semiconductor chip CHP1 is arranged as close to the source lead SL as possible, and the gate pad GPj formed on the surface of the semiconductor chip CHP1 is arranged so as to be close to the source lead SL. Yes. As described above, in the first embodiment, first, the chip mounting part PLT1 on which the semiconductor chip CHP1 in which the junction FET is formed is mounted is arranged at a position close to the source lead SL, and further, the chip mounting part PLT1 in the chip mounting part PLT1 The semiconductor chip CHP1 is mounted in a region near the source lead SL in the internal region. In addition, in the first embodiment, the gate pad GPj is arranged so that the gate pad GPj formed on the surface of the semiconductor chip CHP1 approaches the source lead SL. As a result, the gate pad GPj formed on the surface of the semiconductor chip CHP1 and the source lead SL come close to each other. In other words, in the first embodiment, the gate pad GPj formed on the surface of the semiconductor chip CHP1 is arranged so as to be closer to the source lead SL than the other leads (drain lead DL and gate lead GL). Will be. As a result, according to the first embodiment, since the distance between the gate pad GPj and the source lead SL can be shortened, the length of the wire Wgj connecting the gate pad GPj and the source lead SL is shortened. can do. Particularly, in the first embodiment, since the wire Wgj is connected by the wide source lead post portion SPST existing at the tip portion close to the gate pad GPj in the source lead SL, the wire Wgj The length can be shortened. The fact that the length of the wire Wgj can be shortened means that the parasitic inductance (Lgi1 and Lgi2 in FIG. 2) existing in the wire Wgj can be reduced. That is, according to the first embodiment, it is possible to sufficiently reduce the parasitic inductance existing in the wire Wgj. From this, it is possible to suppress the voltage application to or higher than the withstand voltage to the MOSFET by the second mechanism described above, and thereby it is possible to effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, according to the first embodiment, the reliability of the semiconductor device can be improved.

  Next, the second feature point in the first embodiment will be described. As shown in FIG. 3, the second feature point in the first embodiment is that the gate pad GPm provided on the surface of the semiconductor chip CHP2 on which the MOSFET is formed and the gate lead GL are arranged as close as possible. It is in. Specifically, in the first embodiment, the chip mounting part PLT2 for mounting the semiconductor chip CHP2 is disposed on the same side as the side on which the gate lead GL is disposed with respect to the drain lead DL. Thereby, the chip mounting part PLT2 can be brought close to the gate lead GL. This means that the semiconductor chip CHP2 mounted on the chip mounting portion PLT2 can be arranged so as to be close to the gate lead GL. In the first embodiment, the semiconductor chip CHP2 mounted on the chip mounting portion PLT2 is not disposed at the center of the chip mounting portion PLT2, but approaches the side closest to the gate lead GL of the chip mounting portion PLT2. Thus, the semiconductor chip CHP2 is arranged. Thereby, the semiconductor chip CHP2 can be arranged so as to be closest to the gate lead GL. Furthermore, in the first embodiment, the semiconductor chip CHP2 is arranged as close to the gate lead GL as possible, and the gate pad GPm formed on the surface of the semiconductor chip CHP2 is arranged so as to be close to the gate lead GL. Yes. As described above, in the first embodiment, first, the chip mounting portion PLT2 on which the semiconductor chip CHP2 on which the MOSFET is formed is mounted is disposed at a position close to the gate lead GL, and further, the inside of the chip mounting portion PLT2 Among the regions, the semiconductor chip CHP2 is mounted in a region close to the gate lead GL. Moreover, in the first embodiment, the gate pad GPm is arranged so that the gate pad GPm formed on the surface of the semiconductor chip CHP2 approaches the gate lead GL. As a result, the gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead GL approach each other. In other words, in the first embodiment, the gate pad GPm formed on the surface of the semiconductor chip CHP2 is arranged so as to be closer to the gate lead GL than the other leads (drain lead DL and source lead SL). Will be. As a result, according to the first embodiment, since the distance between the gate pad GPm and the gate lead GL can be shortened, the length of the wire Wgm connecting the gate pad GPm and the gate lead GL is shortened. can do. In particular, in the first embodiment, among the gate leads GL, the wire Wgm is connected by the wide gate lead post portion GPST present at the tip portion close to the gate pad GPm. The length can be shortened. Thereby, according to this Embodiment 1, the parasitic inductance of the wire Wgm can be reduced. The reduction of the parasitic inductance of the wire Wgm contributes to the improvement of the electrical characteristics of the cascode-connected switching elements, but is not directly related to the suppression of voltage application beyond the withstand voltage to the MOSFET. According to the configuration of the second feature point in the first embodiment, it is possible to suppress the voltage application to the MOSFET more than the withstand voltage, not directly but indirectly.

  This point will be described below. As shown in FIG. 3, the second feature point in the first embodiment is that the semiconductor chip CHP2 on which the MOSFET is formed is arranged as close to the gate lead GL as possible. This means that, as shown in FIG. 3, the semiconductor chip CHP2 is arranged to be biased toward the front side of the chip mounting part PLT2, in other words, the semiconductor chip CHP2 is mounted on the back side of the chip mounting part PLT2. It means that there can be a large space that is not. As described above, the first embodiment has an indirect feature in that a large space in which the semiconductor chip CHP2 is not mounted can be secured in the chip mounting portion PLT2. Specifically, due to this feature, as shown in FIG. 3, the source pad SPj formed on the surface of the semiconductor chip CHP1 mounted on the chip mounting portion PLT1 is electrically connected to the chip mounting portion PLT2. A sufficient wire connection area can be secured. As a result, as shown in FIG. 3, the source pad SPj and the chip mounting portion PLT2 can be connected by a plurality of wires Wds. Here, since the chip mounting portion PLT2 is electrically connected to the drain electrode formed on the back surface of the mounted semiconductor chip CHP2, according to the first embodiment, a plurality of wires Wds are provided. Thus, the drain of the MOSFET and the source of the junction FET are connected. This means that the parasitic inductance (Lse1, Lse2 in FIG. 2) of the wire Wds connecting the drain of the MOSFET and the source of the junction FET can be reduced. That is, according to the first embodiment, by using a plurality of wires Wds, the parasitic inductance between the drain of the MOSFET and the source of the junction FET can be sufficiently reduced.

  Furthermore, as shown in FIG. 3, it is desirable that the formation position of the source pad SPj formed on the surface of the semiconductor chip CHP1 is as close as possible to the chip mounting portion PLT2. This is because by arranging the source pad SPj in this way, the length of the wire Wds connecting the source pad SPj and the chip mounting portion PLT2 can be made as short as possible. This also reduces the parasitic inductance (Lse1, Lse2 in FIG. 2) of the wire Wds connecting the drain of the MOSFET and the source of the junction FET.

  From the above, according to the second feature point of the first embodiment, it is possible to suppress the voltage application over the withstand voltage to the MOSFET by the first mechanism described above, and thereby the cascode-connected MOSFET The avalanche destruction can be effectively suppressed. As a result, according to the first embodiment, the reliability of the semiconductor device can be improved.

  In the first embodiment, as shown in FIG. 3, the gate pad GPj is electrically connected to the source lead SL by the wire Wgj, and the gate pad GPm is connected to the gate lead GL by the wire Wgm. Electrically connected. At this time, it is desirable that the thickness (width) of the wire Wgj is larger than the thickness (width) of the wire Wgm. This is because when the parasitic resistance existing in the wire Wgj is increased, a voltage exceeding the withstand voltage is applied to the MOSFET by the third mechanism. Therefore, it is desirable to make the wire Wgj thicker than other wires from the viewpoint of reducing the parasitic resistance existing in the wire Wgj. As a result, the parasitic resistance between the gate electrode of the junction FET and the source of the switching element (also referred to as the source of the MOSFET) can be reduced. Therefore, a voltage exceeding the withstand voltage is applied to the MOSFET by the third mechanism described above. Thus, the avalanche breakdown of the cascode-connected MOSFET can be effectively suppressed. As a result, according to the first embodiment, the reliability of the semiconductor device can be improved.

  Next, the third feature point in the first embodiment will be described. As shown in FIG. 3, the third feature of the first embodiment is that the source pad SPm provided on the surface of the semiconductor chip CHP2 on which the MOSFET is formed and the source lead SL (source lead post portion SPST) are provided. The connection is made with a plurality of wires Wsm. Thereby, the parasitic resistance and the parasitic inductance between the source of the MOSFET and the source lead SL can be reduced. As a result, the source potential of the MOSFET can be prevented from fluctuating from the GND potential (reference potential) supplied from the source lead SL, and the source of the MOSFET can be reliably fixed to the GND potential. Furthermore, since the parasitic resistance between the source of the MOSFET and the source lead SL is reduced, the on-resistance of the cascode-connected switching element can also be reduced. As described above, according to the third feature point in the first embodiment, the electrical characteristics of the cascode-connected switching element formed in the package PKG1 can be improved.

  As described above, according to the package PKG1 (semiconductor device) in the first embodiment, by providing the first feature point and the second feature point described above, it is possible to suppress the voltage application to the MOSFET beyond the withstand voltage. Thus, the avalanche breakdown of the cascode-connected MOSFET can be effectively suppressed. As a result, the reliability of the semiconductor device can be improved. Furthermore, since the package PKG1 (semiconductor device) according to the first embodiment is provided with the third feature point described above, the parasitic resistance and the parasitic inductance can be reduced, so that the electrical characteristics of the semiconductor device are improved. Can be achieved.

  Further, as a specific effect accompanying the package PKG1 of the first embodiment, the package PKG1 in the first embodiment includes a semiconductor chip CHP1 in which a junction FET is formed and a semiconductor chip CHP2 in which a MOSFET is formed in a plane. Since the arrangement configuration is adopted, the chip areas of the semiconductor chip CHP1 and the semiconductor chip CHP2 can be freely designed. This facilitates the design of low on-resistance and on-current density, and can realize switching devices with various specifications.

  Subsequently, an example of another mounting form of the switching element according to the first embodiment will be described. FIG. 4 is a diagram showing a mounting configuration of the package PKG2 in the first embodiment. The difference between the package PKG2 shown in FIG. 4 and the package PKG1 shown in FIG. 3 is that the formation positions of the source lead SL and the drain lead DL are different. Specifically, in the package PKG1 shown in FIG. 3, the gate lead GL is disposed on the leftmost side, the drain lead DL is disposed in the middle, and the source lead SL is disposed on the rightmost side. On the other hand, in the package PKG2 shown in FIG. 4, the gate lead GL is arranged on the leftmost side, the source lead SL is arranged in the middle, and the drain lead DL is arranged on the rightmost side. In this case, as shown in FIG. 4, as the arrangement position of the source lead SL is changed, the formation position of the gate pad GPj formed on the surface of the semiconductor chip CHP1 is also more source than the other leads. It has been changed to be closer to the lead SL. As a result, also in the package PKG2 shown in FIG. 4, the distance between the gate pad GPj and the source lead SL can be shortened. For this reason, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. That is, also in the package PKG2 shown in FIG. 4, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. From this, it is possible to suppress the voltage application to or higher than the withstand voltage to the MOSFET by the second mechanism described above, and thereby it is possible to effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, the reliability of the semiconductor device can be improved also in the package PKG2 shown in FIG.

  Furthermore, as a characteristic point peculiar to the package PKG2 shown in FIG. 4, the length of the wire Wsm that electrically connects the source pad SPm formed on the surface of the semiconductor chip CHP2 and the source lead SL is shown in FIG. This is a point that can be sufficiently shortened as compared with the package PKG1 shown in FIG. Therefore, according to the package PKG2 shown in FIG. 4, since the parasitic resistance and the parasitic inductance of the wire Wsm can be reduced, the electrical characteristics of the switching element according to the first embodiment can be improved. In particular, the effect of shortening the length of the wire Wsm becomes apparent in that the on-resistance of the switching element in the first embodiment is reduced.

<Modification 1>
Next, the mounting configuration of the package PKG3 in the first modification will be described. In the first modification, a configuration in which a semiconductor chip on which a junction FET is formed and a semiconductor chip on which a MOSFET is formed will be described.

FIG. 5 is a diagram showing a mounting configuration of the package PKG3 in the first modification. In FIG. 5 , the package PKG3 in the first modification has a chip mounting portion PLT made of, for example, a rectangular metal plate. The chip mounting portion PLT is integrally formed so as to be connected to the drain lead DL, and the chip mounting portion PLT and the drain lead DL are electrically connected. The source lead SL and the gate lead GL are arranged so as to sandwich the drain lead DL. Specifically, as shown in FIG. 5, the source lead SL is arranged on the right side of the drain lead DL, and the gate lead GL is arranged on the left side of the drain lead DL. The drain lead DL, the source lead SL, and the gate lead GL are electrically insulated from each other. A source lead post portion SPST made of a wide region is formed at the tip portion of the source lead SL, and a gate lead post portion GPST made of a wide region is formed at the tip portion of the gate lead GL.

  Next, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive made of, for example, silver paste or solder. For example, a junction FET made of SiC is formed on the semiconductor chip CHP1. The back surface of the semiconductor chip CHP1 serves as a drain electrode, and the source pad SPj and the gate pad GPj are formed on the front surface (main surface) of the semiconductor chip CHP1. In other words, the semiconductor chip CHP1 is formed with a junction FET that constitutes a part of a cascode-connected switching element, and a drain electrode electrically connected to the drain of the junction FET is formed on the back surface of the semiconductor chip CHP1. A source pad SPj formed and electrically connected to the source of the junction FET and a gate pad GPj electrically connected to the gate electrode of the junction FET are formed on the surface of the semiconductor chip CHP1.

  Subsequently, the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 via a conductive adhesive made of, for example, silver paste or solder. For example, a MOSFET made of Si is formed on the semiconductor chip CHP2. At this time, the back surface of the semiconductor chip CHP2 serves as a drain electrode, and the source pad SPm and the gate pad GPm are formed on the front surface (main surface) of the semiconductor chip CHP1. In other words, the semiconductor chip CHP2 is formed with a MOSFET that constitutes a part of the switching element using the cascode connection method, and a drain electrode that is electrically connected to the drain of the MOSFET is formed on the back surface of the semiconductor chip CHP2. A source pad SPm electrically connected to the source of the MOSFET and a gate pad GPm electrically connected to the gate electrode of the MOSFET are formed on the surface of the semiconductor chip CHP2.

  As described above, in the first modification, the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1, and in particular, the semiconductor chip CHP2 is mounted on the source pad SPj formed on the surface of the semiconductor chip CHP1. As a result, the drain electrode formed on the back surface of the semiconductor chip CHP2 and the source pad SPj formed on the surface of the semiconductor chip CHP1 are electrically connected. As a result, the source of the junction FET formed in the semiconductor chip CHP1 and the drain of the MOSFET formed in the semiconductor chip CHP2 are electrically connected. Therefore, the semiconductor chip CHP2 needs to be formed so as to be included in the source pad SPj formed on the surface of the semiconductor chip CHP1 in plan view. That is, in the first modification, the size of the semiconductor chip CHP2 needs to be smaller than the size of the semiconductor chip CHP1, and more specifically, the size of the semiconductor chip CHP2 is smaller than the size of the source pad SPj. It needs to be.

  Subsequently, as shown in FIG. 5, the gate pad GPj formed on the surface of the semiconductor chip CHP1 and the source lead post part SPST formed at the tip of the source lead SL are electrically connected by the wire Wgj. ing. The source pad SPm formed on the surface of the semiconductor chip CHP2 and the source lead post portion SPST formed at the tip of the source lead SL are electrically connected by a wire Wsm. Further, the gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead post part GPST formed at the tip of the gate lead GL are electrically connected by a wire Wgm. Here, the region where the wire Wgj and the wire Wsm of the source lead post part SPST are connected and the region where the wire Wgm of the gate lead post part GPST is connected are the upper surface of the chip mounting part PLT1 and the chip mounting part PLT2. It is comprised so that it may be located in a position higher than an upper surface.

  In the package PKG3 thus configured, the semiconductor chip CHP1, the semiconductor chip CHP2, a part of the chip mounting part PLT, a part of the drain lead DL, a part of the source lead SL, a part of the gate lead GL, and The wires Wgj, Wgm, and Wsm are at least sealed with a sealing body. Note that the lower surface of the chip mounting portion PLT may be configured to be exposed from the sealing body. In this case, the heat generated in the semiconductor chip CHP1 and the semiconductor chip CHP2 can be efficiently dissipated from the lower surface of the chip mounting portion PLT.

  The sealing body has, for example, a rectangular parallelepiped shape, and has a first side surface and a second side surface facing the first side surface. In this case, for example, a part of the drain lead DL, a part of the source lead SL, and a part of the gate lead GL protrude from the first side surface of the sealing body. A part of the protruding drain lead DL, a part of the source lead SL, and a part of the gate lead GL function as external connection terminals.

  The package PKG3 in the first modification example is configured as described above, and the characteristic points of the package PKG3 in the first modification example will be described below. First, as shown in FIG. 5, the characteristic point in the first modification is that the gate pad GPj provided on the surface of the semiconductor chip CHP1 on which the junction FET is formed and the source lead SL are arranged as close as possible. It is in. Specifically, in the first modification, the semiconductor chip CHP1 is arranged on the same side as the side on which the source lead SL is arranged with respect to the drain lead DL. That is, the semiconductor chip CHP1 is arranged to be shifted to the right side with respect to the center line aa ′ shown in FIG. Thereby, the semiconductor chip CHP1 can be brought close to the source lead SL. In the first modification, the semiconductor chip CHP1 is not disposed at the center of the chip mounting portion PLT, but the semiconductor chip CHP1 is disposed so as to approach the side closest to the source lead SL of the chip mounting portion PLT. . That is, the semiconductor chip CHP1 is arranged so as to be biased toward the near side (lower side) with respect to the center line bb ′ shown in FIG. Thereby, the semiconductor chip CHP1 can be arranged so as to be closest to the source lead SL. In other words, in the first modification, the gate pad GPj formed on the surface of the semiconductor chip CHP1 is disposed so as to be closer to the source lead SL than the other leads (drain lead DL and gate lead GL). It will be. As a result, according to the first modification, since the distance between the gate pad GPj and the source lead SL can be shortened, the length of the wire Wgj connecting the gate pad GPj and the source lead SL is shortened. be able to. In particular, in the first modification, the wire Wgj is connected to the source lead SL by the wide source lead post portion SPST existing at the tip portion close to the gate pad GPj, and therefore, the length of the wire Wgj is further increased. The length can be shortened. The fact that the length of the wire Wgj can be shortened means that the parasitic inductance (Lgi1 and Lgi2 in FIG. 2) existing in the wire Wgj can be reduced. That is, according to the first modification, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. From this, it is possible to suppress the voltage application to or higher than the withstand voltage to the MOSFET by the second mechanism described above, and thereby it is possible to effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, according to the first modification, the reliability of the semiconductor device can be improved.

  Here, from the viewpoint of shortening the length of the wire Wgj connecting the gate pad GPj and the source lead SL, the gate pad GPj may be biased on the side closest to the source lead SL of the semiconductor chip CHP1. Conceivable. However, in the first modification, as shown in FIG. 5, the gate pad GPj is arranged along the right side of the semiconductor chip CHP1 and symmetrical with respect to the center of the right side. This is due to the following reason. That is, the gate pad GPj is connected to each gate electrode of the plurality of junction FETs formed inside the semiconductor chip CHP1 by the gate wiring. From this, for example, by arranging the gate pad GPj so as to be symmetric with respect to the central portion on the right side, it is possible to suppress variations in the distance of the gate wiring connecting each gate electrode of the plurality of junction FETs and the gate pad GPj. It is. This means that the characteristics of a plurality of junction FETs formed in the semiconductor chip CHP1 can be used together. For this reason, in the first modification, the gate pad GPj is arranged so as to be symmetric with respect to the central portion on the right side of the semiconductor chip CHP1.

  In the first modification, as shown in FIG. 5, the gate pad GPj is electrically connected to the source lead SL by the wire Wgj, and the gate pad GPm is electrically connected to the gate lead GL by the wire Wgm. Connected. At this time, it is desirable that the thickness (width) of the wire Wgj is larger than the thickness (width) of the wire Wgm. This is because when the parasitic resistance existing in the wire Wgj is increased, a voltage exceeding the withstand voltage is applied to the MOSFET by the third mechanism. Therefore, it is desirable to make the wire Wgj thicker than other wires from the viewpoint of reducing the parasitic resistance existing in the wire Wgj. As a result, the parasitic resistance between the gate electrode of the junction FET and the source of the switching element (also referred to as the source of the MOSFET) can be reduced. Therefore, a voltage exceeding the withstand voltage is applied to the MOSFET by the third mechanism described above. Thus, the avalanche breakdown of the cascode-connected MOSFET can be effectively suppressed. As a result, according to the first modification, the reliability of the semiconductor device can be improved.

  Next, further feature points in the first modification will be described. As shown in FIG. 5, a further feature point of the first modification is that a plurality of source pads SPm and source leads SL (source lead post portions SPST) provided on the surface of the semiconductor chip CHP2 on which the MOSFET is formed are provided. It is in the point connected by the wire Wsm. Thereby, the parasitic resistance and the parasitic inductance between the source of the MOSFET and the source lead SL can be reduced. As a result, the source potential of the MOSFET can be prevented from fluctuating from the GND potential (reference potential) supplied from the source lead SL, and the source of the MOSFET can be reliably fixed to the GND potential. Furthermore, since the parasitic resistance between the source of the MOSFET and the source lead SL is reduced, the on-resistance of the cascode-connected switching element can also be reduced. As described above, according to the further feature point of the first modification, the electrical characteristics of the cascode-connected switching element formed in the package PKG3 can be improved.

  Subsequently, characteristic points unique to the first modification will be described. As shown in FIG. 5, the characteristic feature of the first modification is that a semiconductor chip CHP2 in which a MOSFET is formed is mounted on a semiconductor chip CHP1 in which a junction FET is formed. Thereby, the source pad SPj formed on the surface of the semiconductor chip CHP1 and the drain electrode formed on the back surface of the semiconductor chip CHP2 can be directly connected. That is, according to the first modification, the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire. This means that the parasitic inductance interposed between the source of the junction FET and the drain of the MOSFET can be almost completely eliminated. That is, the characteristic feature unique to the first modification is that the semiconductor chip CHP2 is directly mounted on the semiconductor chip CHP1, and this configuration is used to connect the source of the junction FET and the drain of the MOSFET. This eliminates the need for wires. When a wire is used, parasitic inductance existing in the wire becomes a problem. According to the first modification, the source of the junction FET and the drain of the MOSFET can be directly connected without using the wire. Therefore, the parasitic inductance (Lse1, Lse2 in FIG. 2) between the drain of the MOSFET and the source of the junction FET can be almost completely eliminated. From the above, according to the characteristic feature unique to the first modification, it is possible to suppress the voltage application over the withstand voltage to the MOSFET by the first mechanism described above, and thereby, the cascode-connected MOSFET Avalanche destruction can be effectively suppressed. As a result, according to the first modification, the reliability of the semiconductor device can be improved.

  According to the package PKG3 in the first modification, the semiconductor chip CHP1 and the semiconductor chip CHP2 are stacked on the chip mounting portion PLT. From this, the package PKG3 in the first modification may have a structure having one chip mounting portion PLT in the package, and therefore, an existing general-purpose package having only one chip mounting portion in the package is used as it is. be able to. That is, according to the package PKG3 in the first modification, since a so-called inexpensive general-purpose package can be used as it is, a high-performance switching element connected in cascode can be provided at low cost. In other words, according to the first modification, it is possible to reduce the cost of the package PKG3 in which the cascode-connected high-performance switching element is formed.

  Further, according to the first modification, since the semiconductor chip CHP1 in which the junction FET is formed and the semiconductor chip CHP2 in which the MOSFET is formed are stacked, there is also an advantage that the mounting area of the semiconductor chip can be reduced. In particular, in this case, as shown in FIG. 5, since a large space can be secured in the chip mounting portion PLT, heat generated in the semiconductor chip CHP1 and the semiconductor chip CHP2 can also be efficiently dissipated. Furthermore, according to the first modification, since the mounting area of the switching element can be reduced, conventionally, a free wheel diode (freewheeling diode) arranged on a printed circuit board outside the package is replaced with a switching element. There is also an advantage that it can be mounted in the same package. As a result, according to the first modification, it is possible to contribute to a reduction in the mounting area of the printed circuit board, thereby reducing the cost of the entire system represented by the power supply system.

  Next, an example of another mounting form of the switching element in the first modification will be described. FIG. 6 is a diagram showing a mounting configuration of the package PKG4 in the first modification. The difference between the package PKG4 shown in FIG. 6 and the package PKG3 shown in FIG. 5 is that the arrangement positions of the gate pads GPj formed on the surface of the semiconductor chip CHP1 are different. Specifically, in the package PKG3 shown in FIG. 5, the gate pad GPj is arranged along the right side of the semiconductor chip CHP1 so as to be symmetric with respect to the center of the right side. On the other hand, in the package PKG4 shown in FIG. 6, the gate pad GPj is biased and arranged on the side closest to the source lead SL of the semiconductor chip CHP1. In this case, the distance from the gate pad GPj to the source lead SL can be minimized. Therefore, according to the package PKG4 shown in FIG. 6, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be minimized, thereby minimizing the parasitic inductance existing in the wire Wgj. be able to. From this, it is possible to suppress the voltage application to or higher than the withstand voltage to the MOSFET by the second mechanism described above, and thereby it is possible to effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, the reliability of the semiconductor device can be improved also in the package PKG4 shown in FIG.

  An example of another mounting form of the switching element in Modification 1 will be described. FIG. 7 is a diagram showing a mounting configuration of the package PKG5 in the first modification. In the package PKG5 shown in FIG. 7, for example, a clip CLP made of a copper plate (metal plate) is used for the connection between the gate pad GPj and the source lead SL and the connection between the source pad SPm and the source lead SL. By using the copper plate in this way, the conductor resistance becomes smaller than that of the wire, so that the parasitic inductance can be reduced. That is, by using the clip CLP having a metal plate structure, the parasitic inductance existing between the gate pad GPj and the source lead SL and the parasitic inductance existing between the source pad SPm and the source lead SL are reduced. can do.

  In particular, according to the package PKG5 shown in FIG. 7, since the parasitic inductance existing between the gate pad GPj and the source lead SL can be reduced, the application of a voltage exceeding the withstand voltage to the MOSFET by the second mechanism described above is suppressed. This can effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, according to the package PKG5 shown in FIG. 7, the reliability of the semiconductor device can be improved. Further, according to the package PKG5 shown in FIG. 7, since the parasitic inductance existing between the source pad SPm and the source lead SL can be reduced, the electrical characteristics of the semiconductor device can be improved.

  FIG. 8 is a view showing a cross section of the package PKG5 in the first modification. As shown in FIG. 8, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a conductive adhesive (not shown) is mounted on the semiconductor chip CHP1. The semiconductor chip CHP2 is mounted. The semiconductor chip CHP1 (gate pad) and the source lead SL, and the semiconductor chip CHP2 (source pad) and the source lead SL are electrically connected by the clip CLP. In addition, the broken line part has shown the part covered with a sealing body.

  Next, an example of another mounting form of the switching element in the first modification will be described. FIG. 9 is a diagram showing a mounting configuration of the package PKG6 in the first modification. The difference between the package PKG6 shown in FIG. 9 and the package PKG3 shown in FIG. 5 is that the formation positions of the source lead SL and the drain lead DL are different. Specifically, in the package PKG3 shown in FIG. 5, the gate lead GL is disposed on the leftmost side, the drain lead DL is disposed in the middle, and the source lead SL is disposed on the rightmost side. On the other hand, in the package PKG6 shown in FIG. 9, the gate lead GL is disposed on the leftmost side, the source lead SL is disposed in the middle, and the drain lead DL is disposed on the rightmost side. In this case, as shown in FIG. 9, the mounting position of the semiconductor chip CHP1 mounted on the chip mounting portion PLT is changed in accordance with the change of the arrangement position of the source lead SL. That is, the arrangement position of the semiconductor chip CHP1 is changed so as to be closer to the source lead SL than the other leads. Specifically, the semiconductor chip CHP1 is arranged so as to be symmetric with respect to the center line aa ′ shown in FIG. Are arranged as follows. As a result, also in the package PKG6 shown in FIG. 9, the distance between the gate pad GPj and the source lead SL can be shortened. For this reason, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be shortened. That is, also in the package PKG6 shown in FIG. 9, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. From this, it is possible to suppress the voltage application to or higher than the withstand voltage to the MOSFET by the second mechanism described above, and thereby it is possible to effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, the reliability of the semiconductor device can be improved also in the package PKG6 shown in FIG.

  Further, as a characteristic feature peculiar to the package PKG6 shown in FIG. 9, the length of the wire Wgm that electrically connects the gate pad GPm formed on the surface of the semiconductor chip CHP2 and the gate lead GL is shown in FIG. Compared with the package PKG3 shown in FIG. For this reason, according to the package PKG6 shown in FIG. 9, since the parasitic resistance and the parasitic inductance of the wire Wgm can be reduced, the electrical characteristics of the switching element in the first modification can be improved.

  FIG. 10 is a diagram showing a cross section of the package PKG6 in the first modification. As shown in FIG. 10, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a conductive adhesive (not shown) is mounted on the semiconductor chip CHP1. The semiconductor chip CHP2 is mounted. The semiconductor chip CHP2 (source pad) and the source lead SL are electrically connected by a wire Wsm. In addition, the broken line part has shown the part covered with a sealing body.

  Next, an example of another mounting form of the switching element in Modification 1 will be described. FIG. 11 is a diagram showing a mounting configuration of the package PKG7 in the first modification. A difference between the package PKG7 shown in FIG. 11 and the package PKG6 shown in FIG. 9 is that the arrangement positions of the gate pads GPj formed on the surface of the semiconductor chip CHP1 are different. Specifically, in the package PKG6 shown in FIG. 9, the gate pad GPj is arranged along the right side of the semiconductor chip CHP1 so as to be symmetric with respect to the center of the right side. On the other hand, in the package PKG7 shown in FIG. 11, the gate pad GPj is arranged in a biased manner on the side closest to the source lead SL of the semiconductor chip CHP1. In this case, the distance from the gate pad GPj to the source lead SL can be minimized. Therefore, according to the package PKG7 shown in FIG. 11, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be minimized, thereby minimizing the parasitic inductance existing in the wire Wgj. be able to. From this, it is possible to suppress the voltage application to or higher than the withstand voltage to the MOSFET by the second mechanism described above, and thereby it is possible to effectively suppress the avalanche breakdown of the cascode-connected MOSFET. As a result, also in the package PKG7 shown in FIG. 11, the reliability of the semiconductor device can be improved.

  Next, the parasitic inductance existing in the switching element in the first embodiment and the switching element in the present modification will be described in comparison with the parasitic inductance existing in the switching element in the conventional technology. FIG. 12 is a diagram showing a circuit diagram of a switching element connected in cascode together with a parasitic inductance. Specifically, FIG. 12A is a circuit diagram showing the existence position of the parasitic inductance together with the switching element in the prior art, and FIG. 12B is the existence position of the parasitic inductance together with the switching element in the first embodiment. FIG. FIG. 12C is a circuit diagram showing the presence position of the parasitic inductance together with the switching element in the first modification.

  First, as can be seen from FIG. 12A, in the conventional cascode-connected switching element, the parasitic inductance Lse exists at the intermediate node Se connecting the source of the junction FET Q1 and the drain of the MOSFET Q2, and the source of the MOSFET Q2 And a parasitic inductance Ls exists between the source S of the switching element. Further, a parasitic inductance Lgi exists between the gate electrode of the junction FET and the source S of the switching element, and a parasitic inductance exists in the gate electrode Gm of the MOSFET.

  On the other hand, as shown in FIG. 12B, in the cascode-connected switching element of the first embodiment, the parasitic inductance Lse, the parasitic inductance Ls, and the parasitic inductance Lgi are shown in FIG. Compared to the conventional cascode-connected switching elements. For example, as shown in FIG. 3, in the first embodiment, the gate pad GPj is arranged by devising the arrangement position of the chip mounting portion PLT1, the arrangement position of the semiconductor chip CHP1, and the arrangement position of the gate pad GPj. This is based on the point that the wire Wgj for connecting the source lead SL is shortened and the point that the wire Wds for connecting the source pad SPj and the chip mounting portion PLT2 is composed of a plurality of wires. Thereby, according to this Embodiment 1, the voltage application more than the withstand voltage to MOSFET can be suppressed, and, thereby, the avalanche breakdown of cascode-connected MOSFET can be suppressed effectively. As a result, according to the first embodiment, the reliability of the semiconductor device can be improved.

  Further, as shown in FIG. 12C, in the cascode-connected switching element of the first modification, the parasitic inductance Ls and the parasitic inductance Lgi are changed as shown in FIG. As compared with the conventional cascode-connected switching element shown in FIG. Furthermore, in the first modification, the parasitic inductance Lse present at the intermediate node Se connecting the source of the junction FET Q1 and the drain of the MOSFET Q2 can be almost completely eliminated. This is because, for example, as shown in FIG. 5, the semiconductor chip CHP2 in which the MOSFET is formed is mounted on the semiconductor chip CHP1 in which the junction FET is formed. Thereby, the source pad SPj formed on the surface of the semiconductor chip CHP1 and the drain electrode formed on the back surface of the semiconductor chip CHP2 can be directly connected. That is, according to the first modification, the source of the junction FET and the drain of the MOSFET can be directly connected without using a wire. Therefore, according to the first modification, the parasitic inductance interposed between the source of the junction FET and the drain of the MOSFET can be almost completely eliminated. Thus, according to the first modification, it is possible to suppress the voltage application to the MOSFET that is higher than the withstand voltage, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. As a result, according to the first modification, the reliability of the semiconductor device can be improved.

<Modification 2>
Next, the mounting configuration of the package PKG8 in the second modification will be described. FIG. 13 is a diagram showing a mounting configuration of the package PKG8 in the second modification. The configuration of the package PKG8 shown in FIG. 13 is almost the same as the configuration of the package PKG1 shown in FIG. The difference is the outer shape of the package. Thus, the technical idea of the present invention can be applied not only to the package PKG1 shown in FIG. 3, but also to the package PKG8 shown in FIG. That is, there are various types of general-purpose packages for mounting and configuring the switching elements, and the technical idea of the present invention is various, for example, the package PKG1 shown in FIG. 3 and the package PKG8 shown in FIG. It can be realized by improving the general-purpose package. Specifically, in the package PKG8 shown in FIG. 13, for example, since the distance between the gate pad GPj and the source lead SL can be shortened, the length of the wire Wgj connecting the gate pad GPj and the source lead SL is long. The length can be shortened. Therefore, also in the package PKG8 shown in FIG. 13, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. From this, it is possible to suppress the application of a voltage exceeding the withstand voltage to the MOSFET, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. As a result, the reliability of the semiconductor device can be improved also in the package PKG8 shown in FIG.

  FIG. 14 is a view showing a cross section of the package PKG8 in the second modification. As shown in FIG. 14, the semiconductor chip CHP2 is mounted on the chip mounting portion PLT2 via the conductive adhesive PST. For example, the semiconductor chip CHP2 (gate pad) and the gate lead GL (gate lead post part GPST) are electrically connected by a wire Wgm. In addition, the broken line part has shown the part covered with a sealing body.

  Subsequently, an example of another mounting form of the switching element in Modification 2 will be described. FIG. 15 is a diagram illustrating a mounting configuration of the package PKG9 in the second modification. The configuration of the package PKG9 shown in FIG. 15 is almost the same as the configuration of the package PKG3 shown in FIG. The difference is the outer shape of the package. Thus, the technical idea of the present invention can be applied not only to the package PKG3 shown in FIG. 5, but also to the package PKG9 shown in FIG. That is, there are various types of general-purpose packages in which the switching elements are mounted and configured, and the technical idea of the present invention is various, for example, represented by the package PKG3 shown in FIG. 5 and the package PKG9 shown in FIG. It can be applied to general-purpose packages. Specifically, the package PKG9 shown in FIG. 15 also has the semiconductor chip CHP2 with the MOSFET mounted on the semiconductor chip CHP1 with the junction FET, so that it is formed on the source pad SPj and the back surface of the semiconductor chip CHP2. The drain electrode can be directly connected. From this, the package PKG9 shown in FIG. 15 can also directly connect the source of the junction FET and the drain of the MOSFET without using a wire, and therefore, between the drain of the MOSFET and the source of the junction FET. Parasitic inductance (Lse1, Lse2 in FIG. 2) can be almost completely eliminated. Therefore, even with the package PKG9 shown in FIG. 15, it is possible to suppress the voltage application to the MOSFET beyond the withstand voltage, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. As a result, according to the second modification, the reliability of the semiconductor device can be improved.

  FIG. 16 is a diagram showing a cross section of the package PKG9 in the second modification. As shown in FIG. 16, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT via the conductive adhesive PST, and on the semiconductor chip CHP1, via the conductive adhesive (not shown), A semiconductor chip CHP2 is mounted. For example, the semiconductor chip CHP2 (gate pad) and the gate lead GL (gate lead post part GPST) are electrically connected by a wire Wgm. In addition, the broken line part has shown the part covered with a sealing body.

<Modification 3>
Next, the mounting configuration of the package PKG10 in the third modification will be described. FIG. 17 is a diagram showing a mounting configuration of the package PKG10 in the third modification. The configuration of the package PKG10 illustrated in FIG. 17 is substantially the same as the configuration of the package PKG1 illustrated in FIG. The difference is the outer shape of the package. Thus, the technical idea of the present invention can be applied not only to the package PKG1 shown in FIG. 3, but also to the package PKG10 as shown in FIG. That is, there are various types of general-purpose packages in which the switching elements are mounted and configured, and the technical idea of the present invention is various, for example, represented by the package PKG1 shown in FIG. 3 and the package PKG10 shown in FIG. It can be realized by improving the general-purpose package. Specifically, also in the package PKG10 shown in FIG. 17, for example, the distance between the gate pad GPj and the source lead SL can be shortened, so that the length of the wire Wgj connecting the gate pad GPj and the source lead SL is long. The length can be shortened. From this, also in the package PKG10 shown in FIG. 17, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. From this, it is possible to suppress the application of a voltage exceeding the withstand voltage to the MOSFET, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. As a result, the reliability of the semiconductor device can be improved also in the package PKG10 shown in FIG.

  FIG. 18 is a diagram showing a cross section of the package PKG10 in the third modification. As shown in FIG. 18, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via the conductive adhesive PST. For example, the semiconductor chip CHP1 (gate pad GPj) and the source lead SL (source lead post part SPST) are electrically connected by a wire Wgj. In addition, the broken line part has shown the part covered with a sealing body.

  Next, an example of another mounting form of the switching element in Modification 3 will be described. FIG. 19 is a diagram showing a mounting configuration of the package PKG11 in the third modification. The configuration of the package PKG11 illustrated in FIG. 19 is substantially the same as the configuration of the package PKG3 illustrated in FIG. The difference is the outer shape of the package. Thus, the technical idea of the present invention can be applied not only to the package PKG3 shown in FIG. 5, but also to the package PKG11 as shown in FIG. In other words, there are various types of general-purpose packages for mounting and configuring the switching elements, and the technical idea of the present invention is, for example, a variety of packages represented by the package PKG3 shown in FIG. 5 and the package PKG11 shown in FIG. It can be applied to general-purpose packages. Specifically, the package PKG11 shown in FIG. 19 also has the semiconductor chip CHP2 with the MOSFET mounted on the semiconductor chip CHP1 with the junction FET, so that it is formed on the source pad SPj and the back surface of the semiconductor chip CHP2. The drain electrode can be directly connected. From this, the package PKG11 shown in FIG. 19 can also directly connect the source of the junction FET and the drain of the MOSFET without using a wire, and therefore, between the drain of the MOSFET and the source of the junction FET. Parasitic inductance (Lse1, Lse2 in FIG. 2) can be almost completely eliminated. Therefore, the package PKG11 shown in FIG. 19 can also suppress voltage application to the MOSFET beyond the withstand voltage, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. As a result, according to the third modification, the reliability of the semiconductor device can be improved.

  FIG. 20 is a diagram showing a cross section of the package PKG11 in the third modification. As shown in FIG. 20, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive PST, and a conductive adhesive (not shown) is mounted on the semiconductor chip CHP1. A semiconductor chip CHP2 is mounted. For example, the semiconductor chip CHP2 (gate pad) and the gate lead GL (gate lead post portion GPST) are electrically connected by the wire Wsm. In addition, the broken line part has shown the part covered with a sealing body.

<Modification 4>
Next, the mounting configuration of the package PKG12 in the fourth modification will be described. FIG. 21 is a diagram showing a mounting configuration of the package PKG12 in the fourth modification. The configuration of the package PKG12 illustrated in FIG. 21 is substantially the same as the configuration of the package PKG1 illustrated in FIG. The difference is the outer shape of the package. Specifically, the package form of the package PKG12 in Modification 4 is SOP (Small Outline Package). Thus, the technical idea of the present invention can be applied not only to the package PKG1 shown in FIG. 3, but also to the package PKG12 shown in FIG. In other words, there are various types of general-purpose packages for mounting and configuring the switching elements, and the technical idea of the present invention is various, for example, represented by the package PKG1 shown in FIG. 3 and the package PKG12 shown in FIG. It can be realized by improving the general-purpose package. Specifically, also in the package PKG12 shown in FIG. 21, for example, since the distance between the gate pad GPj and the source lead SL can be shortened, the length of the wire Wgj connecting the gate pad GPj and the source lead SL is long. The length can be shortened. Therefore, also in the package PKG12 shown in FIG. 21, the parasitic inductance existing in the wire Wgj can be sufficiently reduced. From this, it is possible to suppress the application of a voltage exceeding the withstand voltage to the MOSFET, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. As a result, the reliability of the semiconductor device can be improved also in the package PKG12 shown in FIG.

  FIG. 22 is a diagram showing a cross section of the package PKG12 in the fourth modification. As shown in FIG. 22, the semiconductor chip CHP1 is mounted on the chip mounting portion PLT1 via a conductive adhesive (not shown). For example, the semiconductor chip CHP1 (gate pad GPj) and the source lead SL (source lead post part SPST) are electrically connected by a wire Wgj. In the fourth modification, for example, as shown in FIG. 22, the chip mounting portion PLT1, the semiconductor chip CHP1, the wire Wgj, a part of the lead, and the like are sealed with a sealing body MR made of resin. At this time, as can be inferred from FIGS. 21 and 22, in the package PKG12 (SOP package), the sealing body MR has a substantially rectangular parallelepiped shape, and the first side surface and the second side facing the first side surface. And have side faces. The gate lead GL and the source lead SL are configured to protrude from the first side surface of the sealing body MR, and the drain lead DL is configured to protrude from the second side surface of the sealing body MR. Yes.

Subsequently, an example of another mounting form of the switching element in Modification 4 will be described. FIG. 23 is a diagram showing a mounting configuration of the package PKG13 in the fourth modification. The configuration of the package PKG13 illustrated in FIG. 23 is substantially the same as the configuration of the package PKG3 illustrated in FIG. The difference is the outer shape of the package. Specifically, the package form of the package PKG13 in Modification 4 is SOP (Small Outline Package). Thus, the technical idea of the present invention can be applied not only to the package PKG3 shown in FIG. 5, but also to the package PKG13 as shown in FIG. That is, there are various types of general-purpose packages in which the switching elements are mounted and configured, and the technical idea of the present invention is various, for example, represented by the package PKG3 shown in FIG. 5 and the package PKG13 shown in FIG. It can be applied to general-purpose packages. Specifically, the package PKG13 shown in FIG. 23 also has a semiconductor chip CHP2 with a MOSFET mounted on a semiconductor chip CHP1 with a junction FET, so that it is formed on the source pad SPj and the back surface of the semiconductor chip CHP2. The drain electrode can be directly connected. Therefore, even with the package PKG13 shown in FIG. 23, it is possible to directly connect the source of the junction FET and the drain of the MOSFET without using a wire, and therefore, between the drain of the MOSFET and the source of the junction FET. Parasitic inductance (Lse1, Lse2 in FIG. 2) can be almost completely eliminated. Therefore, the package PKG13 shown in FIG. 23 can also suppress voltage application to the MOSFET that is higher than the withstand voltage, thereby effectively suppressing avalanche breakdown of the cascode-connected MOSFET. As a result, according to the fourth modification, the reliability of the semiconductor device can be improved.

FIG. 24 is a diagram showing a cross section of the package PKG13 in the fourth modification. As shown in FIG. 24, a semiconductor chip CHP1 is mounted on the chip mounting portion PLT via a conductive adhesive (not shown), and a conductive adhesive (not shown) is mounted on the semiconductor chip CHP1. The semiconductor chip CHP2 is mounted via For example, the semiconductor chip CHP1 (gate pad GPj) and the source lead SL (source lead post part SPST) are electrically connected by a wire Wgj. In the fourth modification, for example, as shown in FIG. 24 , the chip mounting portion PLT, the semiconductor chip CHP1, the semiconductor chip CHP2, the wire Wgj, a part of the lead, and the like are sealed with a sealing body MR made of resin. Has been. At this time, some of the leads protrude from the side surfaces on both sides of the sealing body MR.

(Embodiment 2)
In the first embodiment, the device point related to the package structure has been described. In the second embodiment, the device point related to the device structure will be described.

<Layout structure of laminated semiconductor chip>
FIG. 25 is a diagram showing a layout configuration of a semiconductor chip in the second embodiment. The layout configuration of the semiconductor chip shown below includes, for example, silicon (Si) on a semiconductor chip CHP1 in which a junction FET made of a material having a larger band gap than silicon (Si) typified by silicon carbide (Si) is formed. The semiconductor chip CHP2 in which the MOSFET made of the material is formed is stacked and mounted. In FIG. 25, the semiconductor chip CHP1 has a rectangular shape, and a termination region TMj is formed in the outer peripheral region of the rectangular semiconductor chip CHP1. This termination region TMj is a region provided to ensure a withstand voltage. An area inside the termination area TMj is an active area ACTj. A plurality of junction FETs are formed in the active region ACTj.

Although the termination region TMj is provided in the outer peripheral region of the semiconductor chip CHP1, a part of the termination region TMj enters inside, and the gate pad GPj is formed in this region. The gate pad GPj is connected to each gate electrode of a plurality of junction FETs formed in the active region ACTj through a gate wiring. Here, in FIG. 25, the gate pad GPj is arranged at the center of the right side of the semiconductor chip CHP1. In other words, the gate pad GPj is arranged so as to be biased toward the right side, and is arranged so as to be symmetric with respect to the center line extending to the left and right. Thereby, the dispersion | variation in the distance of the gate wiring which connects each gate electrode and gate pad GPj of several junction FET can be suppressed. Therefore, according to the layout configuration shown in FIG. 25, there is an advantage that the characteristics of the plurality of junction FETs formed in the semiconductor chip CHP1 can be used in a uniform manner.

  A source pad SPj is formed on the active region ACTj of the semiconductor chip CHP1. The source pad SPj is electrically connected to the source region of the junction FET formed in the active region ACTj. A rectangular semiconductor chip CHP2 is mounted on the source pad SPj. A plurality of MOSFETs are formed on the semiconductor chip CHP2, and a source pad SPm and a gate pad GPm are formed on the main surface of the semiconductor chip CHP2. The source pad SPm is electrically connected to the source region of the MOSFET, and the gate pad GPj is electrically connected to the gate electrode of the MOSFET.

  FIG. 26 is a diagram showing another layout configuration of the laminated semiconductor chip according to the second embodiment. The layout configuration shown in FIG. 26 is almost the same as the layout configuration shown in FIG. The difference between FIG. 26 and FIG. 25 is that in the layout configuration shown in FIG. 25, the gate pad GPj is arranged at the center on the right side, whereas in the layout configuration shown in FIG. This is a point that is biased toward the lower right corner of CHP1. As described above, in FIG. 26, by disposing the semiconductor chip CHP1 at the lower right corner, the distance from the gate pad GPj to the source lead SL can be minimized as shown in FIG. 6, for example. That is, by adopting the layout configuration shown in FIG. 26, the length of the wire Wgj connecting the gate pad GPj and the source lead SL can be minimized, thereby minimizing the parasitic inductance existing in the wire Wgj. Can be

27 is a cross-sectional view taken along line AA in FIGS. 25 and 26. FIG. As shown in FIG. 27, the drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj , and the drift layer DFTj is formed on the main surface ( front surface) of the semiconductor substrate SUBj . An active region ACTj is formed on the drift layer DFTj, and a gate electrode and a source region of the junction FET are formed in the active region ACTj. A termination region TMj for ensuring a withstand voltage is formed at the end of the active region ACTj, and a source pad SPj is formed on the active region ACTj. For example, an insulating film IL1 made of a silicon oxide film is formed so as to cover the end of the source pad SPj. The configuration so far is the structure of the semiconductor chip CHP1 in which the junction FET is formed, and the semiconductor chip CHP2 in which the MOSFET is formed is mounted on the semiconductor chip CHP1 in which the junction FET is formed.

  Specifically, the drain electrode DEm is in contact with the exposed source pad SPj via, for example, a conductive adhesive (not shown). The drain electrode DEm is formed on the back surface of the semiconductor substrate SUBm, and a drift layer DFTm is formed on the main surface (front surface) opposite to the back surface of the semiconductor substrate SUBm. An active region ACTm is formed in the drift layer DFTm, and termination regions TMm for ensuring a breakdown voltage are formed at both ends of the active region ACTm. In the active region ACTm, a gate electrode and a source region of a MOSFET are formed. A source pad SPm is formed so as to straddle the active region ACTm and the termination region TMm. The insulating film IL2 is formed so as to cover the end portion of the source pad SPm, but most of the surface region of the source pad SPm is exposed from the insulating film IL2. In this manner, the semiconductor chip CHP2 in which the MOSFET is formed is mounted on the semiconductor chip CHP1 in which the junction FET is formed.

  As shown in FIG. 27, the semiconductor chip CHP2 is mounted on the semiconductor chip CHP1 so as to be included in the source pad SPj. Therefore, the drain electrode DEm formed on the back surface of the semiconductor chip CHP2 is in direct contact with the source pad SPj formed on the surface of the semiconductor chip CHP1 with a conductive adhesive (not shown) without a wire. ing. This means that the parasitic inductance interposed between the source of the junction FET and the drain of the MOSFET can be almost completely eliminated. That is, as shown in FIG. 27, the structure in which the semiconductor chip CHP2 is directly mounted on the semiconductor chip CHP1 eliminates the need for a wire to connect the source of the junction FET and the drain of the MOSFET. When a wire is used, parasitic inductance existing in the wire becomes a problem. However, according to the layout configuration in the second embodiment, the source of the junction FET and the drain of the MOSFET are directly connected without using the wire. can do. From this, the parasitic inductance (Lse1, Lse2 in FIG. 2) between the drain of the MOSFET and the source of the junction FET can be almost completely eliminated. From the above, according to the second embodiment, it is possible to suppress the voltage application to the MOSFET that is higher than the withstand voltage, thereby effectively suppressing the avalanche breakdown of the cascode-connected MOSFET. . As a result, according to the second embodiment, the reliability of the semiconductor device can be improved.

As shown in FIG. 27, according to the layout configuration in the present second embodiment, since the source pad SPj is arranged on the active region ACTj , the current flowing through the junction FET can be increased. In this case, since the area of the source pad SPj can be increased, the area of the semiconductor chip CHP2 mounted on the source pad SPj can also be increased. That is, the fact that the area of the semiconductor chip CHP2 can be increased means that the number of MOSFETs formed in the semiconductor chip CHP2 can be increased, and as a result, the current flowing through the plurality of MOSFETs as a whole can be increased. it can. As described above, according to the layout configuration in the second embodiment, the current flowing through the plurality of junction FETs and the current flowing through the plurality of MOSFETs can be increased, so that the junction FET and the MOSFET are cascode-connected. It is possible to easily realize a large current of the switching element. Furthermore, according to the second embodiment, since a junction FET using silicon carbide capable of realizing a high breakdown voltage and a low on-resistance in principle compared to silicon is used, a large current, a high breakdown voltage, And the switching element which can make low ON resistance compatible can be provided.

<Modification of layout configuration>
Next, another layout configuration of the laminated semiconductor chip in the second embodiment will be described. FIG. 28 is a diagram showing a layout configuration of the laminated semiconductor chip in the present modification. As shown in FIG. 28, the semiconductor chip CHP1 has a rectangular shape, and a termination region TMj is formed in the outer peripheral region of the rectangular semiconductor chip CHP1. An active region ACTj, a gate pad GPj, and a source pad SPj are formed in the inner region of the termination region TMj. Here, the feature of this modification is that the active region ACTj, the gate pad GPj, and the source pad SPj are arranged so as not to overlap in a plane. That is, as shown in FIG. 28, the active region ACTj in which the junction FET is formed is arranged so as to avoid the gate pad GPj and the source pad SPj. The semiconductor chip CHP2 is mounted on the source pad SPj.

  FIG. 29 is a diagram showing another layout configuration of the laminated semiconductor chip in the present modification. The layout configuration shown in FIG. 29 is almost the same as the layout configuration shown in FIG. 29 differs from FIG. 28 in that the gate pad GPj is arranged at the center of the right side in the layout configuration shown in FIG. 28, whereas the gate pad GPj is arranged in the semiconductor chip in the layout configuration shown in FIG. This is a point that is biased toward the lower right corner of CHP1.

  Next, FIG. 30 is a cross-sectional view taken along the line AA in FIGS. As shown in FIG. 30, the drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj, and the drift layer DFTj is formed on the main surface (front surface) of the semiconductor substrate SUBj. In this drift layer DFTj, an active region ACTj is formed, and a termination region TMj is formed outside the active region ACTj. In the active region ACTj, the gate electrode GE and the source region SR of the junction FET are formed. An insulating film IL1 is formed over the active region ACTj and the termination region TMj, and a source pad SPj is formed over the insulating film IL1. Here, in the present modification, an important point is that the source pad SPj is not formed in the active region ACTj but is formed on the termination region TMj. That is, in this modification, the active region ACTj and the source pad SPj are arranged so as not to overlap each other in plan view, and the source pad SPj is arranged on the termination region TMj. In FIG. 30, the illustration of the semiconductor chip CHP2 disposed on the source pad SPj is omitted. That is, in FIG. 30 as well as in FIG. 27, the semiconductor chip CHP2 is mounted on the source pad SPj, but since the configuration is the same, in FIG. 30, the semiconductor chip CHP2 disposed on the source pad SPj. Is omitted.

  According to this modified example configured as described above, the following effects can be obtained. That is, the semiconductor chip CHP2 is mounted on the source pad SPj. In this case, stress is applied to the source pad SPj. However, in the present modification, since the active region ACTj in which the junction FET is formed is not formed in the region immediately below the source pad SPj, it is possible to prevent stress from being applied to the active region ACTj. That is, according to the present modification, it is possible to prevent unnecessary stress from being applied to the active region ACTj, thereby preventing mechanical breakdown of the junction FET formed in the active region ACTj.

  Further, a gate pad GPm and a source pad SPm are formed on the surface of the semiconductor chip CHP2 mounted on the source pad SPj, and wires are connected to these pads by wire bonding. Although stress is also generated in this wire bonding process, in the present modification, the semiconductor chip CHP2 and the active region ACTj are arranged so as not to overlap in plan view, so that the stress generated in the wire bonding process is applied to the active region ACTj. Direct transmission can be prevented. As a result, according to the layout configuration of the laminated semiconductor chip in this modification, the stress generated when the semiconductor chip CHP2 is mounted or wire bonding affects the characteristics of the junction FET formed in the active region ACTj of the semiconductor chip CHP1. Can be suppressed. That is, according to this modification, a semiconductor device with a high assembly yield and high reliability can be provided.

<Device structure of MOSFET>
Next, an example of the device structure of the MOSFET formed in the semiconductor chip CHP2 will be described. FIG. 31 is a cross-sectional view showing an example of the device structure of the MOSFET according to the second embodiment. As shown in FIG. 31, for example, a drain electrode DEm made of a gold film, for example, is formed on the back surface of a semiconductor substrate SUBm made of silicon into which an n-type impurity is introduced, and on the main surface side of the semiconductor substrate SUBm. Is formed with a drift layer DFTm made of an n-type semiconductor region. A body region PR made of a p-type semiconductor region is formed in the drift layer DFTm, and a source region SR made of an n-type semiconductor region is formed so as to be included in the body region PR. A surface region of the body region PR sandwiched between the source region SR and the drift layer DFTm functions as a channel formation region. A source electrode SE is formed so as to be electrically connected to both the source region SR and the body region PR. Further, a gate insulating film GOX made of, for example, a silicon oxide film is formed on the surface of the drift layer DFTm including the channel forming region, and the gate electrode G is formed on the gate insulating film GOX.

  In the MOSFET configured in this way, for example, the drain electrode DEm formed on the back surface of the semiconductor substrate SUBm from the drift layer DFTm through the channel formation region formed on the surface of the body region PR from the source region SR. This is a structure called so-called vertical MOSFET. The advantage of this vertical MOSFET is that it can be formed at a high density on the semiconductor chip CHP2, resulting in a MOSFET with a high current density. Therefore, by using the vertical MOSFET for the switching element of the present invention, a switching element having a large current density can be realized.

  For example, in the case of the layout configuration shown in FIG. 28 or FIG. 29, characteristic deterioration based on stress on the junction FET formed in the active region ACTj can be effectively prevented, while the area of the source pad SPj is compared. Become smaller. In this case, the area of the semiconductor chip CHP2 on which the MOSFET disposed on the source pad SPj is formed is also relatively small. However, if the vertical MOSFET shown in FIG. 31 is used as the MOSFET formed on the semiconductor chip CHP2, the area is small. Even with a chip area, a MOSFET having a relatively large current density can be realized. As a result, the current density of the entire cascode-connected switching element can be increased. That is, in particular, even when the area of the semiconductor chip CHP2 on which the MOSFET is formed is reduced by adopting the layout configuration shown in FIG. 28 or FIG. 29, the vertical MOSFET shown in FIG. It is possible to provide a high-performance switching element capable of securing a large current while effectively preventing characteristic deterioration based on stress on the junction FET formed in the region ACTj.

<Problems found by the inventor>
Next, a new problem found by the present inventor will be described. FIG. 32 is a diagram illustrating a current path in the cascode-connected switching element. FIG. 32A is a diagram illustrating a current path at the time of on, and FIG. 32B is a diagram illustrating a current path of a leakage current that flows at the time of off. As shown in FIG. 32A, at the time of ON, the rated current Id flows from the drain of the junction FET Q1 to the source of the MOSFET Q2. That is, the rated current Id flows from the drain D to the source S of the cascode-connected switching elements. At this time, the drain voltage (voltage of the intermediate node Se) of the MOSFET Q2 before the MOSFET Q2 is cut off can be obtained from the product of the on-resistance of the MOSFET Q2 and the rated current Id. For example, if the on-resistance is 10 mΩ and the rated current Id is 40 A, the voltage of the intermediate node Se is 0.4V. Since the voltage of the intermediate node Se is the drain voltage of the MOSFET Q2 and also the source voltage of the junction FET Q1, the voltage Vgs which is the gate voltage of the junction FET Q1 with respect to the source voltage of the junction FET Q1 is −0.4V. is there.

  When transitioning the cascode-connected switching element from the on-state to the off-state, as shown in FIG. 32 (a), from the state where 15V is applied to the gate electrode Gm of the MOSFET Q2, as shown in FIG. 32 (b), 0 V is applied to the gate electrode Gm of the MOSFET Q2. Since the MOSFET Q2 is a normally-off type MOSFET, it is cut off when 0 V is applied to the gate electrode Gm.

  In the process of cutting off MOSFET Q2, in the initial stage, the channel gradually disappears, so the on-resistance between the drain and source of MOSFET Q2 gradually increases. The junction FET Q1 used for the cascode-connected switching element is a normally-on type, and at the initial stage of cutting off the MOSFET Q2, the voltage Vgs of the junction FET Q1 is −0.4 V. Therefore, the junction FET Q1 is Keep on. From this, a current flows from the drain of the junction FET Q1 (for example, in the application of the power supply voltage of 300 V, the drain voltage is about 300 V) toward the source of the junction FET Q1. Therefore, the drain voltage of MOSFET Q2 (the voltage at intermediate node Se) is the product of the on-resistance that increases with the disappearance of the channel and the drain current flowing from the drain of junction FET Q1, so the drain voltage of MOSFET Q2 (at intermediate node Se) Voltage) gradually increases from 0.4V.

  After that, when the channel of the MOSFET Q2 disappears completely and the MOSFET Q2 is completely cut off, a charge is accumulated in the intermediate node Se due to the current flowing from the junction FET Q1, so that the drain voltage of the MOSFET Q2 (the voltage of the intermediate node Se) ) Further rises and rises to the cutoff voltage (for example, about 5V to 15V) of the junction FET Q1. In this state, the junction FET Q1 is turned off, and the drain current of the junction FET Q1 does not flow. That is, the rise of the drain voltage of MOSFET Q2 (the voltage of intermediate node Se) stops and this state is maintained.

  However, in the cascode-connected switching element, even when the voltage Vgs of the junction FET Q1 is about −5 V to −15 V, the leakage current Idl may flow between the drain and the source of the junction FET Q1. Found. When this leakage current Idl flows, charge is accumulated in the intermediate node Se, and therefore the drain voltage of the MOSFET Q2 (voltage of the intermediate node Se) increases. For this reason, when the above-described leakage current Idl increases, the drain voltage of the MOSFET Q2 (voltage of the intermediate node Se) may become a voltage higher than the breakdown voltage of the MOSFET Q2 (for example, 30 V or higher). As a result, the MOSFET Q2 performs an avalanche operation, and eventually the MOSFET Q2 may be destroyed. As a countermeasure, the use of a high-breakdown-voltage high-voltage MOSFET increases the possibility of preventing the above-described MOSFET avalanche breakdown. However, when a high-breakdown-voltage MOSFET is used, the drift layer is thickened to ensure the breakdown voltage. Need to design. When the thickness of the low-concentration drift layer is increased in this way, the on-resistance of the MOSFET is increased, which causes a problem that conduction loss increases when the cascode-connected switching element is turned on. That is, in order to prevent the avalanche breakdown of the MOSFET while ensuring the high performance of the cascode-connected switching element, it is necessary to devise other than the configuration in which the low-concentration drift layer is thickened. Therefore, in the second embodiment, the device structure of the junction FET is devised in order to prevent the avalanche breakdown of the MOSFET while ensuring the high performance of the cascode-connected switching element. The device structure of the junction FET according to the second embodiment to which this device is applied will be described below.

<Device structure of junction FET>
FIG. 33 is a cross-sectional view showing the device structure of the junction FET in the second embodiment. As shown in FIG. 33, the junction FET in the second embodiment has a semiconductor substrate SUBj, and a drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj. On the other hand, a drift layer DFTj is formed on the main surface side opposite to the back surface of the semiconductor substrate SUBj, and a plurality of trenches TR are formed in the drift layer DFTj. A gate electrode GE (also referred to as a gate region) is formed on each side surface and bottom surface of each of the plurality of trenches TR, and is sandwiched between the gate electrodes GE formed on the side surfaces and bottom surfaces of adjacent trenches TR. A channel formation region is formed. A source region SR is formed above the channel formation region. In the junction FET configured as described above, the extension of the depletion layer from the gate electrode GE is controlled by controlling the voltage applied to the gate electrode GE. As a result, when the depletion layers extending from the adjacent gate electrodes GE are connected, the channel formation region disappears and the off state is realized. On the other hand, when the depletion layers extending from the adjacent gate electrodes GE are not connected, the channel formation is performed. A region is formed to realize the on state.

  Here, the feature of the junction FET in the second embodiment is that the channel length CL of the channel formation region is 1 μm or more. In other words, the feature of the second embodiment is that the distance between the bottom of the source region SR and the bottom of the gate electrode GE is 1 μm or more. Thereby, since the channel length of the channel formation region can be increased, the electrostatic potential in the channel formation region when the junction FET is turned off can be increased. From this, according to the second embodiment, the leakage current flowing between the drain and the source of the junction FET can be suppressed smaller than in the case of using a device structure having a channel length of about 0.5 μm. As described above, the advantage that the channel length CL is 1 μm or more is that the leakage current can be reduced due to the fact that the electrostatic potential in the channel formation region at the time of OFF can be increased. It is considered that the increase in the length of time contributes to the reduction of leakage current.

  Further, in the device structure of the junction FET shown in FIG. 33, the distance between the semiconductor substrate SUBj and the gate electrode GE is smaller than the distance between the semiconductor substrate SUBj serving as the drain and the source region SR. When the junction FET is off, a reverse voltage (reverse bias) is applied between the gate electrode GE and the drift layer DFTj. As a result, the leakage current that flows through the junction FET at the time of off-state is the reverse current (between the semiconductor substrate SUBj and the gate electrode GE, which has a shorter distance than the current flowing between the semiconductor substrate SUBj and the source region SR, which are separated from each other) (Leakage current) is considered to flow mainly. Therefore, according to the second embodiment, after the junction FET is cut off, the leakage current flowing between the drain and source of the junction FET can be greatly reduced. From this, according to the second embodiment, it is possible to suppress the drain voltage of the MOSFET from rising to a voltage higher than the breakdown voltage due to the leak current flowing between the drain and the source of the junction FET at the time of OFF, Thereby, it is possible to effectively prevent the MOSFET from being avalanche-operated and finally destroying the MOSFET. Note that, according to the junction FET having the trench structure shown in FIG. 33, the junction FET can be formed at a high density, so that it is needless to say that a switching element having a high current density can be realized.

  Next, FIG. 34 is a cross-sectional view showing another device structure of the junction FET in the second embodiment. As shown in FIG. 34, another junction FET in the second embodiment has a semiconductor substrate SUBj, and a drain electrode DEj is formed on the back surface of the semiconductor substrate SUBj. On the other hand, a drift layer DFTj is formed on the main surface side opposite to the back surface of the semiconductor substrate SUBj, and a plurality of gate electrodes GE are formed in the drift layer DFTj so as to be embedded at a distance. Yes. A source region SR is formed on the surface of the drift layer DFTj between the adjacent gate electrodes GE. The thus configured junction FET shown in FIG. 34 is a vertical junction FET having no so-called trench structure.

  The junction FET having such a structure is also characterized in that the channel length CL of the channel formation region is 1 μm or more. In other words, the feature is that the distance (channel length CL) between the bottom of the source region SR and the bottom of the gate electrode GE is 1 μm or more. Thereby, since the channel length of the channel formation region can be increased, even in the junction FET shown in FIG. 34, the electrostatic potential in the channel formation region at the off time can be increased. Therefore, also in the junction FET shown in FIG. 34, the leakage current flowing between the drain and the source of the junction FET can be suppressed smaller than when a device structure having a channel length of about 0.5 μm is used. As described above, the advantage that the channel length CL is 1 μm or more is that the leakage current can be reduced due to the fact that the electrostatic potential in the channel formation region at the time of OFF can be increased. It is considered that the increase in the length of time contributes to the reduction of leakage current.

  The advantage of the junction FET shown in FIG. 34 is that the device structure is simple and the manufacturing cost can be reduced. Further, in the junction FET shown in FIG. 33, it is necessary to form a conductive impurity (p-type impurity) on the side surface of the trench TR by means such as an advanced oblique ion implantation technique, whereas the junction FET shown in FIG. Then, in order to form the gate electrode GE, it is not necessary to use an advanced oblique ion implantation technique, and there is an advantage that the accuracy of the impurity profile introduced into the gate electrode GE is high. That is, according to the junction FET shown in FIG. 34, an advantage that a junction FET with uniform characteristics can be easily formed is obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the example in which the gate electrode of the MOSFET is driven by the gate drive circuit (gate driver) has been described, but the gate electrode of the junction FET may be driven by the gate drive circuit. In this case, since the source voltage of the junction FET can be controlled to a desired level by controlling the gate electrode of the junction FET with the gate drive circuit, an effect of suppressing the surge voltage at the intermediate node can be obtained. In the case of this configuration, the number of terminals increases, but there is an advantage that a switching element with lower loss can be provided.

  Further, the lead arrangement is not limited to the package form described in the first embodiment. That is, the arrangement positions of the gate lead, the drain lead, and the source lead can be variously changed. For example, when the package is mounted on the mounting substrate, the lead arrangement of the package can be determined so that the existing lead arrangement can be used. In this case, it is not necessary to change the mounting substrate, and an increase in cost due to the design change can be suppressed.

  Further, the layout configuration of the laminated semiconductor chip is not particularly limited to the layout configuration described in the specification, and the shape of each semiconductor chip, the shape of the pad, the shape of the termination region, and the like are not particularly limited. Further, the structure of the junction FET or MOSFET is not limited, and various existing structures can be applied. Furthermore, the impurity profile of the device can be freely changed. For example, in the MOSFET, the impurity concentration on the surface may be reduced so as not to punch through, and the impurity may be implanted so as to gradually increase the impurity concentration in the depth direction.

  Note that the MOSFET described above is not limited to the case where the gate insulating film is formed from an oxide film, but is assumed to include a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that forms the gate insulating film widely from an insulating film. ing. That is, in this specification, the term MOSFET is used for convenience, but this MOSFET is used herein as a term intended to include a MISFET.

  As the metal material of each wire described above, gold (Au), gold alloy, copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or the like may be used.

  The switching element of the present invention can be applied to, for example, a power circuit, but is not limited thereto. For example, an inverter for an air conditioner, a power conditioner for a solar power generation system, an inverter for a hybrid vehicle or an electric vehicle It can be applied to various devices such as personal computer power modules and white LED inverters.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

ACTj Active region ACTm Active region CHP1 Semiconductor chip CHP2 Semiconductor chip CL Channel length CLP clip D Drain D1 Drain D2 Drain DEj Drain electrode DEm Drain electrode DFTj Drift layer DFTm Drift layer Dj1 Drain Dj2 Drain Dm Drain Dm Drain Drain Dm Drain Dm Drain Dm Drain Dm Drain Electrode GE Gate electrode Gj Gate electrode Gj1 Gate electrode Gj2 Gate electrode GL Gate lead Gm Gate electrode Gm1 Gate electrode Gm2 Gate electrode GOX Gate insulation film GPj Gate pad GPm Gate pad GPST Gate lead post part Id Leakage current IL1 Insulating film Lgi1 Parasitic inductance Lgi2 Parasitic inductor LL Load inductance Ls Parasitic inductance Lse1 Parasitic inductance Lse2 Parasitic inductance MR Sealed body PKG1 package PKG2 package PKG3 package PKG4 package PKG5 package PKG6 package PKG7 package PKG8 package PKG9 package PKG10 package PKG11 package PKG13 package PKG13 package PKG13 package PKG13 package TKG chip PLT2 Chip mounting part PR Body region Q1 Junction FET
Q1a junction FET
Q1b junction FET
Q2 MOSFET
Q2a MOSFET
Q2b MOSFET
S source S1 source S2 source SE source electrode Se intermediate node Sj source Sj1 source Sj2 source SL source lead Sm source Sm1 source Sm2 source SPj source pad SPm source pad SPST source lead post portion SR source region SUBj semiconductor substrate SUBm semiconductor substrate TMj termination region TMm Termination region TR Trench Vak voltage Vdsu voltage Vdsmu voltage Vdsmd voltage Wds wire Wgj wire Wgm wire Wsm wire

Claims (4)

A first metal plate having a first surface and a second surface opposite to the first surface;
A second metal plate having a third surface and a fourth surface opposite to the third surface;
A first semiconductor chip mounted on the first surface of the first metal plate;
A second semiconductor chip mounted on the third surface of the second metal plate;
The first lead;
A second lead;
A third lead connected to the first metal plate;
A sealing body that seals the first semiconductor chip, the second semiconductor chip, a part of the first lead, a part of the second lead, and a part of the third lead;
The first semiconductor chip includes a normally-on type junction FET made of silicon carbide and having a first gate electrode, a first source, and a first drain, and the first source of the junction FET A first surface on which a first source pad electrically connected, a first gate pad electrically connected to the first gate electrode of the junction FET, and the first drain of the junction FET; A first back surface electrically connected and opposite to the first surface;
The second semiconductor chip includes a normally-off type MOSFET made of silicon and having a second gate electrode, a second source, and a second drain, and is electrically connected to the second source of the MOSFET. A second surface formed with a second source pad, and a second surface formed with a second gate pad electrically connected to the second gate electrode of the MOSFET, and electrically connected to the second drain of the MOSFET, A second back surface opposite to the second surface;
Since the first back surface of the first semiconductor chip is mounted on the first surface of the first metal plate via a first conductive adhesive, the first drain of the junction FET is Electrically connected to the third lead,
Since the second back surface of the second semiconductor chip is mounted on the third surface of the second metal plate via a second conductive adhesive, the second drain of the MOSFET is the first drain. Electrically connected to two metal plates,
The first gate pad of the first semiconductor chip is electrically connected to the first lead through a first wire;
The second source pad of the second semiconductor chip is electrically connected to the first lead via the second wire, thereby being electrically connected to the first gate pad of the first semiconductor chip. And
The second gate pad of the second semiconductor chip is electrically connected to the second lead through a third wire;
The first source pad of the first semiconductor chip is electrically connected to the second metal plate through a fourth wire;
The semiconductor device, wherein the first gate pad of the first semiconductor chip is disposed closer to the first lead than the second lead and the third lead in a plan view. The semiconductor device according to claim 1,
The sealing body has a rectangular parallelepiped shape having a first side surface and a second side surface facing the first side surface,
A portion of each of the first lead, the second lead, and the third lead that is not sealed by the sealing body protrudes from the first side surface. The semiconductor device according to claim 2,
The semiconductor device, wherein the second surface of the first metal plate and the fourth surface of the second metal plate are covered with a sealing body. The semiconductor device according to claim 2,
A semiconductor device, wherein a part of a sealing body is disposed between the first metal plate and the second metal plate.

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