CN103839915A - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN103839915A CN103839915A CN201410053576.4A CN201410053576A CN103839915A CN 103839915 A CN103839915 A CN 103839915A CN 201410053576 A CN201410053576 A CN 201410053576A CN 103839915 A CN103839915 A CN 103839915A
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- 239000010409 thin film Substances 0.000 title claims abstract description 128
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 title abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 86
- 239000010408 film Substances 0.000 claims abstract description 74
- 230000004888 barrier function Effects 0.000 claims description 63
- 238000000034 method Methods 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 claims description 33
- 238000000059 patterning Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 238000007715 excimer laser crystallization Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 73
- 238000010586 diagram Methods 0.000 description 10
- 239000003292 glue Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- Thin Film Transistor (AREA)
Abstract
The invention relates to a thin film transistor array substrate and a manufacturing method thereof, and belongs to the technical field of display equipment. In the manufacturing process of the thin film transistor array substrate, VDD lines and VSS lines formed by a photoetching patterned metal film are utilized, a first insulating layer covered with the metal film grows on a bottom plate, and accordingly the VDD lines and VSS lines are both completed through first-time photoetching and buried below all insulating layers, furthermore, the VDD lines and VSS lines are effectively prevented from being directly exposed in air or making direct contact with Frit plaste, and the yield and performance reliability of products are substantially promoted; meanwhile, space can be provided for wider power lines in arrangement, and the thin film transistor array substrate can be suitable for display equipment with higher resolution. The thin film transistor array substrate is simple in structure, the manufacturing method of the thin film transistor array substrate is easy and convenient to achieve, and the application range is wide.
Description
Technical field
The present invention relates to display device technical field, particularly light emitting diode indicator technical field, specifically refers to a kind of thin-film transistor array base-plate and manufacture method thereof.
Background technology
In existing thin-film transistor (TFT) array base-plate structure, as shown in Figure 1, near COG(Chip On Glass) in the circuit of side, vdd line 11 and VSS line 13(VSS out), 14(VSS in) all connect up with data wire place metal level, because frit(frit) glue 12 belows and around can not have organic film exist, so vdd line 11 directly contacts with Frit glue 12 with VSS line 13,14, or be directly exposed in air, easily be subject to the impact of following process, thereby affect product reliability.
Meanwhile, vdd line is the power supply of OLED device, and with the lifting of resolution, Pixel Dimensions diminishes, and technological requirement wishes that VDD power line is more wide better, but in existing TFT substrate, there is no enough spatial arrangement vdd lines.
Summary of the invention
The object of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of utilization to increase a photoetching process, vdd line and VSS line are all completed in photoetching for the first time, be embedded in below all insulating barriers, preventing that vdd line and VSS line are directly exposed in air or with Frit glue directly contacts, thereby improving product yield and performance reliability, can provide space for the wider power line of arranging again simultaneously, be applicable to very much the display device that resolution is higher, and simple in structure, the thin-film transistor array base-plate that manufacture method is relatively easy and manufacture method thereof.
In order to realize above-mentioned object, thin film transistor base plate of the present invention has following formation:
This thin film transistor base plate comprises base plate, metal film, the first insulating barrier, semiconductor layer, the second insulating barrier, the first metal layer, the 3rd insulating barrier and the second metal level.
Wherein, metal film is formed on described base plate, as bottom electrode, and vdd line and the VSS line of patterning formation.The first insulating barrier is formed on base plate and covers described metal film.Semiconductor layer is formed on the first described insulating barrier, has the first film transistor source of patterning formation and the source electrode of the second thin-film transistor.On the first insulating barrier described in the second insulating barrier is formed at and described semiconductor layer.The first metal layer is as gate metal and top electrode, and the first film transistor gate of patterning formation and grid and the drain electrode of the second thin-film transistor.The 3rd insulating barrier is formed on described the first metal layer, on the 3rd insulating barrier, offer the first connecting hole, the second connecting hole, the 3rd connecting hole and the 4th connecting hole, the first described connecting hole exposes the first film transistor source on described semiconductor layer, and the second described connecting hole exposes described the first film transistor source and the grid of the second thin-film transistor; The 3rd described connecting hole exposes described vdd line and the drain electrode of the second thin-film transistor; The 4th described connecting hole exposes the second thin-film transistor source electrode on described semiconductor layer.The second metal level is formed on the 3rd described insulating barrier, has the data wire that patterning forms, and described data wire connects described the first film transistor source by the first described connecting hole; Described data wire is electrically connected described the first film transistor source and the grid of the second thin-film transistor by the second described connecting hole; This data wire is electrically connected described vdd line and the drain electrode of the second thin-film transistor by the 3rd described connecting hole; Described data wire connects the second described thin-film transistor source electrode by the 4th described connecting hole.
This thin film transistor base plate also comprises the planarization layer being formed on the second described metal level, on this hardware and software platform layer, on the position corresponding with the 4th described connecting hole, is provided with the perforate that exposes the data wire that connects the second thin-film transistor source electrode.
This thin film transistor base plate also comprises that the 3rd metal level being formed on described hardware and software platform layer, as OLED anode, connects the second described thin-film transistor source electrode by described data wire.
In this thin film transistor base plate, described the first film transistor is switching thin-film transistor, and the second described thin-film transistor is for driving thin-film transistor.
In this thin film transistor base plate, described semiconductor layer is polysilicon layer.
The present invention also provides a kind of manufacture method of thin-film transistor array base-plate, and the method comprises the following steps:
(1) layer of metal film of growing on base plate forms vdd line and the VSS line of bottom electrode, patterning;
(2) first insulating barrier of growing on described base plate and described metal film;
(3) grown semiconductor layer on the first described insulating barrier, and the first film transistor source that this semiconductor layer patternization is formed and the source electrode of the second thin-film transistor;
(4) second insulating barrier of growing on the first described insulating barrier and described semiconductor layer;
(5) on the second described insulating barrier, grow the first metal layer as gate metal and top electrode, and this first metal layer patterning is formed to grid and the drain electrode of the first film transistor gate and the second thin-film transistor;
(6) growth regulation three insulating barriers on described the first metal layer, and on the 3rd insulating barrier, offer the first connecting hole, the second connecting hole, the 3rd connecting hole and the 4th connecting hole, the first described connecting hole exposes the first film transistor source on described semiconductor layer, and the second described connecting hole exposes described the first film transistor source and the grid of the second thin-film transistor; The 3rd described connecting hole exposes described vdd line and the drain electrode of the second thin-film transistor; The 4th described connecting hole exposes the second thin-film transistor source electrode on described semiconductor layer;
(7) second metal level of growing on the 3rd described insulating barrier, and this second metal level of patterning forms data wire, described data wire connects described the first film transistor source by the first described connecting hole; Described data wire is electrically connected described the first film transistor source and the grid of the second thin-film transistor by the second described connecting hole; This data wire is electrically connected described vdd line and the drain electrode of the second thin-film transistor by the 3rd described connecting hole; Described data wire connects the second described thin-film transistor source electrode by the 4th described connecting hole, and utilizes this data wire to described storage capacitance data writing voltage.
In the manufacture method of this thin-film transistor array base-plate, further comprising the steps of:
(8) on the second described metal level, grow organic film as planarization layer, in this hardware and software platform layer, on the position corresponding with the 4th described connecting hole, offer perforate, to expose the data wire that connects the second thin-film transistor source electrode.
In the manufacture method of this thin-film transistor array base-plate, described step (8) specifically comprises the following steps:
(81) on the second described metal level, grow organic film as planarization layer;
(82) utilize developing method to remove being positioned at the locational part hardware and software platform layer that the 4th described connecting hole is corresponding, form the perforate of the data wire that exposes the source electrode that connects the second thin-film transistor.
In the manufacture method of this thin-film transistor array base-plate, further comprising the steps of:
(9) on described hardware and software platform layer, growth regulation three metal levels are as OLED anode, and the 3rd metal level connects the second described thin-film transistor source electrode by described data wire.
In the manufacture method of this thin-film transistor array base-plate, described step (3) specifically comprises the following steps:
(31) amorphous silicon layer of growing on the first described insulating barrier;
(32) make described amorphous silicon layer form polysilicon layer by Excimer-Laser Crystallization or thermal annealing method;
(33) the transistorized source electrode of the first film that the polysilicon layer described in patterning forms and the source electrode of the second thin-film transistor.
Thin-film transistor array base-plate and the manufacture method thereof of this invention are adopted, because it utilizes the film formed vdd line of lithographic patterning metal and VSS line, and first insulating barrier of growing on metal film, make thus vdd line and VSS line all complete in photoetching for the first time, be embedded in below all insulating barriers, thereby effectively preventing that vdd line and VSS line are directly exposed in air or with Frit glue directly contacts, product yield and performance reliability are significantly promoted, can provide space for the wider power line of arranging again simultaneously, be applicable to the display device that resolution is higher, and film transistor array base plate structure of the present invention is simple, its manufacture method is also relatively easy, have wide range of applications.
Brief description of the drawings
Fig. 1 is the structural representation of thin-film transistor array base-plate of the prior art.
Fig. 2 is the structural representation of thin-film transistor array base-plate of the present invention.
Fig. 3 a is the schematic diagram that forms vdd line in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 3 b is the schematic diagram that forms polysilicon layer in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 3 c is the schematic diagram that forms gate metal in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 3 d is the schematic diagram that forms contact connecting hole in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 3 e is the schematic diagram that forms data wire metal in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 3 f is the schematic diagram that forms anode contact perforate in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 3 g is the schematic diagram that forms OLED anode in thin-film transistor array base-plate manufacture process of the present invention.
Fig. 4 is the schematic diagram of vdd line and drive TFT drain electrode connected mode in thin-film transistor array base-plate of the present invention.
Fig. 5 is the schematic diagram of thin-film transistor array base-plate of the present invention and FPC flexible printed circuit board connected mode.
Fig. 6 is the schematic diagram of VSS line and negative electrode connected mode in thin-film transistor array base-plate of the present invention.
Embodiment
In order more clearly to understand technology contents of the present invention, describe in detail especially exemplified by following examples.
In one embodiment, as shown in Fig. 2,3a to 3e, 4 to 6, thin film transistor base plate of the present invention comprises: base plate, metal film 31, the first insulating barrier 32, semiconductor layer 33, the second insulating barrier 34, the first metal layer 35, the 3rd insulating barrier 36 and the second metal level 37.
The first insulating barrier 32 is formed on described base plate and covers described metal film 31.
On the first insulating barrier 32 described in the second insulating barrier 34 is formed at and described semiconductor layer 33.
The first metal layer 35 is as the top electrode of gate metal 35 and storage capacitance Cs, and has the first film transistor T 1 grid that patterning forms and grid and the drain electrode of the second thin-film transistor T2.
The 3rd insulating barrier 36 is formed on described the first metal layer 35, on the 3rd insulating barrier 36, offer the first connecting hole V1, the second connecting hole V2, the 3rd connecting hole V3 and the 4th connecting hole V4, the first described connecting hole V1 exposes the first film transistor T 1 source electrode on described semiconductor layer 33, and the second described connecting hole V2 exposes described the first film transistor T 1 source electrode and the grid of the second thin-film transistor T2; The 3rd described connecting hole V3 exposes described vdd line 31 and the drain electrode of the second thin-film transistor T2; The 4th described connecting hole V4 exposes the second thin-film transistor T2 source electrode on described semiconductor layer 33.The second metal level 37 is formed on the 3rd described insulating barrier 36, has 37 data wires that patterning forms, and described data wire 37 connects described the first film transistor T 1 source electrode by the first described connecting hole V1; Described data wire 37 is electrically connected described the first film transistor T 1 source electrode and the grid of the second thin-film transistor T2 by the second described connecting hole V2; This data wire 37 is electrically connected described vdd line 31 and the drain electrode of the second thin-film transistor T2 by the 3rd described connecting hole V3; Described data wire 37 connects the second described thin-film transistor T2 source electrode by the 4th described connecting hole V4.
The manufacture method of the thin-film transistor array base-plate described in this execution mode comprises the following steps:
(1) layer of metal film 31 of growing on base plate forms vdd line and the VSS line of storage capacitance Cs bottom electrode, patterning;
(2) first insulating barrier 32 of growing on described base plate and described metal film 31;
(3) grown semiconductor layer 33 on the first described insulating barrier 32, and the first film transistor T 1 source electrode that these semiconductor layer 33 patternings are formed and the source electrode of the second thin-film transistor T2;
(4) second insulating barrier 34 of growing on the first described insulating barrier 32 and described semiconductor layer 33;
(5) on the second described insulating barrier 34, grow the first metal layer 35 as gate metal 35 and storage capacitance Cs top electrode, and these the first metal layer 35 patternings are formed to grid and the drain electrode of the first film transistor T 1 grid and the second thin-film transistor T2;
(6) growth regulation three insulating barriers 36 on described the first metal layer 35, and on the 3rd insulating barrier 36, offer the first connecting hole V1, the second connecting hole V2, the 3rd connecting hole V3 and the 4th connecting hole V4, the first described connecting hole V1 exposes the first film transistor T 1 source electrode on described semiconductor layer 33, and the second described connecting hole V2 exposes described the first film transistor T 1 source electrode and the grid of the second thin-film transistor T2; The 3rd described connecting hole V3 exposes described vdd line 31 and the drain electrode of the second thin-film transistor T2; The 4th described connecting hole V4 exposes the second thin-film transistor T2 source electrode on described semiconductor layer 33;
(7) second metal level 37 of growing on the 3rd described insulating barrier 36, and this second metal level 37 of patterning forms data wire 37, described data wire 37 connects described the first film transistor T 1 source electrode by the first described connecting hole V1; Described data wire 37 is electrically connected described the first film transistor T 1 source electrode and the grid of the second thin-film transistor T2 by the second described connecting hole V2; This data wire 37 is electrically connected described vdd line 31 and the drain electrode of the second thin-film transistor T2 by the 3rd described connecting hole V3; Described data wire 37 connects the second described thin-film transistor T2 source electrode by the 4th described connecting hole V4, and utilizes this data wire 37 to described storage capacitance Cs data writing voltage.
In a preferred embodiment, as shown in Fig. 3 f and 3g, this thin film transistor base plate also comprises the planarization layer 38 that is formed on the second described metal level 37 and the 3rd metal level 39 on hardware and software platform layer 38, on this hardware and software platform layer 38, on the position corresponding with the 4th described connecting hole V4, is provided with the perforate that exposes the data wire 37 that connects the second thin-film transistor T2 source electrode.The 3rd metal level 39, as OLED anode, connects the second described thin-film transistor T2 source electrode by described data wire 37.
Preferred embodiment the manufacture method of described thin film transistor base plate is further comprising the steps of for this:
(8) on the second described metal level 37, grow organic film 38 as planarization layer 38, in this hardware and software platform layer 38, on the position corresponding with the 4th described connecting hole V4, offer perforate, to expose the data wire 37 that connects the second thin-film transistor T2 source electrode;
(9) on described hardware and software platform layer 38, growth regulation three metal levels 39 are as OLED anode, and the 3rd metal level 39 connects the second described thin-film transistor T2 source electrode by described data wire 37.
Wherein, described step (8) specifically comprises the following steps:
(81) on the second described metal level 37, grow organic film 38 as planarization layer 38;
(82) utilize developing method to remove being positioned at described locational part hardware and software platform layer 38 corresponding to the 4th connecting hole V4, form the perforate of the data wire 37 that exposes the source electrode that connects the second thin-film transistor T2.
In preferred execution mode, described semiconductor layer 33 is p-Si polysilicon layer.
Described in this preferred execution mode, in the manufacture method of thin film transistor base plate, described step (3) specifically comprises the following steps:
(31) amorphous silicon layer of growing on the first described insulating barrier 32;
(32) make described amorphous silicon layer form polysilicon layer 33 by Excimer-Laser Crystallization or thermal annealing method;
(33) source electrode of the first film transistor T 1 that the polysilicon layer 33 described in patterning forms and the source electrode of the second thin-film transistor T2.
In the actual manufacture process of thin-film transistor array base-plate of the present invention, the layer of metal film of first growing, the bottom electrode of formation vdd line 31 and storage capacitance; Forming grow successively on the vdd line 31 of patterning insulating barrier 32 and amorphous silicon 33, use ELA(Excimer-Laser Crystallization) or the method formation p-Si of thermal annealing, semiconductor pattern 33 finally formed; On the p-Si33 of patterning, grow successively in insulating barrier 34(figure and do not draw) and gate metal 35, etching grid metal level 35, form the grid and the grid line that drive T1, the grid of T2, the top electrode of storage capacitance Cs, wherein T1 is switching TFT, and T2 is drive TFT, and Cs is grid and the drain electrode storage capacitance before of T2 pipe.Then, at the gate metal 35 of the patterning insulating barrier 36 of growing, the insulating barrier 32,34 and 36 that etching is all, forms not contact hole V1, V2, V3, the V4 of same-action.Wherein the object of V1 contact hole is to expose P-Si, is then connected with data wire, writes driving voltage; The object of contact hole V2 is to expose the source electrode of T1 and the grid of T2, then will be electrically connected the phase with data wire metal; The object in V3 hole is the drain electrode of exposing vdd line and T2 pipe, then in postorder processing, with data wire, the drain electrode of vdd line and T2 pipe is electrically connected; The object of V4 pipe is to expose P-SI, and T2 pipe source electrode is connected with the anode of OLED device, and driving OLED is luminous.Complete after the etching of contact hole, growing metal layer 37, then forms data wire pattern, and wherein data wire 37 is connected by the source electrode of V1 contact hole and T1, data voltage is write and is stored in Cs, equal covering metal layer 37 above V2, V3, V4.Above metal level 37, spin coating one deck organic film is used as planarization layer 38, then the OC layer of V4 top is taken down by the mode of developing, and object is to expose metal level 37, and the anode of the source electrode of T2 and OLED is connected.The last layer of metal 39 of growing above flatness layer 38 is served as the anode of OLED display device.
The vdd line of thin-film transistor array base-plate of the present invention and drive TFT drain electrode connected mode, with FPC flexible printed circuit board connected mode and VSS line and negative electrode connected mode respectively as shown in Figure 4,5, 6.Wherein label 39 is pixel electrode, and label 40 is pixel boundary layer, and label 41 is negative electrode.
Adopt method of the present invention to produce thin-film transistor array base-plate, only increase by a layer photoetching number of times, and form layer protective layer at vdd line with above VSS line, prevent in postorder processing influenced., vdd line is arranged in below P-Si rete meanwhile, can effectively prevents that vdd line from directly directly contacting with Frit glue.
Thin-film transistor array base-plate and the manufacture method thereof of this invention are adopted, because it utilizes the film formed vdd line of lithographic patterning metal and VSS line, and first insulating barrier of growing on metal film, make thus vdd line and VSS line all complete in photoetching for the first time, be embedded in below all insulating barriers, thereby effectively preventing that vdd line and VSS line are directly exposed in air or with Frit glue directly contacts, product yield and performance reliability are significantly promoted, can provide space for the wider power line of arranging again simultaneously, be applicable to the display device that resolution is higher, and film transistor array base plate structure of the present invention is simple, its manufacture method is also relatively easy, have wide range of applications.
In this specification, the present invention is described with reference to its specific embodiment.But, still can make various amendments and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (10)
1. a thin film transistor base plate, is characterized in that, comprising:
Base plate;
Metal film, is formed on described base plate, has vdd line and the VSS line of bottom electrode, patterning formation;
The first insulating barrier, is formed on described base plate and covers described metal film;
Semiconductor layer, is formed on the first described insulating barrier, has the transistorized source electrode of the first film of patterning formation and the source electrode of the second thin-film transistor;
The second insulating barrier, on the first insulating barrier described in being formed at and described semiconductor layer;
The first metal layer, has top electrode, the transistorized grid of the first film of patterning formation and grid and the drain electrode of the second thin-film transistor;
The 3rd insulating barrier, is formed on described the first metal layer, offers the first connecting hole, the second connecting hole, the 3rd connecting hole and the 4th connecting hole on the 3rd insulating barrier; The first described connecting hole exposes the first film transistor source on described semiconductor layer, the second described connecting hole exposes described the first film transistor source and the grid of the second thin-film transistor, the 3rd described connecting hole exposes described vdd line and the drain electrode of the second thin-film transistor, and the 4th described connecting hole exposes the second thin-film transistor source electrode on described semiconductor layer;
The second metal level, is formed on the 3rd described insulating barrier, has the data wire that patterning forms; Described data wire connects described the first film transistor source by the first described connecting hole; Described data wire is electrically connected described the first film transistor source and the grid of the second thin-film transistor by the second described connecting hole; Described data wire is electrically connected described vdd line and the drain electrode of the second thin-film transistor by the 3rd described connecting hole; Described data wire connects the source electrode of the second described thin-film transistor by the 4th described connecting hole.
2. thin film transistor base plate according to claim 1, is characterized in that, also comprises:
Planarization layer, is formed on the second described metal level, is provided with perforate, to expose the data wire of the source electrode that connects the second thin-film transistor in this hardware and software platform layer on the position corresponding with the 4th described connecting hole.
3. thin film transistor base plate according to claim 2, is characterized in that, also comprises:
The 3rd metal level, is formed on described hardware and software platform layer, as OLED anode, connects the source electrode of the second described thin-film transistor by described data wire.
4. thin film transistor base plate according to claim 1, is characterized in that, described the first film transistor is switching thin-film transistor, and the second described thin-film transistor is for driving thin-film transistor.
5. thin film transistor base plate according to claim 1, is characterized in that, described semiconductor layer is polysilicon layer.
6. a manufacture method for thin-film transistor array base-plate, is characterized in that, described method comprises the following steps:
(1) layer of metal film of growing on base plate forms vdd line and the VSS line of bottom electrode, patterning;
(2) first insulating barrier of growing on described base plate and described metal film;
(3) grown semiconductor layer on the first described insulating barrier, and the transistorized source electrode of the first film that this semiconductor layer patternization is formed and the source electrode of the second thin-film transistor;
(4) second insulating barrier of growing on the first described insulating barrier and described semiconductor layer;
(5) on the second described insulating barrier, grow the first metal layer as gate metal and top electrode, and described the first metal layer patterning is formed to grid and the drain electrode of the first film transistor gate and the second thin-film transistor;
(6) growth regulation three insulating barriers on described the first metal layer, and on the 3rd insulating barrier, offer the first connecting hole, the second connecting hole, the 3rd connecting hole and the 4th connecting hole; The first described connecting hole exposes the first film transistor source on described semiconductor layer, and the second described connecting hole exposes described the first film transistor source and the grid of the second thin-film transistor; The 3rd described connecting hole exposes described vdd line and the drain electrode of the second thin-film transistor; The 4th described connecting hole exposes the second thin-film transistor source electrode on described semiconductor layer;
(7) second metal level of growing on the 3rd described insulating barrier, and this second metal level of patterning forms data wire; Described data wire connects described the first film transistor source by the first described connecting hole; Described data wire is electrically connected described the first film transistor source and the grid of the second thin-film transistor by the second described connecting hole; This data wire is electrically connected described vdd line and the drain electrode of the second thin-film transistor by the 3rd described connecting hole; Described data wire connects the second described thin-film transistor source electrode by the 4th described connecting hole, and utilizes this data wire to described storage capacitance data writing voltage.
7. the manufacture method of thin-film transistor array base-plate according to claim 6, is characterized in that, described method is further comprising the steps of:
(8) on the second described metal level, grow organic film as planarization layer, in described hardware and software platform layer, on the position corresponding with the 4th described connecting hole, offer perforate, to expose the data wire of the source electrode that connects the second thin-film transistor.
8. the manufacture method of thin-film transistor array base-plate according to claim 7, is characterized in that, described step (8) specifically comprises the following steps:
(81) on the second described metal level, grow organic film as planarization layer;
(82) utilize developing method to remove being positioned at the locational part hardware and software platform layer that the 4th described connecting hole is corresponding, form the perforate of the data wire that exposes the source electrode that connects the second thin-film transistor.
9. according to the manufacture method of the thin-film transistor array base-plate described in claim 7 or 8, it is characterized in that, described method is further comprising the steps of:
(9) on described hardware and software platform layer, growth regulation three metal levels are as OLED anode, and the 3rd described metal level connects the second described thin-film transistor source electrode by described data wire.
10. the manufacture method of thin-film transistor array base-plate according to claim 6, is characterized in that, described step (3) specifically comprises the following steps:
(31) amorphous silicon layer of growing on the first described insulating barrier;
(32) make described amorphous silicon layer form polysilicon layer by Excimer-Laser Crystallization or thermal annealing method;
(33) the transistorized source electrode of the first film that the polysilicon layer described in patterning forms and the source electrode of the second thin-film transistor.
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| CN201410053576.4A CN103839915B (en) | 2014-02-17 | A kind of thin-film transistor array base-plate and manufacture method thereof | |
| JP2014123641A JP6098017B2 (en) | 2014-02-17 | 2014-06-16 | Thin film transistor array substrate and manufacturing method thereof |
| KR1020140088418A KR101671896B1 (en) | 2014-02-17 | 2014-07-14 | Thin film transistor array panel and method for manufacturing the same |
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| CN201410053576.4A CN103839915B (en) | 2014-02-17 | A kind of thin-film transistor array base-plate and manufacture method thereof |
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| CN103839915A true CN103839915A (en) | 2014-06-04 |
| CN103839915B CN103839915B (en) | 2016-11-30 |
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| KR20150097363A (en) | 2015-08-26 |
| JP6098017B2 (en) | 2017-03-22 |
| KR101671896B1 (en) | 2016-11-03 |
| JP2015154072A (en) | 2015-08-24 |
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Address after: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506 Patentee after: Shanghai Hehui optoelectronic Co., Ltd Address before: 201508, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee before: EverDisplay Optronics (Shanghai) Ltd. |