CN103839812A - Semiconductor device and method for preparing same - Google Patents
Semiconductor device and method for preparing same Download PDFInfo
- Publication number
- CN103839812A CN103839812A CN201210477217.2A CN201210477217A CN103839812A CN 103839812 A CN103839812 A CN 103839812A CN 201210477217 A CN201210477217 A CN 201210477217A CN 103839812 A CN103839812 A CN 103839812A
- Authority
- CN
- China
- Prior art keywords
- gate
- dummy gate
- layer
- material layers
- hard mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 147
- 239000007769 metal material Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 150000004767 nitrides Chemical class 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 229910052735 hafnium Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- WMFOQBRAJBCJND-UHFFFAOYSA-M Lithium hydroxide Chemical compound [Li+].[OH-] WMFOQBRAJBCJND-UHFFFAOYSA-M 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 150000005208 1,4-dihydroxybenzenes Chemical class 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a semiconductor device and a method for preparing the same. The method comprises the following steps: providing a semiconductor substrate; forming a gate dielectric layer on the substrate; forming a gate material layer and a hard mask layer on the gate dielectric layer; patterning the hard mask layer and part of the gate material layer to form the upper part of a virtual gate; forming a virtual spacer on the side wall of the upper part of the virtual gate; etching the remaining gate material layer to form the lower part of the virtual gate, wherein the key dimension of the lower part of the virtual gate is smaller than that of the upper part of the virtual gate; and removing the virtual spacer and the hard mask layer to form a virtual gate, and finally forming a metal gate. The method of the invention solves the problem existing in the prior art, and the process is simpler.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
Manufacture field at integrated circuit, along with constantly dwindling of MOS transistor, especially in the technique below 32nm, it is various because the second-order effect that the physics limit of device is brought is inevitable, the scaled difficulty that becomes of characteristic size of device, easily there is the electric leakage problem from grid to substrate in MOS transistor device and circuit thereof the field of manufacturing wherein.
The solution of current technique is the method that adopts high-K gate material and metal gate, first the forming process of metal current grid for forming gate oxide, gate dielectric layer and mask layer in Semiconductor substrate, to form lamination, then described in patterning, lamination forms dummy gate and forms clearance wall, then described dummy gate is removed in etching, then plated metal grid, described metal gates can comprise function metal level, barrier layer and metal material layer.
In current preparation method in rear grid technique (Gate-last), especially after high K in the high-k/metal gate technique of grid (high-k last), the filling of metal gate material is along with dwindling of grid well width becomes more and more difficult, in the time filling, be easy to cause and fill not exclusively, in grid structure, form space, performance during impact.In order to address this problem, prior art has report that metal material Ti soakage layer can be formed to larger overhang when the PVD, causes follow-up metal A l to be difficult to fill.After adopting Co soakage layer, this problem can be eased, but Co soakage layer is again a kind of new material for metal gate process, all brings very large difficulty for control and the metal gate CMP technique polluted.
Therefore, although prepare the common process comparative maturity of metal gates at present, but along with during further the dwindling of size, make in rear grid technique, in the time filling metal material, easily to cause and to fill not exclusively, in grid structure, form space, and the method addressing this problem in prior art can cause again other problem, so need to do further improvement to prior art, to can eliminate described problem, improve the performance of semiconductor device.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention is in order to overcome current existing problems, and a kind of preparation method of semiconductor device is provided, and comprising:
Semiconductor substrate is provided;
On described substrate, form gate dielectric;
On described gate dielectric, form gate material layers and hard mask layer;
The described gate material layers of hard mask layer and part described in patterning, to form the top of dummy gate;
On the sidewall on the top of described dummy gate, form virtual clearance wall;
Described in etching, remain gate material layers, to form the bottom of described dummy gate, the critical size of the bottom of described dummy gate is less than the top of described dummy gate;
Remove described virtual clearance wall and described hard mask layer, to form dummy gate, finally form metal gates.
As preferably, described method is further comprising the steps of:
On described dummy gate, form clearance wall, and carry out source leakage and inject, to form source-drain area;
On described source-drain area, deposit interlayer dielectric layer planarization, to expose the top of described dummy gate;
Remove described dummy gate deposit metallic material, then planarization, to form described metal gates.
As preferably, described method is further comprising the steps of:
Before forming described gate dielectric, in described substrate, form fleet plough groove isolation structure.
As preferably, described gate dielectric is oxide.
As preferably, Semiconductor substrate described in thermal oxidation, to form described gate dielectric.
As preferably, described gate material layers is polysilicon layer.
As preferably, the method for hard mask layer and the described gate material layers of part is described in patterning:
On described hard mask layer, form the photoresist layer of patterning, taking described photoresist layer as hard mask layer described in mask etch with the described gate material layers of part, to form the top of dummy gate.
As preferably, the method that forms the bottom of described dummy gate is:
Described in first anisotropic etching, gate material layers is to described gate dielectric, and then the gate material layers under virtual clearance wall described in isotropic etching, reduces its critical size, is less than the bottom of the dummy gate on the top of described dummy gate to form critical size.
As preferably,, the thickness of the described gate material layers of removal is 5-20nm when on the top of described formation dummy gate.
As preferably, the material of described hard mask layer and the material of described virtual clearance wall have etching selectivity.
As preferably, the bottom of described dummy gate is than the little 1-5nm of the critical size on the top of described dummy gate.
As preferably, the formation method of described metal gates is rear grid technique.
As preferably, the method that forms described metal gates is:
Remove described dummy gate and described gate dielectric, then deposition interface layer and high k dielectric layer, then deposit metallic material planarization.
The present invention also provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Metal gate structure, is positioned in described Semiconductor substrate, and described metal gates is structure wide at the top and narrow at the bottom;
Source-drain area, is positioned at described metal gate structure both sides.
As preferably, described metal gates comprises the first half and the latter half, and wherein the critical size of the first half is than the large 1-5nm of the critical size of the latter half.
As preferably, described metal gate structure comprises boundary layer, high k dielectric layer and metal material layer.
The invention provides a kind of new method that metal gate is filled that forms, wherein in the time forming described dummy gate, carry out at twice, etch for the first time the first half of wider dummy gate, then protect the wider dummy gate of the first half by virtual clearance wall, the latter half described in etching, to etch compared with hachure, make the critical size of the latter half of described dummy gate be less than the first half, thereby grid wide at the top and narrow at the bottom, to form larger opening, after larger opening described in forming, be conducive to the filling of hafnium layer below and metal material layer, can not cause hole and space, problems of the prior art are solved, and described technique is simpler.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Schematic diagram is prepared for semiconductor device of the present invention in Fig. 1-8;
Fig. 9 is semiconductor device preparation flow figure of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that semiconductor device of the present invention and preparation method thereof to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Preparation method below in conjunction with Fig. 1-8 pair semiconductor device of the present invention is described further:
With reference to Fig. 1, Semiconductor substrate 201 is provided, described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon-on-insulator (SOI), insulator can also form other active devices in this Semiconductor substrate.Preferred silicon-on-insulator (SOI) in the present invention, described silicon-on-insulator (SOI) comprises and is followed successively by from the bottom up support substrates, oxide insulating layer and semiconductor material layer, and the semiconductor material layer at wherein said top is monocrystalline silicon layer, polysilicon layer, SiC or SiGe.Have oxide insulating layer because SOI is made into below, device active region, this oxide insulating layer is embedded in semiconductor base layer, thereby makes device have more excellent performance, but is not limited to above-mentioned example.
Then on described substrate, form shallow trench isolation from 202, described shallow trench isolation can be selected method conventional in prior art from 202 formation method, for example first, forms successively the first oxide skin(coating) and the first nitride layer in Semiconductor substrate 201.Then, carry out dry etch process, successively the first nitride layer, the first oxide skin(coating) and Semiconductor substrate 201 are carried out to etching to form groove 202.Particularly, can on the first nitride layer, form the figuratum photoresist layer of tool, taking this photoresist layer as mask, the first nitride layer is carried out to dry etching, with by design transfer to the first nitride layer, and taking photoresist layer and the first nitride layer as mask, the first oxide skin(coating) and Semiconductor substrate 201 are carried out to etching, to form groove.Certainly can also adopt other method to form groove, think known in the artly due to this technique, therefore no longer be described further.
Then, in groove, fill shallow trench isolated material, to form the first sub-fleet plough groove isolation structure.Particularly, can on the first nitride layer He in groove, form shallow trench isolated material, described shallow trench isolated material can be silica, silicon oxynitride and/or other existing advanced low-k materials; Carry out chemical mechanical milling tech and stop on the first nitride layer, thering is fleet plough groove isolation structure to form.
Continue with reference to Fig. 2, on described substrate, form gate dielectric;
Particularly, described gate dielectric is oxide skin(coating) 203, particularly, can be silica (SiO2) or silicon oxynitride (SiON).Can adopt those skilled in the art's oxidation technology known such as furnace oxidation, rapid thermal annealing oxidation (RTO), original position steam oxidation (ISSG) etc. to form the gate dielectric layer of silica material.Silica is carried out to nitriding process and can form silicon oxynitride, wherein, described nitriding process can be high temperature furnace pipe nitrogenize, rapid thermal annealing nitrogenize or pecvd nitride, certainly, can also adopt other nitriding process, repeats no more here.Be preferably in the present invention silica (SiO2).
Then on described gate dielectric, form gate material layers 204 and hard mask layer 205;
Wherein, described gate material layers is monocrystalline silicon layer, polysilicon layer, SiC or SiGe, be preferably in the present invention silicon layer, described semiconductor material layer can be selected reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy and molecular beam epitaxy, in the present invention preferred selective epitaxy.
Wherein, described hard mask layer 205 is nitride layer, be preferably SiN, the one that the deposition process of described mask layer can select low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy of the formation such as chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method to grow in (SEG).
With reference to Fig. 2, hard mask layer and the described gate material layers of part described in patterning, to form the top of dummy gate;
Particularly, on described hard mask layer, form the photoresist layer of patterning, taking described photoresist layer as hard mask layer described in mask etch with the described gate material layers of part, to form the top of dummy gate, in this step, can select hard mask layer and described gate material layers described in dry etching, in described dry etching, can select CF
4, CHF
3, add in addition N
2, CO
2, O
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, etching period is 5-120s, is preferably 5-60s, more preferably 5-30s.
As preferably, the thickness of the gate material layers that etching is removed in this step is 5-20nm.
With reference to Fig. 3, on the sidewall on the top of described dummy gate, form virtual clearance wall 206;
Particularly, form the virtual clearance wall (spacer) 206 on the top that surrounds described dummy gate; Described virtual clearance wall can be a kind of in silica, silicon nitride, silicon oxynitride or they constitute.Optimize execution mode for one as the present embodiment, described virtual clearance wall is that silica, silicon nitride form jointly, concrete technology is: in Semiconductor substrate, form the first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer, then adopt engraving method to form clearance wall.
Described virtual clearance wall structure, comprises nitride, oxynitride or their combination, forms by deposition and etching.Virtual clearance wall structure can have different thickness, but starts to measure from basal surface, and the thickness of clearance wall structure is generally 10 to 30nm.
As example, in Semiconductor substrate, can also be formed with and be positioned at grid structure both sides and the clearance wall structure near grid structure.Wherein, clearance wall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.
With reference to Fig. 4, remain gate material layers described in etching, to form the bottom of described dummy gate, the critical size of the bottom of described dummy gate is less than the top of described dummy gate;
Particularly, top taking described dummy gate remains gate material layers as described in mask etch, described in first anisotropic etching, gate material layers is to described gate dielectric, then the gate material layers under virtual clearance wall described in isotropic etching, reduce its critical size, to form the bottom of described dummy gate, as preferably, the bottom of described dummy gate is than the little 1-5nm of the critical size on the top of described dummy gate.
Described high-K metal grid is divided into two parts in the present invention, wherein the critical size of the first half is greater than the critical size of described the latter half, to form larger opening, after larger opening described in forming, be conducive to the filling of hafnium layer below and metal material layer, can not cause hole and space, solve problems of the prior art.
Further, described anisotropic etching is selected alkaline wet etch in the present invention, described alkaline etching liquid can be KOH or EDP(ethylenediamine+hydroquinones+water), also have TMAH(Tetramethylammonium hydroxide), one or more in hydrazine, lithium hydroxide and ammoniacal liquor.The concentration of wherein said etching solution is 15-25%, and now, described gate material layers and described gate dielectric layer have larger etching selectivity.
Described isotropic etching can be selected pure chemistry reaction etching or additive method, does not repeat them here.
With reference to Fig. 5, remove described virtual clearance wall and described mask layer, to form dummy gate;
Particularly, can select in the present invention dry method or wet etching to remove described virtual clearance wall and described mask layer, wherein, the material of described hard mask layer and the material of described virtual clearance wall have etching selectivity.Therefore can remove in two sub-sections in the present invention described virtual clearance wall and described mask layer.
Remove the bottom of exposing described dummy gate after described virtual clearance wall and described mask layer, in conjunction with the top of described dummy gate, to form dummy gate.
With reference to Fig. 6, on described dummy gate, form clearance wall 207, and carry out source leakage and inject, to form source-drain area;
Particularly, form clearance wall 207 on described dummy gate, the formation method of described clearance wall can be with reference to the formation method of virtual clearance wall.
Then leak injection to carrying out source on described semiconductor material layer, the ionic type of injection is leaked in wherein said source and the concentration of doping all can be selected this area usual range.
The implant energy of selecting is in the present invention 2000ev-5kev, is preferably 500-100ev, to ensure that its doping content can reach 5E17 ~ 1E25 atom/cm
3.
As preferably, after leaking injection, source can also carry out annealing steps, particularly, carry out after described thermal anneal step, infringement on silicon chip can be eliminated, minority carrier lifetime and mobility can obtain recovery in various degree, and impurity also can obtain a certain proportion of activation, therefore can improve device efficiency.
Described annealing steps is generally that described substrate is placed under the protection of high vacuum or high-purity gas; being heated to certain temperature heat-treats; be preferably nitrogen or inert gas at high-purity gas of the present invention; the temperature of described thermal anneal step is 800-1200 DEG C, and the described thermal anneal step time is 1-200s.
As further preferred, can select in the present invention rapid thermal annealing, particularly, can select the one in following several mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent wideband light source (as halogen lamp, arc lamp, graphite heating) short annealing etc.Those skilled in the art can select as required, are also not limited to examples cited.
Continue with reference to Fig. 6, on described source-drain area, deposit interlayer dielectric layer 208 planarization, to expose the top of described dummy gate;
Described interlayer dielectric layer can be dielectric layer between metal layers 208, preferably formed by low dielectric constant dielectric materials, for example fluorine silex glass (FSG), silica (silicon oxide), carbonaceous material (carbon-containing material), porous material (porous-likematerial) or homologue.
Interlayer dielectric layer can be silicon oxide layer, comprise the material layer that has doping or unadulterated silica that utilizes thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process to form, silex glass (USG), phosphorosilicate glass (PSG) or the boron-phosphorosilicate glass (BPSG) of for example undoped.In addition, interlayer dielectric layer can be also spin cloth of coating-type glass (spin-on-glass, SOG), the tetraethoxysilane (PTEOS) of Doping Phosphorus or the tetraethoxysilane (BTEOS) of doped with boron of doped with boron or Doping Phosphorus.
Interlayer dielectric layer can use such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can use film having formed SiCN film etc. on fluorocarbon (CF).Fluorocarbon is taking fluorine (F) and carbon (C) as main component.Fluorocarbon also can use the material with noncrystal (amorphism) structure.Interlayer dielectric layer can also use the Porous structures such as such as carbon doped silicon oxide (SiOC).
With reference to Fig. 7-8, remove described dummy gate deposit metallic material, then planarization, to form metal gates;
Particularly, as shown in Figure 7, first remove dummy gate electrode, form groove.The method of described removal can be chemical etching.Gas used in etching process comprises HBr, and it is as main etching gas; Also comprise 02 or Ar as etching make-up gas, it can improve the quality of etching.
With reference to Fig. 8, then metal material, then planarization, to form metal gates, particularly, grid of the present invention is high-K metal grid HKMG(high-k insulating barrier+metal gates), the formation of described grid can be first grid (Gate-first) technique or rear grid (Gate-last) technique, while selecting in the present invention rear grid (Gate-last) technique, removes described dummy gate, then deposition interface layer and high k dielectric layer, then deposit metallic material planarization.
In one embodiment of this invention, described metal gates forms by the multiple film storehouses of deposition.Described film comprises merit boundary layer, hafnium layer and metal material layer.
Described hafnium forms described gate dielectric, for example, be used in hafnium that the ratio introducing the elements such as Si, Al, N, La, Ta in Hf02 and optimize each element obtains etc.The method of described formation gate dielectric can be physical gas-phase deposition or atom layer deposition process.In an embodiment of the present invention, on described SiO2 boundary layer, form HfAION gate dielectric, its thickness is 15 to 60 dusts.
Described metal material layer can deposit by the method for CVD or PVD.After this conductive layer forms, under 300-500 degree celsius temperature, anneal.It is 10-60 minute containing the time of reacting in nitrogen environment.Finally carry out the planarization of conductive layer, form metal gates to remove the conductive layer beyond groove.
The present invention also provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Metal gates, is positioned in described Semiconductor substrate, and described metal gates is structure wide at the top and narrow at the bottom;
Source-drain area, is positioned at described metal gates both sides.
Wherein, described metal gates comprises the first half and the latter half, and wherein the critical size of the first half is than the large 1-5nm of the critical size of the latter half.
The invention provides a kind of new method that metal gate is filled that forms, wherein in the time forming described dummy gate, carry out at twice, etch for the first time the first half of wider dummy gate, then protect the wider dummy gate of the first half by virtual clearance wall, the latter half described in etching, to etch compared with hachure, make the critical size of the latter half of described dummy gate be less than the first half, thereby grid wide at the top and narrow at the bottom, to form larger opening, after larger opening described in forming, be conducive to the filling of hafnium layer below and metal material layer, can not cause hole and space, problems of the prior art are solved, and described technique is simpler.
Fig. 9 is the process chart that the present invention prepares described semiconductor device, comprises the following steps:
Step 201 provides Semiconductor substrate;
Step 202 forms gate dielectric on described substrate;
Step 203 forms gate material layers and hard mask layer on described gate dielectric;
The described gate material layers of hard mask layer and part described in step 204 patterning, to form the top of dummy gate;
Step 205 forms virtual clearance wall on the sidewall on the top of described dummy gate;
Described in step 206 etching, remain gate material layers, to form the bottom of described dummy gate, the critical size of the bottom of described dummy gate is less than the top of described dummy gate;
Step 207 is removed described virtual clearance wall and described hard mask layer, to form dummy gate, finally forms metal gates.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a preparation method for semiconductor device, comprising:
Semiconductor substrate is provided;
On described substrate, form gate dielectric;
On described gate dielectric, form gate material layers and hard mask layer;
The described gate material layers of hard mask layer and part described in patterning, to form the top of dummy gate;
On the sidewall on the top of described dummy gate, form virtual clearance wall;
Described in etching, remain gate material layers, to form the bottom of described dummy gate, the critical size of the bottom of described dummy gate is less than the top of described dummy gate;
Remove described virtual clearance wall and described hard mask layer, to form dummy gate, finally form metal gates.
2. method according to claim 1, is characterized in that, described method is further comprising the steps of:
On described dummy gate, form clearance wall, and carry out source leakage and inject, to form source-drain area;
On described source-drain area, deposit interlayer dielectric layer planarization, to expose the top of described dummy gate;
Remove described dummy gate deposit metallic material, then planarization, to form described metal gates.
3. method according to claim 1, is characterized in that, described method is further comprising the steps of:
Before forming described gate dielectric, in described substrate, form fleet plough groove isolation structure.
4. method according to claim 1, is characterized in that, described gate dielectric is oxide.
5. method according to claim 1, is characterized in that, Semiconductor substrate described in thermal oxidation, to form described gate dielectric.
6. method according to claim 1, is characterized in that, described gate material layers is polysilicon layer.
7. method according to claim 1, is characterized in that, the method for hard mask layer and the described gate material layers of part is described in patterning:
On described hard mask layer, form the photoresist layer of patterning, taking described photoresist layer as hard mask layer described in mask etch with the described gate material layers of part, to form the top of dummy gate.
8. method according to claim 1, is characterized in that, the method that forms the bottom of described dummy gate is:
Described in first anisotropic etching, gate material layers is to described gate dielectric, and then the gate material layers under virtual clearance wall described in isotropic etching, reduces its critical size, is less than the bottom of the dummy gate on the top of described dummy gate to form critical size.
9. method according to claim 1, is characterized in that,, the thickness of the described gate material layers of removal is 5-20nm when on the top of described formation dummy gate.
10. method according to claim 1, is characterized in that, the material of described hard mask layer and the material of described virtual clearance wall have etching selectivity.
11. methods according to claim 1, is characterized in that, the bottom of described dummy gate is than the little 1-5nm of the critical size on the top of described dummy gate.
12. methods according to claim 1, is characterized in that, the formation method of described metal gates is rear grid technique.
13. methods according to claim 12, is characterized in that, the method that forms described metal gates is:
Remove described dummy gate and described gate dielectric, then deposition interface layer and high k dielectric layer, then deposit metallic material planarization.
14. 1 kinds of semiconductor device, comprising:
Semiconductor substrate;
Metal gate structure, is positioned in described Semiconductor substrate, and described metal gates is structure wide at the top and narrow at the bottom;
Source-drain area, is positioned at described metal gate structure both sides.
15. devices according to claim 14, is characterized in that, described metal gates comprises the first half and the latter half, and wherein the critical size of the first half is than the large 1-5nm of the critical size of the latter half.
16. devices according to claim 14, is characterized in that, described metal gate structure comprises boundary layer, high k dielectric layer and metal material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210477217.2A CN103839812A (en) | 2012-11-21 | 2012-11-21 | Semiconductor device and method for preparing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210477217.2A CN103839812A (en) | 2012-11-21 | 2012-11-21 | Semiconductor device and method for preparing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103839812A true CN103839812A (en) | 2014-06-04 |
Family
ID=50803199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210477217.2A Pending CN103839812A (en) | 2012-11-21 | 2012-11-21 | Semiconductor device and method for preparing same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103839812A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990113A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN107331769A (en) * | 2016-04-29 | 2017-11-07 | 上海磁宇信息科技有限公司 | A kind of method of the double-deck hard mask of reactive ion beam selective etch MTJ |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1819198A (en) * | 2004-12-31 | 2006-08-16 | 东部亚南半导体株式会社 | Semiconductor device and fabricating method thereof |
| CN101266972A (en) * | 2008-04-22 | 2008-09-17 | 北京大学 | Method for improving MOSFET anti-single particle radiation and MOSFET component |
| US20080265322A1 (en) * | 2007-04-24 | 2008-10-30 | Chin-Hsiang Lin | Metal oxide semiconductor transistor with y shape metal gate and fabricating method thereof |
| US20110079854A1 (en) * | 2009-10-02 | 2011-04-07 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN102104006A (en) * | 2011-01-17 | 2011-06-22 | 复旦大学 | Preparation method of field effect transistor |
| CN102479691A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Forming methods of metal gate and MOS (Metal Oxide Semiconductor) transistor |
-
2012
- 2012-11-21 CN CN201210477217.2A patent/CN103839812A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1819198A (en) * | 2004-12-31 | 2006-08-16 | 东部亚南半导体株式会社 | Semiconductor device and fabricating method thereof |
| US20080265322A1 (en) * | 2007-04-24 | 2008-10-30 | Chin-Hsiang Lin | Metal oxide semiconductor transistor with y shape metal gate and fabricating method thereof |
| CN101266972A (en) * | 2008-04-22 | 2008-09-17 | 北京大学 | Method for improving MOSFET anti-single particle radiation and MOSFET component |
| US20110079854A1 (en) * | 2009-10-02 | 2011-04-07 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN102479691A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Forming methods of metal gate and MOS (Metal Oxide Semiconductor) transistor |
| CN102104006A (en) * | 2011-01-17 | 2011-06-22 | 复旦大学 | Preparation method of field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990113A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN105990113B (en) * | 2015-01-30 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN107331769A (en) * | 2016-04-29 | 2017-11-07 | 上海磁宇信息科技有限公司 | A kind of method of the double-deck hard mask of reactive ion beam selective etch MTJ |
| CN107331769B (en) * | 2016-04-29 | 2020-10-27 | 上海磁宇信息科技有限公司 | Method for selectively etching double-layer hard mask of magnetic tunnel junction by reactive ion beam |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105428304B (en) | Semiconductor structure and method of forming isolation between fin structures of fin device | |
| CN102129978B (en) | Method of forming a semiconductor device | |
| KR101637853B1 (en) | Source/drain structure of semiconductor device | |
| KR101639483B1 (en) | Fin structure of semiconductor device | |
| JP5284594B2 (en) | DRAM (Dynamic Random Access Memory) cell | |
| US8765556B2 (en) | Method of fabricating strained structure in semiconductor device | |
| TW202004999A (en) | Semiconductor devices and methods for forming the same | |
| US9953878B2 (en) | Method of forming a semiconductor device | |
| WO2011124088A1 (en) | Gate stack structure, semiconductor device, and methods for manufacturing them | |
| CN102623318A (en) | Semiconductor device and manufacturing method thereof | |
| CN106373924A (en) | Semiconductor structure forming method | |
| CN103035712A (en) | Semiconductor device and method for manufacturing the same | |
| CN103390556A (en) | Semiconductor device manufacturing method | |
| CN104752215A (en) | Transistor forming method | |
| CN101980358B (en) | Method for fabricating an isolation structure | |
| CN104465376B (en) | Transistor and forming method thereof | |
| KR100634260B1 (en) | Method of forming a thin layer and method of forming a semiconductor device using the same | |
| CN112582265B (en) | Semiconductor structure and forming method thereof | |
| CN106847697B (en) | Method for forming fin field effect transistor | |
| CN103839812A (en) | Semiconductor device and method for preparing same | |
| CN103811420A (en) | Preparation method of semiconductor device | |
| TW201145388A (en) | Low temperature dielectric flow using microwaves | |
| CN103943492A (en) | Semiconductor device and preparation method thereof | |
| CN105789131A (en) | Semiconductor device and preparation method thereof and electronic device | |
| CN104051245A (en) | Preparation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140604 |
|
| RJ01 | Rejection of invention patent application after publication |