CN103824858B

CN103824858B - The anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor

Info

Publication number: CN103824858B
Application number: CN201210464622.0A
Authority: CN
Inventors: 苏庆; 王邦麟; 苗彬彬; 邓樟鹏
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2012-11-16
Filing date: 2012-11-16
Publication date: 2016-08-17
Anticipated expiration: 2032-11-16
Also published as: CN103824858A

Abstract

The invention discloses a kind of anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor, including: N-type protection from latch-up layer and p-type protection from latch-up layer are constituted, and N-type protection from latch-up layer is made up of N-type deep trap, n type buried layer, N trap, N-type diffusion region one or more of which；P-type protection from latch-up layer is made up of p-type deep trap, p type buried layer, p-well, p type diffusion region one or more of which；Wherein, N-type protection from latch-up layer and p-type protection from latch-up layer organize arrangement, in cross-shaped more.Compared with present invention bolt lock structure anti-with existing CMOS complementary metal-oxide-semiconductor, electrostatic protection cut-in voltage can be reduced, promote leakage current ability.

Description

The anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to a kind of CMOS complementary metal-oxide-semiconductor anti-breech lock knot Structure.

Background technology

On the chip of CMOS complementary metal-oxide-semiconductor technique, it will usually there is some p-types simultaneously and N-type is brilliant Body pipe (PMOS and NMOS).Therefore, between power line and earth lead, the P-N-P-N of some parasitisms must be there is Thyristor (Silicon-controlled rectifier, the SCR) device of structure (P+/NW/Psub/N+) Part.Breech lock has two kinds of current systems, and one is in I/O(input/output) inject positive current on pin, one be Negative current is injected on I/O pin.As it is shown on figure 3, by positive current inject trigger breech lock as a example by, thyristor be by Following structure forms, and receives the P+ diffusion region of VDD in (1) N trap；(2) N well region；(3) P type substrate or p-well region； (4) P type substrate or p-well region are connected to the N+ diffusion region of VSS.When parasitic thyristor is triggered conducting so that When parasitic NPN and PNP transistor carry out positive feedback, low-impedance state, even if trigger source (Trigger Source) is Being removed, parasitic thyristor still can maintain latch mode and cannot release voluntarily.Because of latch-up on chip The overcurrent (Over current) that lock causes tends to cause burning of device.The trigger source of thyristor is probably Overvoltage, overcurrent signal, change rapid voltage or current signal, or any abnormal state of affairs.

As it is shown in figure 1, prior art is to use N-type and p-type two-layer protection from latch-up layer, in one line, parallel two rows' Arrangement mode.Its protection mainly utilizes monolateral, and the protection of breech lock can be played certain effect by this kind of mode, but this Protection from latch-up structure is single, and the effective area of overcoat is limited, and its protective capacities is limited.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of complementation utilizing existing cmos device structure to realize electrostatic protection The anti-bolt lock structure of type metal oxide semiconductor, compared with bolt lock structure anti-with existing CMOS complementary metal-oxide-semiconductor, Electrostatic protection cut-in voltage can be reduced, promote leakage current ability.

For solving above-mentioned technical problem, the anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor of the present invention, including: N-type Protection from latch-up layer and p-type protection from latch-up layer are constituted, and N-type protection from latch-up layer is by N-type deep trap, n type buried layer, N trap, N-type Diffusion region one or more of which is constituted；P-type protection from latch-up layer is by p-type deep trap, p type buried layer, p-well, p type diffusion region One or more of which is constituted；Wherein, N-type protection from latch-up layer and p-type protection from latch-up layer organize arrangement, in decussation more Shape.

Wherein, described N-type protection from latch-up layer and P row protection from latch-up layer, its width is between 0.5um ~ 50um.

Wherein, the cross section length of described N-type protection from latch-up layer and p-type protection from latch-up layer 0.5um ~ 50um it Between.

Wherein, the distance between described N-type protection from latch-up layer and p-type protection from latch-up layer cross section is at 0.5um ~ 50um Between.

Inventive principle: in the case of not increasing more area, by changing the arrangement of protection from latch-up layer, increases anti- The lateralarea of the effective area protected, particularly overcoat, improves the protective capacities to breech lock with this.

The present invention, by changing the structure of protection from latch-up layer, reaches to improve the purpose of protection from latch-up ability.The present invention solves The protection question of latch-up in CMOS technology, by changing the structure of protection from latch-up layer, improves protection from latch-up further Ability.Compared with present invention bolt lock structure anti-with existing CMOS complementary metal-oxide-semiconductor, overcoat can be effectively increased Effective area, promote leakage current ability

Accompanying drawing explanation

The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:

Fig. 1 is existing CMOS complementary metal-oxide-semiconductor anti-bolt lock structure schematic diagram.

Fig. 2 is protection from latch-up structural representation of the present invention.

Fig. 3 is that positive current of the present invention injects the breech lock schematic diagram triggered.

Fig. 4 is that negative current of the present invention injects the breech lock schematic diagram triggered.

Description of reference numerals

A is N-type protection from latch-up layer

B is p-type protection from latch-up layer

VSS is ground connection

VDD is running voltage

A+ is positive current

A-is negative current

P+ is P+ expanding district

N+ is N+ diffusion region

PW is p-well

NW is N trap

IO PMOS is PMOS

IO NMOS is NMOS tube

PNP is parasitic PNP pipe

NPN is parasitic NPN pipe

Detailed description of the invention

The anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor of the present invention, including: N-type protection from latch-up layer and p-type breech lock are prevented Sheath is constituted；Wherein: N-type protection from latch-up layer can by the N-type deep trap of device, n type buried layer, N trap, N-type diffusion region its In one or more constitute；P-type protection from latch-up layer can be by the p-type deep trap of device, p type buried layer, p-well, p type diffusion region One or more of which is constituted；

As in figure 2 it is shown, wherein, N-type protection from latch-up layer and p-type protection from latch-up layer organize arrangement, in cross-shaped more.

N-type protection from latch-up layer and P row protection from latch-up layer, its width is between 0.5um ~ 50um, preferably 10um,20um,25.25um,30um,40um。

The cross section length of N-type protection from latch-up layer and p-type protection from latch-up layer is between 0.5um ~ 50um, preferably 10um,20um,25.25um,30um,40um。

Distance between described N-type protection from latch-up layer and p-type protection from latch-up layer cross section is excellent between 0.5um ~ 50um Select 10um, 20um, 25.25um, 30um, 40um.

Latched test has two kinds of current systems, and one is in I/O(input/output) inject positive current, Yi Zhongshi on pin I/O pin injects negative current.

As shown in Figure 3, Figure 4 as a example by CMOS complementary metal-oxide-semiconductor, when injecting positive current, positive current (A+) Enter the drain electrode (P+ diffusion region) of IO PMOS, trigger PNP parasitic for PMOS and open (by the drain electrode of IO PMOS, N Trap and p-well are constituted), current direction PW (p-well), and from the source-drain electrode of its ground connection, (N+ spreads through IO NMOS area District) flow out, along with the raising of positive current, raise the current potential of PW, the source-drain electrode 0.7V higher than NMOS triggers NPN and opens Open (by the N+ diffusion region in N trap, p-well and p-well, the i.e. drain electrode of IO NMOS or source electrode), ultimately form breech lock.And The p-type overcoat added between NMOS and PMOS can collect the electric current that major part comes from PNP, thus prevents NPN Unlatching.

When injecting negative current, negative current (A-) enters the drain electrode (N+ diffusion region) of IO NMOS, triggers NMOS parasitic NPN open, electronics flows to NW (N trap), and (P+ spreads to connect the source-drain electrode of VDD through IO PMOS area from it District) flow out, along with the raising of negative current, drag down the current potential of NW, the source-drain electrode 0.7V less than PMOS triggers PNP and opens Open, ultimately form breech lock.And the N-type overcoat added between NMOS and PMOS can be collected major part and come from NPN Electronics, thus prevent the unlatching of PNP.

Above by detailed description of the invention and embodiment, the present invention is described in detail, but these have not been constituted this The restriction of invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and changes Entering, these also should be regarded as protection scope of the present invention.

Claims

1. the anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor, including: N-type protection from latch-up layer and p-type breech lock are prevented Sheath is constituted, and N-type protection from latch-up layer is arranged in N trap by N-type deep trap, n type buried layer, N trap, N-type diffusion region wherein One or more are constituted；P-type protection from latch-up layer is arranged in p-well by p-type deep trap, p type buried layer, p-well, p-type diffusion District's one or more of which is constituted；It is characterized in that: N-type protection from latch-up layer and p-type protection from latch-up layer organize arrangement, in ten more Word cross-like.

2. the anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor as claimed in claim 1, is characterized in that: described N-type Protection from latch-up layer and P row protection from latch-up layer, its width is between 0.5um～50um.

3. the anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor as claimed in claim 1, is characterized in that: described N-type The cross section length of protection from latch-up layer and p-type protection from latch-up layer is between 0.5um～50um.

4. the anti-bolt lock structure of CMOS complementary metal-oxide-semiconductor as claimed in claim 1, is characterized in that: described N-type Distance between protection from latch-up layer and p-type protection from latch-up layer cross section is between 0.5um～50um.