CN103824765B - Grid side wall imaging method - Google Patents
Grid side wall imaging method Download PDFInfo
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- CN103824765B CN103824765B CN201310616217.0A CN201310616217A CN103824765B CN 103824765 B CN103824765 B CN 103824765B CN 201310616217 A CN201310616217 A CN 201310616217A CN 103824765 B CN103824765 B CN 103824765B
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- side wall
- grid
- semiconductor structure
- wall
- polycrystalline carbon
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- 238000003384 imaging method Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 claims abstract description 73
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 16
- 239000001301 oxygen Substances 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract 1
- 238000009832 plasma treatment Methods 0.000 abstract 1
- 239000011800 void material Substances 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000011049 filling Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 oxonium ion Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H01L29/401—
-
- H01L29/6656—
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a grid side wall imaging method. The method comprises the steps that a semiconductor structure which has a grid and a first side wall which covers the side wall of the grid is provided; a polycrystalline carbon layer is prepared to cover the surface of the semiconductor structure; the polycrystalline carbon layer is partially removed, so that a second side wall of the grid is formed on the surface of the first side wall; after a source drain implantation process is carried out on the semiconductor structure, the second side wall is removed; and a source drain annealing technology is continued. According to the grid side wall imaging method provided by the invention, through oxygenated plasma treatment, a polycrystalline carbon side wall which is used as a main side wall can be neatly removed; without using an SPT process which needs to be carried out in a specific etching cavity, the problem of void in a high stress through hole etching stop layer process can be solved; a process flow is simplified; and the production cost is reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of patterned method of grid curb wall.
Background technology
In semiconductor development process, an integrated circuit（Integrated circuit, abbreviation IC）Frequently include
Up to a million electronic devices, and the application requirement of the development and continuous lifting with technique, integrated circuit is to miniaturization, multilayer
Change, planarization, slimming development, and in ultra-large integrated circuit, only on several millimeters of silicon chips of square it is integrated it is up to ten thousand extremely
Million transistors.
And with the further diminution of device size, the requirement of its manufacturing process also is subjected to significant challenge.So, partly leading
Introduced successively in body manufacturing process comprising heavily stressed via etch stop-layer（CESL）, high k/metal gate and
The new techniques such as ultra low k, to improve the performance of device, meet the development of semiconductor technology.
Wherein, the filling of silicon nitride is an important challenge in semiconductor technology in CESL techniques.Because CESL works
Skill has certain requirement to the thickness of silicon nitride film, and thickness is too thin, and stress will be reduced, so as to have influence on the performance of device.
But, when the thickness of silicon nitride film is thicker, its is seamless filled, and certain difficulty occurs, produces cavity, and cavity is follow-up
Serious problem can be caused in technique.Therefore, now with the development of technology, generate silica（Or nitridation
Silicon）The technique that side wall is removed first（SPT）, the packing space of silicon nitride can be so expanded, so as to obtain seamless filling.But
It is that the current SPT techniques specific etch chamber of needs can just be carried out, so as to increased production cost.
Chinese patent（Publication number：CN101483154A）A kind of grid curb wall manufacture method of dual gate oxide device is disclosed,
Dual gate oxide device has thick, thin grid oxygen metal-oxide-semiconductor, and the grid curb wall includes thick, thin grid oxygen side wall, and it is produced in thick, thin grid
Oxygen grid both sides, wherein, the thick grid oxygen side wall includes bias internal side wall and external wall.The grid of dual gate oxide device in the prior art
Side wall is not used bias internal side wall, and causes the leakage current and grid of thick grid oxygen metal-oxide-semiconductor larger with the electric capacity of source and drain interpolar,
And cause the electrical property of the dual gate oxide device to deteriorate.The invention first deposits the first side wall medium layer and removes thin grid oxygen metal-oxide-semiconductor pair
First side wall medium layer of the active area answered；Bias internal side wall is formed by dry etching again；Then lightly doped drain injection is carried out
Technique；Finally deposit the second side wall medium layer and the external wall of thin grid oxygen side wall and thick grid oxygen side wall is formed by dry etching.
The invention can reduce the leakage current and its grid of thick grid oxygen metal-oxide-semiconductor and the electric capacity of source and drain interpolar, and can improve dual gate oxide device
Electrical property.
Chinese patent（Publication number：CN102437039A）A kind of uniform deposition silicon nitride is disclosed to form the side of side wall
Method, the method forms nitrogen according to silicon chip surface figure line width and the thickness requirement of required silicon nitride film, gradation deposited silicon nitride
SiClx film, comprises the following steps：1) above the grid structure of silicon chip surface and its both sides deposited silicon nitride formed silicon nitride
Film；2) silicon nitride film is bombarded with inert gas ion or oxonium ion, to homogenize the silicon nitride film；Repeat step 1)
With step 2), until silicon nitride film thickness reaches required requirement, etching forms side wall.The method of the present invention can be opened small
The silicon nitride sealing formed in the processing procedure of linewidth requirements, continues to be easy to reach the uniformity of side wall thicknesses during deposited silicon nitride；Should
Method will not remove the silicon nitride of the sealing bottom while silicon nitride sealing is opened, so as to not interfere with the heavy of silicon nitride
Product effect.
Above-mentioned two pieces patent is not solved in the prior art to solve the nitrogen in heavily stressed via etch stop layer process
SiClx film is too thick and producing may cause the cavity of serious problems in subsequent technique, and silica is removed using SPT techniques
Or the master wall of silica material can expand the packing space of silicon nitride and solve empty problem, but due to current
The specific etch chamber of SPT techniques needs can just be carried out, and then cause technological process complication and the increased problem of production cost.
The content of the invention
For above-mentioned problem, the invention discloses a kind of patterned method of grid curb wall, to overcome existing skill
Being produced for the silicon nitride film in the heavily stressed via etch stop layer process of solution is too thick in art may in subsequent technique
Cause the cavity of serious problems, the master wall for removing silica or silica material using SPT techniques can expand nitridation
The packing space of silicon and solve empty problem, but can just be carried out because current SPT techniques need specific etch chamber, and then
Cause technological process complication and the increased problem of production cost.
To achieve these goals, the present invention is adopted the following technical scheme that：
A kind of patterned method of grid curb wall, comprises the following steps：
S1, there is provided one has grid and covers the semiconductor structure of the first side wall of the gate lateral wall；
S2, prepares the surface that polycrystalline carbon-coating covers the semiconductor structure；
S3, partly removes the polycrystalline carbon-coating, with the second side that the grid is formed on the surface of first side wall
Wall；
S4, after continuation carries out source and drain injection technology to the semiconductor structure, removes second side wall；
S5, continues the annealing process of source and drain.
The above-mentioned patterned method of grid side wall, wherein, in the step S1, the semiconductor structure also has shallow ridges
Groove is isolated（STI, shallow trench isolation）, the grid include polysilicon gate and gate oxide.
The above-mentioned patterned method of grid side wall, wherein, in the step S2, the polycrystalline carbon-coating covers the grid
Roof, the surface of first side wall, shallow trench isolation surface and the exposed surface of the semiconductor structure.
The above-mentioned patterned method of grid side wall, wherein, in the step S2, the thickness of the polycrystalline carbon-coating is 100-
600 angstroms.
The above-mentioned patterned method of grid side wall, wherein, the step S3 is refined as：
S301, partly removes the polycrystalline carbon-coating, with forming the second of the grid on the surface of first side wall
Side wall, second side wall is polycrystalline carbon side wall；
S302, continuation carries out wet-cleaning to the semiconductor structure.
The above-mentioned patterned method of grid side wall, wherein, the step S4 is specifically, continue to the semiconductor structure source
After leakage injection technology, second side wall is removed with oxygen containing plasma.
The above-mentioned patterned method of grid side wall, wherein, in the step S5, the temperature of the annealing process is 950-
1100℃。
The above-mentioned patterned method of grid side wall, wherein, first side wall is offset side wall, based on second side wall
Side wall.
The above-mentioned patterned method of grid side wall, wherein, the thickness of first side wall is 1-20 angstroms.
The above-mentioned patterned method of grid side wall, wherein, also including, S6, continuation carries out high answering to the semiconductor structure
The via etch stop layer process of power.
Foregoing invention has the following advantages that or beneficial effect：
The patterned method of grid side wall of the invention, can neatly be removed and be used as very much by oxygen containing corona treatment
The polycrystalline carbon side wall of master wall, and need not be using the SPT techniques that need to can be just carried out in specific etch chamber, you can to solve high answering
Empty problem in the via etch stop layer process of power, so as to simplify technological process, reduces production cost.
Specific brief description of the drawings
By the detailed description made to non-limiting example with reference to the following drawings of reading, the present invention and its feature, outward
Shape and advantage will become more apparent.Identical mark indicates identical part in whole accompanying drawings.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is show purport of the invention.
Fig. 1-Fig. 5 is the flowage structure schematic diagram of the patterned embodiment of the method one of grid side wall of the present invention.
Wherein, 1 is semiconductor structure；2 is grid；21 is polysilicon gate；22 is gate oxide；3 is shallow trench isolation；4
It is the first side wall；5 is polycrystalline carbon-coating；51 is the second side wall.
Specific embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as limit of the invention
It is fixed.
Embodiment one：
As Figure 1-5, this implementation is related to a kind of patterned method of grid curb wall, comprises the following steps：
S1, there is provided one has grid 2 and covers the semiconductor structure 1 of the first side wall 4 of the side wall of grid 2, semiconductor
Structure 1 also has shallow isolating trough 3（STI, shallow trench isolation）, grid 2 include polysilicon gate 21 and grid oxygen
Change layer 22.
S2, prepares the surface that polycrystalline carbon-coating 5 covers semiconductor structure 1, and polycrystalline carbon-coating 5 covers roof, first side of grid 2
The surface of wall 4, the surface and the exposed surface of semiconductor structure 1 of shallow trench isolation 3.
S3, part removes polycrystalline carbon-coating 5, with the second side wall 51 that grid 2 is formed on the surface of the first side wall 4, i.e., right
Polycrystalline carbon-coating 5 is performed etching, and to form the second side wall of grid 2, i.e. polycrystalline carbon side wall, semiconductor structure 1 is entered afterwards
Row wet-cleaning forms residue after the second side wall 51 to remove a part for etches polycrystalline carbon-coating 5 on semiconductor structure,
In order to the carrying out of the source and drain injection technology in step S4；
S4, after continuing to the semiconductor structure source and drain injection technology, the second side wall 51 is removed with oxygen containing plasma.
S5, proceeds the annealing process of source and drain, and the temperature of annealing process is 950-1100 DEG C.
S6, continuation carries out heavily stressed via etch stop layer process to semiconductor structure.
Wherein, in the step S2, polycrystalline carbon-coating 5 can be formed using depositional modes such as chemical vapor depositions, because
Polycrystalline carbon has good guarantor's type spreadability, and the guarantor's type of polycrystalline carbon-coating 5 covering semiconductor structure 1, i.e. guarantor's type covers the top of grid 2
Wall, the surface of the first side wall 4, the surface and the exposed surface of semiconductor structure 1 of shallow trench isolation 3；First side wall 4 is skew
Side wall, its thickness is 1-20 angstroms, and the thickness of polycrystalline carbon-coating 5 is that 100-600 angstroms, the i.e. thickness of the second side wall are 100-600 angstroms, the
Two side walls are main side wall, because of offset side wall very thin thickness, so not interfering with the nothing of heavily stressed via etch stop layer process
Seam filling, therefore only need to remove thicker master wall, i.e. polycrystalline carbon side wall with oxygen containing plasma, you can solve heavily stressed
Empty problem in via etch stop layer process, and need not be using the SPT techniques that need to can be just carried out in specific etch chamber.
Additionally, the technique not being described in detail in the present embodiment can take the technique that same purpose is played in this area.
In sum, using the patterned method of grid curb wall of the invention, using the removal of oxygen containing plasma as main
The polycrystalline carbon side wall of side wall, can effectively solve the empty problem in heavily stressed via etch stop layer process, and need not adopt
With the SPT techniques that need to can be just carried out in specific etch chamber, so as to simplify technological process, production cost is reduced.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
The change case is realized, be will not be described here.Such change case has no effect on substance of the invention, not superfluous herein
State.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundation
Technical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of technical scheme protection.
Claims (6)
1. a kind of patterned method of grid curb wall, it is characterised in that comprise the following steps：
S1, there is provided one has grid and covers the semiconductor structure of the first side wall of the gate lateral wall, the semiconductor structure
Also isolate with shallow trench, the grid includes polysilicon gate and gate oxide；
S2, prepares the surface that polycrystalline carbon-coating covers the semiconductor structure, and the polycrystalline carbon-coating covers roof, the institute of the grid
State surface, the surface and the exposed surface of the semiconductor structure of shallow trench isolation of the first side wall；S3, part removes described
Polycrystalline carbon-coating, with the second side wall that the grid is formed on the surface of first side wall；
The step S3 is refined as：
S301, partly removes the polycrystalline carbon-coating, with the second side wall that the grid is formed on the surface of first side wall,
Second side wall is polycrystalline carbon side wall；
S302, continuation carries out wet-cleaning to the semiconductor structure；
S4, after continuation carries out source and drain injection technology to the semiconductor structure, removes second side wall；
S5, continues the annealing process of source and drain.
2. the patterned method of grid curb wall as claimed in claim 1, it is characterised in that described many in the step S2
The thickness of brilliant carbon-coating is 100-600 angstroms.
3. the patterned method of grid curb wall as claimed in claim 1, it is characterised in that the step S4 is specifically, continue
After carrying out source and drain injection technology to the semiconductor structure, second side wall is removed with oxygen containing plasma.
4. the patterned method of grid curb wall as claimed in claim 1, it is characterised in that described to move back in the step S5
The temperature of ignition technique is 950-1100 DEG C.
5. the patterned method of grid curb wall as claimed in claim 1, it is characterised in that first side wall is skew side
Wall, second side wall is main side wall.
6. the patterned method of grid curb wall as claimed in claim 1, it is characterised in that the thickness of first side wall is 1-
20 angstroms.
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| CN201310616217.0A CN103824765B (en) | 2013-11-26 | 2013-11-26 | Grid side wall imaging method |
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| CN201310616217.0A CN103824765B (en) | 2013-11-26 | 2013-11-26 | Grid side wall imaging method |
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| CN103824765B true CN103824765B (en) | 2017-05-17 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623343A (en) * | 2012-03-14 | 2012-08-01 | 上海华力微电子有限公司 | Side wall hollow layer structure for semiconductor device and preparation method for side wall hollow layer structure |
| CN103325728A (en) * | 2013-06-04 | 2013-09-25 | 上海华力微电子有限公司 | Air gap forming method |
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| US8080443B2 (en) * | 2008-10-27 | 2011-12-20 | Sandisk 3D Llc | Method of making pillars using photoresist spacer mask |
| CN102610646B (en) * | 2012-03-14 | 2015-01-07 | 上海华力微电子有限公司 | Side wall cavity layer structure of semiconductor device and method for preparing side wall cavity layer structure |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623343A (en) * | 2012-03-14 | 2012-08-01 | 上海华力微电子有限公司 | Side wall hollow layer structure for semiconductor device and preparation method for side wall hollow layer structure |
| CN103325728A (en) * | 2013-06-04 | 2013-09-25 | 上海华力微电子有限公司 | Air gap forming method |
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