CN103811493B - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
- Publication number
- CN103811493B CN103811493B CN201310164907.7A CN201310164907A CN103811493B CN 103811493 B CN103811493 B CN 103811493B CN 201310164907 A CN201310164907 A CN 201310164907A CN 103811493 B CN103811493 B CN 103811493B
- Authority
- CN
- China
- Prior art keywords
- nmos
- grid structure
- drain
- region
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 16
- 238000002513 implantation Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 12
- 238000002425 crystallisation Methods 0.000 claims description 10
- 230000008025 crystallization Effects 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 239000002552 dosage form Substances 0.000 claims description 2
- -1 oxidationSilicon Inorganic materials 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 39
- 125000006850 spacer group Chemical group 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 241001139376 Allas Species 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- 101150053888 allA gene Proteins 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910015890 BF2 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052689 Holmium Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052765 Lutetium Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- 229910052775 Thulium Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
本发明公开了半导体器件及其形成方法。一种半导体器件包括具有第一阈值电压的第一NMOS器件和具有第二阈值电压的第二NMOS器件。第一NMOS器件包括位于半导体衬底上方的第一栅极结构、位于半导体衬底中并且邻近于第一栅极结构的相对边缘的第一源极/漏极(S/D)区域。第一S/D区域不包含位错。第二NMOS器件包括位于半导体衬底上方的第二栅极结构、位于半导体衬底中并且邻近于第二栅极结构的相对边缘的第二S/D区域和位于第二S/D区域中的位错。
Description
技术领域
本发明涉及半导体器件及其形成方法。
背景技术
半导体集成电路(IC)产业经历了快速发展。在IC发展过程中,功能密度(即,每芯片面积上互连器件的数量)通常增加了而几何尺寸(即,使用制造工艺可以做出的最小的元件(或线))降低了。通常这种按比例缩小工艺通过提高生产效率和降低相关成本而带来益处。这种按比例缩小的工艺也增大了加工和制造IC的复杂性,并且为了实现这些进步,在IC制造方面也需要类似的发展。
例如,随着将半导体器件(诸如金属氧化物半导体场效应晶体管(MOSFET))按比例缩小至各个技术节点,已经实现了将应变的源极/漏极部件(例如,应激源区)用于增加载流子迁移率以及提高器件性能。虽然用于形成IC器件的应激源区的现有方法大体上足以实现它们的预期用途,但在各方面仍不是完全令人满意的。
发明内容
为了解决现有技术中存在的问题,根据本发明的一方面,提供了一种半导体器件,包括:第一NMOS器件,具有第一阈值电压,所述第一NMOS器件包括:第一栅极结构,位于半导体衬底上方;第一源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第一栅极结构的相对边缘,其中,所述第一S/D区域不包含位错;以及第二NMOS器件,具有第二阈值电压,所述第二NMOS器件包括:第二栅极结构,位于所述半导体衬底上方;第二S/D区域,位于所述半导体衬底中并且邻近于所述第二栅极结构的相对边缘;和位错,位于所述第二S/D区域中。
所述的器件还包括:位于所述半导体衬底上方的PMOS栅极结构;位于所述半导体衬底中并且邻近于所述PMOS栅极结构的相对边缘的第三S/D区域;以及位于所述第三S/D区域中的外延生长的部件。在一个实施例中,所述外延生长的部件是外延SiGe。在另一个实施例中,所述第三S/D区域不包含位错。
在所述的器件中,所述位错的深度在约10纳米至约150纳米的范围内。
在所述的器件中,所述第一阈值电压大于所述第二阈值电压。
在所述的器件中,所述第一NMOS器件包括标准阈值电压晶体管(SVT)和/或高阈值电压晶体管(HVT)。
在所述的器件中,所述第二NMOS器件包括低阈值电压晶体管(LVT)和/或超低阈值电压晶体管(uLVT)。
在所述的器件中,所述第二S/D区域包含的种类为Si、Ge、Ar、Xe、C、BF2、As、In或他们的组合。
在所述的器件中,所述第一NMOS器件的漏电流小于所述第二NMOS器件的漏电流。
在所述的器件中,所述第一NMOS器件的运行速度小于所述第二NMOS器件的运行速度。
根据本发明的另一方面,提供了一种半导体器件,包括:第一NMOS器件,所述第一NMOS器件包括:第一栅极结构,位于半导体衬底上方;和第一源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第一栅极结构的相对边缘,其中,所述第一S/D区域不包含位错;第二NMOS器件,所述第二NMOS器件包括:第二栅极结构,位于所述半导体衬底上方;第二S/D区域,位于所述半导体衬底中并且邻近于所述第二栅极结构的相对边缘;和位错,位于所述第二S/D区域中,其中,所述第一NMOS器件的阈值电压大于所述第二NMOS器件的阈值电压;以及PMOS器件,所述PMOS器件包括:第三栅极结构,位于所述半导体衬底上方;和第三源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第三栅极结构的相对边缘,其中,所述第三S/D区域不包含位错。
在所述的器件中,所述第三S/D区域包括外延生长的部件。
在所述的器件中,所述第二S/D区域包含的种类为硅(Si)或锗(Ge)。
在所述的器件中,所述位错是沿着<111>方向形成的。
根据本发明的又一方面,提供了一种制造半导体器件的方法,包括:在衬底上方形成第一NMOS栅极结构和第二NMOS栅极结构;在所述第一NMOS栅极结构上方形成保护件;在邻近于所述第二NMOS栅极结构的衬底中形成非晶化区域;在所述第一NMOS栅极结构和所述第二NMOS栅极结构上方沉积应力膜;实施退火工艺以在邻近于所述第二NMOS栅极结构的衬底中形成位错;以及去除所述应力膜。
在所述的方法中,所述应力膜是氮化硅、氧化硅、氮氧化硅或他们的组合。
在所述的方法中,采用注入工艺以约1×1014原子/cm2至约2×1015原子/cm2的注入剂量形成所述非晶化区域。
在所述的方法中,通过快速热退火(RTA)工艺在约400℃至约750℃的温度下,在约10秒至约5分钟的时间段内实施所述退火工艺。
在所述的方法中,用于形成所述位错的工艺是通过尖峰热退火(尖峰RTA)工艺在约900℃至约1050℃的温度下,在约0.1秒至约2秒的时间段内实施的退火工艺。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,对各种部件没有被按比例绘制并且仅用于说明的目的。实际上,为了清楚的论述,各种部件的尺寸可以被任意增大或减小。
图1是示出根据本发明的各方面形成半导体器件的方法的流程图。
图2至图6是根据一个或多个实施例的在按照图1的方法制造的各个阶段的半导体器件的横截面侧视图。
具体实施方式
为了实施本发明的不同部件,以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不打算用于限定。例如,在以下描述中第一部件在第二部件上方或者在第二部件上的形成可以包括其中第一部件和第二部件以直接接触形成的实施例,并且也可包括其中在第一部件和第二部件之间形成额外的部件,使得第一部件和第二部件可以不直接接触的实施例。另外,本发明可能在各个实例中重复附图编号和/或字母。这种重复是为了简明和清楚的目的且其本身并没有表明所论述的各个实施例和/或结构之间的关系。可以理解,本领域技术人员能够想出尽管在本文中没有明确描述但是体现了本发明原理的各种等效物。
从本发明的一个或多个实施例可以受益的器件的实例是具有场效应晶体管(FET)的半导体器件。这种器件例如是互补金属氧化物半导体(CMOS)场效应晶体管。以下公开内容将继续该实例以说明本申请的各个实施例。然而,可以理解,除非明确说明,本申请应当不限于具体类型的器件。
参照图1和图2至图6,在下面一起描述方法100和半导体器件200。半导体器件200是指集成电路或集成电路的一部分,其可以包括有源器件,诸如金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、高电压晶体管和/或高频晶体管、其他合适的元件、和/或他们的组合。另外,半导体器件200可以包括无源器件,诸如电阻器、电容器、电感器和/或熔丝。可以理解,可以通过CMOS技术加工形成半导体器件200,并因此在本文中对一些工艺不进行详细描述。可以在方法100之前、期间或之后提供其他步骤,并且对于方法的其他实施例,下面描述的一些步骤可以被替换或去除。此外,还可以理解,可以在半导体器件200中增加其他部件,并且对于半导体器件200的其他实施例,下面描述的一些部件可以被替换或去除。
参照图1,根据本发明的各方面描述了制造半导体器件的方法100。方法100开始于步骤102,其中在衬底上方形成第一NMOS栅极堆叠件、第二NMOS栅极堆叠件和PMOS栅极堆叠件。方法100继续至步骤104,其中对衬底实施预非晶化注入(PAI)工艺。方法100继续至步骤106,其中在衬底上方沉积应力膜。方法100继续至步骤108,其中对衬底实施退火工艺。方法100继续至步骤110,其中从衬底去除应力膜。下面的论述举例说明了可以根据图1的方法100制造的半导体器件200的各个实施例。
图2至图6是根据图1的方法100在各个制造阶段的半导体器件200的横截面侧视图。参照图1和图2,方法100开始于步骤102,其中在衬底202上方形成第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260。第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260中的每一个都限定出其下方的衬底202的沟道区域。在本实施例中,保存第一NMOS栅极堆叠件240用于形成具有低漏电流的NMOS器件。具有低漏电流的NMOS器件例如包括具有标准阈值电压(例如,0.3伏特)的标准阈值电压晶体管(SVT)和/或具有高阈值电压(例如,0.4伏特)的高阈值电压晶体管(HVT)。在本实施例中,保存第二NMOS栅极堆叠件250用于形成具有高运行速度的NMOS器件。具有高运行速度的NMOS器件例如包括具有低阈值电压(例如,0.2伏特)的低阈值电压晶体管(LVT)和/或具有更低阈值电压(例如,<0.2伏特)的超低阈值电压晶体管(uLVT)。
在本实施例中,衬底202是包含硅的半导体衬底。在一些可选的实施例中,衬底202包括元素半导体,包括晶体形式的硅和/或锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或他们的组合。当衬底202是合金半导体时,合金半导体衬底可以具有梯度SiGe部件,其中Si和Ge组成从梯度SiGe部件的一个位置的一个比值变化到另一位置的另一比值。可以在硅衬底上方形成合金SiGe,和/或SiGe衬底可以是应变的。在又一可选的实施例中,半导体衬底可以是绝缘体上半导体(SOI)。
如本领域中公知的,根据设计要求,衬底202包括各种掺杂区域(例如,p型阱或n型阱)。掺杂区域掺杂有p型掺杂物,诸如硼或BF2;和/或n型掺杂物,诸如磷或砷。可以直接在衬底202上、P阱结构中、N阱结构中、双阱结构中,或者使用凸起结构形成掺杂区域。在一些实施例中,衬底202包括隔离部件204以限定并隔离衬底202的各个有源区域。隔离部件204利用诸如浅沟槽隔离(STI)或硅的局部氧化(LOCOS)的隔离技术来限定并电隔离各个区域。隔离部件204包含氧化硅、氮化硅、氮氧化硅、其他合适的材料或他们的组合。
仍参照图2,在一些实施例中,通过在衬底202上相继沉积并图案化栅极介电层206、栅电极层208和硬掩模层210形成第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260。在一个实例中,栅极介电层206是包含氧化硅、氮化硅、氮氧化硅、高k电介质、其他合适的介电材料或他们的组合的薄膜。高k电介质包括金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及其混合物的氧化物。在本实施例中,栅极介电层206是厚度在约10埃至约30埃范围内的高k介电层。可以采用合适的工艺诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV臭氧氧化或他们的组合形成栅极介电层206。栅极介电层206还可以包括界面层(未示出),该界面层用于减少栅极介电层206和衬底202之间的损伤。界面层可以包含氧化硅。
然后在栅极介电层206上形成栅电极层208。在一些实施例中,栅电极层208包括单层结构或多层结构。在本实施例中,栅电极层208包含多晶硅。此外,栅电极层208可以是具有相同或不同掺杂种类的掺杂多晶硅。在一个实施例中,栅电极层208的厚度在约30nm至约60nm的范围内。可以采用诸如低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、其他合适的工艺或他们的组合的工艺形成栅电极层208。然后,在栅电极层208上方形成硬掩模层210,以及在硬掩模层210上形成图案化的感光层(未示出)。将感光层的图案转印到硬掩模层210,然后转印到栅电极层208和栅极介电层206以形成第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260。在一些实施例中,硬掩模层210包含氧化硅。在可选的实施例中,硬掩模层210包含氮化硅、氮氧化硅和/或其他合适的介电材料,并且可以采用诸如CVD或PVD的方法形成。硬掩模层210的厚度在约100埃至约800埃的范围内。然后通过干法和/或湿法剥离工艺去除感光层。
进一步参照图2,邻接第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260的相对侧壁形成侧壁间隔件(或被称为栅极间隔件)212。在一些实施例中,侧壁间隔件212包括单层结构或多层结构。在本实施例中,通过沉积工艺包括CVD、PVD、ALD或其他合适的技术在NMOS栅极堆叠件240、PMOS栅极堆叠件250和衬底202上方形成间隔件材料覆盖层(未示出)。在一些实施例中,间隔件材料包括氧化硅、氮化硅、氮氧化硅、其他合适的材料或他们的组合。在一些实施例中,沉积的间隔件材料层的厚度在约10埃至约60埃的范围内。然后,对间隔件材料实施各向异性蚀刻工艺以形成侧壁间隔件212。侧壁间隔件212可以保护第一NMOS栅极间隔件240、第二NMOS栅极间隔件250和PMOS栅极间隔件260的侧壁。可选地,侧壁间隔件212可以用于偏移后面形成的掺杂区域,诸如重掺杂的源极/漏极区域。
在一些实施例中,在邻近于PMOS栅极堆叠件260的边缘的衬底202中形成源极/漏极(S/D)部件214。在一些实施例中,源极/漏极部件214的顶面高于衬底202的顶面。在一些实施例中,源极/漏极部件214的顶面高于衬底202的顶面,其高度差介于约1nm和约10nm之间。在可选的实施例中,源极/漏极部件214的顶面与衬底202的顶面基本共面。在一些实施例中,首先在衬底202中形成凹槽腔(未示出),然后在凹槽腔中生长应变材料来形成源极/漏极部件214。在一些实施例中,采用包括选择外延生长(SEG)、循环沉积和蚀刻(CDE)、化学汽相沉积(CVD)技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延(MBE)、其他合适的外延工艺或他们的组合的工艺生长应变材料。在一些实施例中,应变材料具有不同于衬底202的晶格常数以在半导体器件200的沟道区域上产生应变或应力,并因此使器件的载流子迁移率能够提高器件性能。
参照图1和图3,方法100继续至步骤104,其中对衬底202实施预非晶化注入(PAI)工艺218。在一些实施例中,PAI工艺218对衬底202进行注入并且对衬底202的晶格结构造成损伤从而形成非晶化区域(amorphizedregion)220。在本实施例中,在邻近于第二NMOS栅极堆叠件250的相对边缘的源极/漏极(S/D)区域中形成非晶化区域220。非晶化区域220具有深度D1(自衬底202的上表面测量的)。根据设计规范形成深度D1。在一些实施例中,深度D1在约10纳米至约150纳米的范围内。在本实施例中,深度D1小于约100纳米。因为侧壁间隔件212用来聚集PAI工艺218的注入能量,可以通过侧壁间隔件212的厚度来控制深度D1。同样,可以通过PAI工艺218,诸如注入能量、注入种类和/或注入剂量来控制深度D1。在至少一个实施例中,PAI工艺218用硅(Si)或锗(Ge)对衬底202进行注入。在可选的实施例中,PAI工艺218可以使用其他注入种类,诸如Ar、Xe、C、BF2、As、In、其他合适的注入种类或他们的组合。在本实施例中,根据注入温度,PAI工艺218在约15KeV至约50KeV的注入能量下以约1×1014原子/cm2至约2×1015原子/cm2的注入剂量注入Si或Ge。在至少一个实施例中,在室温(例如,25℃)下实施PAI工艺218。在可选的实施例中,在低温(例如,-60℃至-100℃)下通过调节离子注入机中的Cryo(低温)功能来实施PAI工艺218以提高注入非晶化的效率。在一些实施例中,以约0度至约20度的倾斜角实施PAI工艺218。
在一些可选的实施例中,PAI工艺218可以是多步骤注入工艺,包括注入工艺的至少第一步骤和第二步骤。分别采用第一和第二注入能量水平、第一和第二注入剂量,以及第一和第二注入倾斜角实施注入工艺的第一步骤和第二步骤。在至少一个实施例中,第一和第二注入能量水平在约15KeV至约50KeV的范围内。在另一实施例中,第一注入能量水平高于第二注入能量水平。在至少一个实施例中,第一和第二注入剂量在约1×1014原子/cm2至约2×1015原子/cm2的范围内。在另一实施例中,第一注入剂量大于第二注入剂量。在一些实施例中,第一和第二注入剂量的合并剂量在约1×1014原子/cm2至约2×1015原子/cm2的范围内,并且第一和第二注入剂量之间的比值在约1∶1至约7∶3的范围内。在一个实施例中,第一和第二倾斜角在约0度至约20度的范围内。在另一实施例中,第一注入倾斜角大于第二注入倾斜角。
在本实施例中,在PAI工艺218期间,第一NMOS栅极堆叠件240和PMOS栅极堆叠件260被保护件216覆盖使得邻近于第一NMOS栅极堆叠件240或PMOS栅极堆叠件260的边缘没有形成非晶化区域。在一些实施例中,保护件216是图案化的光刻胶层或硬掩模层。因此,可以避免由损伤衬底202的PAI工艺218所导致的第一NMOS栅极堆叠件240的漏电源,从而使第一NMOS栅极堆叠件240的漏电流最小化。在PAI工艺218之后通过例如蚀刻工艺或剥离工艺去除保护件216。
参照图1和图4,方法100继续至步骤106,在第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250、PMOS栅极堆叠件260和衬底202上方沉积应力膜222。可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、镀层、其他合适的方法和/或他们的组合形成应力膜222。应力膜222包含介电材料。在一些实施例中,应力膜222包含氮化硅、氮氧化硅、SiCN和/或他们的组合。在可选的实施例中,应力膜222包含氧化硅。在一些实施例中,应力膜222的厚度大于用于形成侧壁间隔件212的间隔件材料的厚度。在一些实施例中,应力膜222的厚度在约100埃至约300埃的范围内。在一些实施例中,在使非晶化区域220再结晶的后续退火工艺中,应力膜222用于提供拉伸应力。
参照图1和图5,方法100继续至步骤108,对衬底202实施退火工艺224。在一些实施例中,退火工艺224是快速热退火(RTA)工艺、尖峰RTA工艺或毫秒热退火(MSA)工艺(例如,毫秒激光热退火工艺)。在至少一个实施例中,退火工艺224包括在约600℃至约750℃的温度下持续约10秒至约5分钟的时间实施的RTA工艺。在可选的实施例中,退火工艺224包括在约990℃至约1050℃的温度下持续约0.1秒至约2秒的时间实施的尖峰RTA工艺。在可选的实施例中,退火工艺224还可以包括预热步骤以最小化(或甚至消除)末端(EOR)缺陷。在一些实施例中,可以在范围为约400℃至约700℃的温度下实施预热步骤。在一些实施例中,预热步骤可以实施约10秒至约5分钟的时间。在本实施例中,在约550℃的温度下实施预热步骤,持续约30秒。
在退火工艺224期间,由于非晶化区域220被再结晶,在衬底202中形成非晶化区域220的再结晶对应区域的位错226。在一些实施例中,邻近于第二NMOS栅极堆叠件250的相对边缘形成位错226。在一些实施例中,衬底202是指(100)衬底,并且沿着<111>方向形成位错226。在一些实施例中,<111>方向具有相对垂直于衬底202的表面的基准面测量的角度θ,该角度θ为约25度至约45度。在本实施例中,位错226具有角度θ为约35度的<111>方向。自夹断点(pinchoffpoint)228开始形成位错226。夹断点228具有自衬底202的上表面测量的深度D2。在一些实施例中,夹断点228的深度D2在约10纳米至约150纳米的范围内。在本实施例中,夹断点228的深度D2在约10纳米至约30纳米的范围内。夹断点228具有从第二NMOS栅极堆叠件250的邻近栅极边缘测量的水平缓冲(邻近)W。根据设计规范形成水平缓冲W和深度D2并且它们是退火工艺224的函数。在一些实施例中,夹断点228的水平缓冲W在约-5纳米至约10纳米的范围内(“-”表示夹断点228位于NMOS栅极堆叠件240或PMOS栅极堆叠件250下方)。可以这样形成夹断点228使其没有设置在由第二NMOS栅极堆叠件250限定的位于衬底202中的沟道区域内。
参照图1和图6,方法100继续至步骤110,从衬底202去除应力膜222。例如通过使用磷酸或氢氟酸的湿蚀刻,或通过使用合适蚀刻剂的干蚀刻来去除应力膜222。
根据公开的实施例,NMOS栅极堆叠件的位错的益处在于在用于NMOS器件(诸如,低阈值电压晶体管(LVT)和/或超低阈值电压晶体管(uLVT))的有源区域(例如,源极/漏极)内形成的位错可以改进NMOS栅极堆叠件的沟道区域内的应力从而增大器件运行速度。此外,防止在用于NMOS器件(诸如标准阈值电压晶体管(SVT)和/或高阈值电压晶体管(HVT))的有源区域(例如,源极/漏极)内形成位错的工艺可以通过阻止漏电流增加来提高器件性能。因此,公开的实施例在沟道区域中提供增大的应力水平以提高一个需要高运行速度的NMOS器件的载流子迁移率,而对另一需要低漏电流的NMOS器件不增添漏电源。可以理解到,不同的实施例可以具有不同的优点,并且没有特定的优点是任何实施例都必需的。
半导体器件可以实施进一步的CMOS或MOS技术加工以形成各种部件。例如,方法100可以继续以形成主间隔件。还可以形成接触部件,诸如硅化物区域。接触部件包含硅化物材料,诸如硅化镍(NiSi)、硅化镍铂(NiPtSi)、硅化镍铂锗(NiPtGeSi)、硅化镍锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化饵(ErSi)、硅化钴(CoSi)、其他合适的导电材料和/或他们的组合。可以通过包括沉积金属层;对金属层进行退火使得金属层能够与硅反应以形成硅化物;然后去除未反应的金属层的工艺来形成接触部件。可以进一步在衬底上形成层间介电(ILD)层以及对衬底进一步实施化学机械抛光(CMP)工艺以平坦化衬底。此外,可以在形成ILD层之前,在栅极结构的顶部形成接触蚀刻停止层(CESL)。
在实施例中,第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260在最终器件中保留多晶硅。在另一实施例中,实施栅极替换工艺(或后栅极工艺),其中用金属栅极替换第一多晶硅NMOS栅极堆叠件240、第二多晶硅NMOS栅极堆叠件250和多晶硅PMOS栅极堆叠件260。例如,金属栅极可以替换第一NMOS栅极堆叠件240、第二NMOS栅极堆叠件250和PMOS栅极堆叠件260的栅极堆叠件(即,多晶硅栅极堆叠件)。金属栅极包括衬层、功函数层、导电层、金属栅极层、填充层、其他合适的层和/或他们的组合。各种层包含任何合适的材料,诸如铝、铜、钨、钛、钽、钽铝、氮化钽铝、氮化钛、氮化钽、硅化镍、硅化钴、银、TaC、TaSiN、TaCN、TiAl、TiAlN、WN、金属合金、其他合适的材料和/或他们的组合。
后续加工可以进一步在衬底上形成各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质),其被配置成连接半导体器件的各种部件或结构。其他部件可以向器件提供电互连。例如,多层互连包括垂直互连件,诸如常规通孔或接触件;和水平互连件,诸如金属线。各种互连部件可以应用各种导电材料,包括铜、钨和/或硅化物。在一个实例中,镶嵌和/或双镶嵌工艺用于形成铜相关的多层互连结构。
所公开的半导体器件可以用于各种应用中,诸如数字电路、图像传感器器件、异质半导体器件、动态随机存取存储器(DRAM)单元、单电子晶体管(SET)和/或其他微电子器件(在本文中统称为微电子器件)。当然,本发明的各方面也适用于和/或易于适应其他类型的晶体管,包括单栅极晶体管、双栅极晶体管和其他多栅极晶体管,并且可以用于许多不同的应用,包括传感器单元、存储器单元、逻辑单元以及其他。
在一个实施例中,一种半导体器件包括具有第一阈值电压的第一NMOS器件和具有第二阈值电压的第二NMOS器件。第一NMOS器件包括位于半导体衬底上方的第一栅极结构、位于半导体衬底中并且邻近于第一栅极结构的相对边缘的第一源极/漏极(S/D)区域。第一S/D区域不包含位错。第二NMOS器件包括位于半导体衬底上方的第二栅极结构、位于半导体衬底中并且邻近于第二栅极结构的相对边缘的第二S/D区域、和位于第二S/D区域中的位错。
在另一实施例中,一种半导体器件包括第一NMOS器件、第二NMOS器件和PMOS器件。第一NMOS器件包括位于半导体衬底上方的第一栅极结构,和位于半导体衬底中并且邻近于第一栅极结构的相对边缘的第一源极/漏极(S/D)区域。第一S/D区域不包含位错。第二NMOS器件包括位于半导体衬底上方的第二栅极结构、位于半导体衬底中并且邻近于第二栅极结构的相对边缘的第二S/D区域、和位于第二S/D区域中的位错。第一NMOS器件的阈值电压大于第二NMOS器件的阈值电压。PMOS器件包括位于半导体衬底上方的第三栅极结构,和位于半导体衬底中并且邻近于第三栅极结构的相对边缘的第三源极/漏极(S/D)区域。第三S/D区域不包含位错。
在又一实施例中,一种用于形成半导体器件的方法包括:在衬底上方形成第一NMOS栅极结构和第二NMOS栅极结构;在第一NMOS栅极结构上方形成保护件;在邻近于第二NMOS栅极结构的衬底中形成非晶化区域;在第一NMOS栅极结构和第二NMOS栅极结构上方沉积应力膜;实施退火工艺以在邻近于第二NMOS栅极结构的衬底中形成位错;以及去除应力膜。
为了实施本发明的不同部件,以上公开内容提供了许多不同的实施例或实例。在上面描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不打算限定。因此,在不背离本发明的范围的情况下,可以以不同于本文中示出的示例性实施例的方式排布、组合或配置本文中公开的元件。
上面论述了若干实施例的部件,使得本领域中的技术人员可以更好地理解本发明的各方面。本领域中的技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域中的技术人员也应该了解到,这些等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (19)
1.一种半导体器件,包括:
第一NMOS器件,具有第一阈值电压,所述第一NMOS器件包括:
第一栅极结构,位于半导体衬底上方;
第一源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第一栅极结构的相对边缘,其中,所述第一源极/漏极(S/D)区域不包含位错;以及
第二NMOS器件,具有第二阈值电压,其中,所述第一阈值电压大于所述第二阈值电压,所述第二NMOS器件包括:
第二栅极结构,位于所述半导体衬底上方;
第二源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第二栅极结构的相对边缘;和
位错,位于所述第二源极/漏极(S/D)区域中。
2.根据权利要求1所述的器件,还包括:
位于所述半导体衬底上方的PMOS栅极结构;
位于所述半导体衬底中并且邻近于所述PMOS栅极结构的相对边缘的第三源极/漏极(S/D)区域;以及
位于所述第三源极/漏极(S/D)区域中的外延生长的部件。
3.根据权利要求2所述的器件,其中,所述外延生长的部件是外延SiGe。
4.根据权利要求2所述的器件,其中,所述第三源极/漏极(S/D)区域不包含位错。
5.根据权利要求1所述的器件,其中,所述位错的深度在10纳米至150纳米的范围内。
6.根据权利要求1所述的器件,其中,所述第一NMOS器件包括标准阈值电压晶体管(SVT)和/或高阈值电压晶体管(HVT)。
7.根据权利要求1所述的器件,其中,所述第二NMOS器件包括低阈值电压晶体管(LVT)和/或超低阈值电压晶体管(uLVT)。
8.根据权利要求1所述的器件,其中,所述第二源极/漏极(S/D)区域包含的种类为Si、Ge、Ar、Xe、C、BF2、As、In或他们的组合。
9.根据权利要求1所述的器件,其中,所述第一NMOS器件的漏电流小于所述第二NMOS器件的漏电流。
10.根据权利要求1所述的器件,其中,所述第一NMOS器件的运行速度小于所述第二NMOS器件的运行速度。
11.一种半导体器件,包括:
第一NMOS器件,包括:
第一栅极结构,位于半导体衬底上方;和
第一源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第一栅极结构的相对边缘,其中,所述第一源极/漏极(S/D)区域不包含位错;
第二NMOS器件,包括:
第二栅极结构,位于所述半导体衬底上方;
第二源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第二栅极结构的相对边缘;和
位错,位于所述第二源极/漏极(S/D)区域中,其中,所述第一NMOS器件的阈值电压大于所述第二NMOS器件的阈值电压;以及
PMOS器件,包括:
第三栅极结构,位于所述半导体衬底上方;和
第三源极/漏极(S/D)区域,位于所述半导体衬底中并且邻近于所述第三栅极结构的相对边缘,其中,所述第三源极/漏极(S/D)区域不包含位错。
12.根据权利要求11所述的器件,其中,所述第三源极/漏极(S/D)区域包括外延生长的部件。
13.根据权利要求11所述的器件,其中,所述第二源极/漏极(S/D)区域包含的种类为硅(Si)或锗(Ge)。
14.根据权利要求11所述的器件,其中,所述位错是沿着<111>方向形成的。
15.一种制造半导体器件的方法,包括:
在衬底上方形成第一NMOS栅极结构和第二NMOS栅极结构;
在所述第一NMOS栅极结构上方形成保护件;
在邻近于所述第二NMOS栅极结构的衬底中形成非晶化区域;
在所述第一NMOS栅极结构和所述第二NMOS栅极结构上方沉积应力膜;
实施退火工艺以在邻近于所述第二NMOS栅极结构的衬底中形成位错;以及
去除所述应力膜;
形成具有第一阈值电压的第一NMOS器件,以及形成具有第二阈值电压且包含所述位错的第二NMOS器件,其中,所述第一阈值电压大于所述第二阈值电压。
16.根据权利要求15所述的方法,其中,所述应力膜是氮化硅、氧化硅、氮氧化硅或他们的组合。
17.根据权利要求15所述的方法,其中,采用注入工艺以1×1014原子/cm2至2×1015原子/cm2的注入剂量形成所述非晶化区域。
18.根据权利要求15所述的方法,其中,通过快速热退火(RTA)工艺在400℃至750℃的温度下,在10秒至5分钟的时间段内实施所述退火工艺。
19.根据权利要求15所述的方法,其中,用于形成所述位错的工艺是通过尖峰热退火(尖峰RTA)工艺在900℃至1050℃的温度下,在0.1秒至2秒的时间段内实施的退火工艺。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/672,436 US8981530B2 (en) | 2012-11-08 | 2012-11-08 | Semiconductor device and method of forming the same |
US13/672,436 | 2012-11-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103811493A CN103811493A (zh) | 2014-05-21 |
CN103811493B true CN103811493B (zh) | 2016-05-25 |
Family
ID=50621568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310164907.7A Active CN103811493B (zh) | 2012-11-08 | 2013-05-07 | 半导体器件及其形成方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8981530B2 (zh) |
CN (1) | CN103811493B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8981530B2 (en) * | 2012-11-08 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
US10090360B2 (en) | 2015-02-13 | 2018-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor structure including a plurality of trenches |
US9679978B2 (en) | 2015-09-24 | 2017-06-13 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
CN106711215B (zh) | 2015-11-12 | 2021-09-07 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
US9871042B2 (en) | 2015-12-03 | 2018-01-16 | Samsung Electronics Co., Ltd. | Semiconductor device having fin-type patterns |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1684246A (zh) * | 2004-03-30 | 2005-10-19 | 三星电子株式会社 | 低噪声和高性能大规模集成器件、布局以及制造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006019936B4 (de) * | 2006-04-28 | 2015-01-29 | Globalfoundries Inc. | Halbleiterbauelement mit unterschiedlich verspannten Ätzstoppschichten in Verbindung mit PN-Übergängen unterschiedlicher Gestaltung in unterschiedlichen Bauteilgebieten und Verfahren zur Herstellung des Halbleiterbauelements |
US7473623B2 (en) * | 2006-06-30 | 2009-01-06 | Advanced Micro Devices, Inc. | Providing stress uniformity in a semiconductor device |
US7786518B2 (en) * | 2007-12-27 | 2010-08-31 | Texas Instruments Incorporated | Growth of unfaceted SiGe in MOS transistor fabrication |
US8193049B2 (en) * | 2008-12-17 | 2012-06-05 | Intel Corporation | Methods of channel stress engineering and structures formed thereby |
US8916428B2 (en) * | 2012-01-05 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device |
US9324622B2 (en) * | 2012-08-15 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
US8981530B2 (en) * | 2012-11-08 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
-
2012
- 2012-11-08 US US13/672,436 patent/US8981530B2/en active Active
-
2013
- 2013-05-07 CN CN201310164907.7A patent/CN103811493B/zh active Active
-
2015
- 2015-02-09 US US14/617,409 patent/US9337194B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1684246A (zh) * | 2004-03-30 | 2005-10-19 | 三星电子株式会社 | 低噪声和高性能大规模集成器件、布局以及制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20150155281A1 (en) | 2015-06-04 |
US8981530B2 (en) | 2015-03-17 |
US20140124869A1 (en) | 2014-05-08 |
US9337194B2 (en) | 2016-05-10 |
CN103811493A (zh) | 2014-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9768076B2 (en) | Semiconductor device and method of forming the same | |
KR101630080B1 (ko) | 반도체 장치 및 그 제조 방법 | |
CN103066124B (zh) | 具有多个应力结构的半导体器件及其制造方法 | |
CN103199064B (zh) | 形成半导体器件的方法 | |
CN102867784B (zh) | 具有位错结构的半导体器件及其形成方法 | |
US8999794B2 (en) | Self-aligned source and drain structures and method of manufacturing same | |
US9117844B2 (en) | Pinch-off control of gate edge dislocation | |
US8674453B2 (en) | Mechanisms for forming stressor regions in a semiconductor device | |
US9324865B2 (en) | Method of forming a semiconductor device | |
US9748390B2 (en) | Semiconductor device and method of forming the same | |
US20120086077A1 (en) | Fet structures with trench implantation to improve back channel leakage and body resistance | |
CN104241366A (zh) | FinFET器件的源极区和漏极区中的位错形成 | |
CN103811493B (zh) | 半导体器件及其形成方法 | |
US9178063B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |