CN103810146B - Reverse-input and sequential-output FFT structure designing method - Google Patents

Abstract

The invention provides a reverse-input and sequential-output FFT structure designing method. The method solves the problems, of extra storage requirements and turnover delay, brought by a traditional FF structure in a pulse compression system. The method comprises the following steps: (1) designing a butterfly-shaped calculation unit in an FFT structure, wherein the butterfly-shaped calculation unit comprises two input, two output, a summator, a subtracter and an actual part and imaginary part exchange unit, the two output are used for obtaining the sum result and the difference result of two input data through calculation of the summator and the subtracter in the butterfly-shaped calculation unit, and an actual and imaginary part, used for exchanging result data, of the actual part and imaginary part exchange unit is used when operation of result data multiplied by an imaginary unit -j is needed, (2) conducting two-dimension decomposition on the address of the input data and output data again, deducing an FFT calculation model of a DIT structure, and utilizing coefficient set obtained through the two-dimension decomposition to design a signal flow graph, (3) realizing the signal flow graph in the step (2) through hardware, and completing the FFT structure design.

Description

A kind of FFT construction design method of backward input sequence output

Technical field

The invention belongs to digital signal processing technique field, relate to the FFT structure design of a kind of backward input sequence output Method.

Background technology

Along with large scale integrated circuit and the development of Digital Signal Processing, fft algorithm has irreplaceable effect, It is widely used in the fields such as radar, sonar, communication.The either pulse compression body employed in currently the majority radar system System, or the matched filtering maximum signal noise ratio principle in the communications field, be directed to time-domain signal and obtain frequency spectrum by FFT, frequently Territory processes, then by IFFT(inverse fast fourier transform) return to time domain.Real-time to FFT of this signal processing Property, storage resource consumption, flowing water sluggishness all have higher requirements, and need the FFT structure that specialized designs optimizes accordingly.

During process of pulse-compression, typical processing procedure is that time-domain signal obtains frequency-region signal through FFT process, At frequency domain and corresponding fac-tor, the data obtained obtain time-domain signal through IFFT process again, and this process is in radar system System receives in compression of signal pulse, SAR image-processing algorithms, communication system reception Signal Matching filtering and is all frequently used, its In important problem be the extraction of typical DIF(frequency domain) FFT process data sequentially inputs, result backward exports, with this When structure carries out IFFT, to cache data before input data, the process of adjustment order, this does not only take up a large amount of storage Space (more than the storage whole than what major part flowing structure FFT processing procedure needed), and increase stream treatment and prolong Time, both improve the system demand to storage resource, reduce again system real time.

Summary of the invention

The invention aims to overcome the defect of prior art, solve traditional FFT structure in pulse compression system The extra storage demand brought and flowing water braking problems, propose the FFT construction design method of a kind of backward input sequence output, with Time the storage to twiddle factor data when realizing of this structure optimize, save storage resource further.

In order to solve above-mentioned technical problem, its basic implementation process is as follows:

The FFT construction design method of a kind of backward input sequence output, comprises the steps:

Step one, design FFT structure in butterfly processing element, this butterfly processing element include two inputs, two defeated Go out, adder, subtractor and real imaginary part crosspoint, two are output as two input data by adding in butterfly processing element That musical instruments used in a Buddhist or Taoist mass and subtractor computing obtain and result and difference result, when needing to do the operation that result data is multiplied by empty unit-j, logical The real imaginary part crossing real imaginary part crosspoint exchange result data realizes；

Step 2, address to input data and output data re-start two-dimensional decomposition, the FFT of derivation DIT structure meter Calculate model, utilize the coefficient sets modelled signal flow graph that two-dimensional decomposition obtains；

Step 3, the signal flow diagram in step 2 is carried out hardware realization, complete the design of FFT structure.

After step 3, utilize the symmetry of twiddle factor, only storeThe twiddle factor counted is in ROM, then Control to produce residue by addressThe twiddle factor counted, to frontSinusoidal wave data carry out turning over about self axis of symmetry Turn, obtain complete sine waveform data about the positive and negative upset of transverse axis, storageThe twiddle factor counted enters in ROM The optimization of row storage.

Step 3 use one-way delay feedback arrangement realize signal flow diagram.

Beneficial effects of the present invention:

The present invention propose a kind of backward input sequence output FFT construction design method itself combine base 2 butterfly and The advantage of radix-4 butterfly, uses the stream treatment structure of single channel Delay Feedback can improve the real-time of process, and backward input Sequential output can save and adjusts the buffer memory of output order and adjust the flowing water delay needed for output order, thus enters one Step reduces flowing water sluggishness, reduces storage demand.During a process of pulse-compression, existing decimation in frequency FFT structure is entered Row FFT process, the DIT-FFT Algorithm structure in conjunction with the present invention carries out IFFT process, can effectively reduce storage, improves in real time Property.The present invention contrasts prior art, no matter takes fixed-point implementation or floating-point realizes, and can realize under keeping precision Middle reduction resource consumption and flowing water are sluggish, thus reduce taking of resource of storage and (also utilize twiddle factor symmetry in the present invention Reduce further the demand to storage resource), improve the real-time of handling process, obtain in resource and performance two aspect simultaneously Promote.

Accompanying drawing explanation

Fig. 1 is R2²The butterfly unit of SDF DIT FFT；

Fig. 2 is the signal flow diagram calculating a certain output data；

Fig. 3 is the circuit structure block diagram of Fig. 2.

Fig. 4 is twiddle factor symmetry.

Detailed description of the invention

Below in conjunction with the accompanying drawings the embodiment of the inventive method is elaborated.

A kind of method of the FFT structure design of backward input sequence output, its concrete steps include:

Step one, design basic processing unit: Fig. 1 show a R2²4 FFT butterfly units of SDF DIT structure, It is mainly made up of 2 butterfly units of two-stage, and so-called butterfly unit comprises two inputs, two outputs, adder, subtractions Device, real imaginary part crosspoint (unit-j in an opponent's defence).The result that two inputs obtain through adder computing is as an output, warp Cross the result that subtractor obtains to export as another, when result is multiplied by empty unit-j, utilize simple data reality imaginary part to hand over Change and can complete.Butterfly unit is designed, as arithmetic element most basic in FFT structure according to the structure of Fig. 1.

Step 2, modelled signal flow graph: according to R2²The principle of SDF algorithm, carries out two dimension point to the address n of input signal Solve: $n=n_1+2n_2+4n_3,n_1=\mathrm{0,1},n_2=\mathrm{0,1},n_3=\mathrm{0,1},...,\frac{N}{4}-1,$ Corresponding output signal address is also carried out two-dimensional decomposition simultaneously:

$k=\frac{N}{2}{k}_1+\frac{N}{4}{k}_2+k_3,k_1=\mathrm{0,1},k_2=\mathrm{0,1},k_3=\mathrm{0,1},...,\frac{N}{4}-1,$ Finally give

$X\left(k\right)=\underset{n_3=0}{\overset{\frac{N}{4}-1}{\mathrm{\Σ}}}\left\{\right[x\left(4n_3\right)+x({4n}_3+2){(-1)}^{k_2}{W}_N^{{2k}_3}]+{(-1)}^{k_1}{(-j)}^{k_2}[x(4n_3+1)+x({4n}_3+3){(-1)}^{k_2}{W}_N^{{2k}_3}\left]W_N^{k_3}\right\}{W}_{\frac{N}{4}}^{n_3{k}_3}$ The principle of algorithm is exactly repeatedly that recurrence is carried outThe FFT counted, wherein for certain output data that OPADD is k, it is Obtained by butterfly computation and multiplying step by step by input data.Fig. 2 show 1 16 DIT structure FFT, in scheming As a example by the signal flow diagram of shown calculating X (0) and (11) two results of X, finally exported knot by two-stage totally four row butterflies Really.After the address k value of output signal determines, one group of unique coefficient sets (k can be obtained according to the above address decomposition method₁, k₂,k₃), the flow direction of signal is just by (k₁,k₂,k₃) decision of this class value, formula above can be seen that the first row butterfly of every one-level Arithmetic element carries out additive operation or subtraction is by k₂Controlling, the secondary series butterfly processing element of every one-level adds Method computing or subtraction are by k₁Control, if carry out real imaginary part exchange (being i.e. multiplied by-j) by k₂Control, final every one-level Result of calculation twiddle factor to be taken advantage ofThe numerical value of twiddle factor is by points N and k₃Determining, concrete numerical value can be by store The ROM addressing of twiddle factor values obtains.X (0) shown in Fig. 2 and X (11) is exactly by corresponding (k₁,k₂,k₃) coefficient warp step by step Cross the output that the computings such as adder, subtractor, multiplier finally give, so for each output data, according to the two of address Dimension isolation, draws its corresponding coefficient (k₁,k₂,k₃) it is assured that the input signal in order to obtain this output flows to.Press The two-dimensional decomposition of the address carried out according to aforesaid way makes computing have the feature of backward input sequence output, shown in Fig. 2 Signal flow diagram invocation step step by step once in butterfly unit can realize the FFT computing of DIT structure, obtain each corresponding Output data X (k) that k value is corresponding.

Step 3, design concrete hardware and realize structure: in order to ensure the real-time of FFT computing, flowing structure should be taked Realizing, Fig. 3 show the flowing structure DIT FFT of 256, uses single channel Delay Feedback structure, concrete as it can be seen, from Data are input to a data output only path, two row butterfly computation lists of every one-level in BFI and BFII representative graph 2 respectively Unit, in the output result temporary cache of the subtractor in every string butterfly to RAM, the operation result of adder is then delivered to next Level proceeds computing, when first order first row data flowing water enters, it is only necessary to cache 1 data and just can start computing, and After data cached reading, participated in the poor result that subtraction obtains be stored in the caching emptied, participated in additive operation And result pass to next stage；When secondary series data flowing water enters, need to cache 2 data and just can start computing, and the One data cached reading is participated in first room that the poor result that subtraction obtains is stored in caching after carrying out computing, Participate in additive operation passes to next stage with result, is participated in the difference that subtraction obtains after second data cached reading Second room that result is stored in caching, participate in additive operation passes to next stage with result；By that analogy, each column operations The caching needed is according to 1,2,4,8 ... (powers of 2) are incremented by, and this caching defines a kind of feedback arrangement, according to this feedback The mode of caching arranges memory node and arithmetic element, it is possible to achieve the data operation of omnidistance flowing water.

Owing to every one-level operation result will be with corresponding rotation fac-tor, twiddle factor (i.e. sinusoidal wave data) data It is stored in ROM, in order to save storage resource further, it is possible to use twiddle factor (i.e. sin cos functions) as shown in Figure 4 Symmetry, only storeThe twiddle factor counted, in ROM, then controls to produce residue by addressThe rotation counted because of Son, sinusoidal wave symmetry as shown in Figure 4, to frontSinusoidal wave data carry out the upset about self axis of symmetry, about horizontal stroke The positive and negative upset of axle can obtain complete sine waveform data, so storageThe twiddle factor counted enters in ROM The optimization of row storage.

The address mapping mode of design, step 3 design in basic butterfly processing element in integrating step one, step 2 Circuit structure and to the optimization that carries out of storage, it is achieved the FFT structure of backward input sequence of the present invention output.

Claims (2)

1. the FFT construction design method of a backward input sequence output, it is characterised in that comprise the steps:

Butterfly processing element in step one, design FFT structure, this butterfly processing element includes two inputs, two output, adds Musical instruments used in a Buddhist or Taoist mass, subtractor and real imaginary part crosspoint, two are output as two input data by the adder in butterfly processing element That obtain with subtractor computing and result and difference result, when needing to do the operation that result data is multiplied by empty unit-j, by reality The real imaginary part of imaginary part crosspoint exchange result data realizes；

Step 2, address to input data and output data re-start two-dimensional decomposition, and the FFT of derivation DIT structure calculates mould Type, utilizes the coefficient sets modelled signal flow graph that two-dimensional decomposition obtains；

Step 3, the signal flow diagram in step 2 is carried out hardware realization, complete the design of FFT structure；

After step 3, utilize the symmetry of twiddle factor, only storeThe twiddle factor counted is in ROM, then by ground Location controls to produce residueThe twiddle factor counted, to frontSinusoidal wave data carry out the upset about self axis of symmetry, about The positive and negative upset of transverse axis obtains complete sine waveform data, storageThe twiddle factor counted is to carrying out in ROM storing Optimize.

The FFT construction design method of a kind of backward input sequence the most as claimed in claim 1 output, it is characterised in that step One-way delay feedback arrangement is used to realize signal flow diagram in three.