CN103810146A - Reverse-input and sequential-output FFT structure designing method - Google Patents

Abstract

The invention provides a reverse-input and sequential-output FFT structure designing method. The method solves the problems, of extra storage requirements and turnover delay, brought by a traditional FF structure in a pulse compression system. The method comprises the following steps: (1) designing a butterfly-shaped calculation unit in an FFT structure, wherein the butterfly-shaped calculation unit comprises two input, two output, a summator, a subtracter and an actual part and imaginary part exchange unit, the two output are used for obtaining the sum result and the difference result of two input data through calculation of the summator and the subtracter in the butterfly-shaped calculation unit, and an actual and imaginary part, used for exchanging result data, of the actual part and imaginary part exchange unit is used when operation of result data multiplied by an imaginary unit -j is needed, (2) conducting two-dimension decomposition on the address of the input data and output data again, deducing an FFT calculation model of a DIT structure, and utilizing coefficient set obtained through the two-dimension decomposition to design a signal flow graph, (3) realizing the signal flow graph in the step (2) through hardware, and completing the FFT structure design.

Description

A kind of FFT construction design method of backward input sequence output

Technical field

The invention belongs to digital signal processing technique field, relate to a kind of FFT construction design method of backward input sequence output.

Background technology

Along with the development of large scale integrated circuit and Digital Signal Processing, fft algorithm has irreplaceable effect, is widely used in the fields such as radar, sonar, communication.No matter be the pulse compression system adopting in present most of radar system, or the matched filtering maximum signal noise ratio principle in the communications field, all relate to time-domain signal and obtain frequency spectrum by FFT, frequency domain is processed, then by IFFT(inverse fast fourier transform) get back to time domain.Real-time, storage resource consumption, the flowing water sluggishness of this signal processing to FFT all has higher requirements, and needs the FFT structure of the corresponding optimization of specialized designs.

In process of pulse-compression process, typical processing procedure is that time-domain signal is processed and obtained frequency-region signal through FFT, multiply each other in frequency domain and the corresponding factor, the data that obtain are processed and are obtained time-domain signal through IFFT again, this process receives compression of signal pulse in radar system, SAR imaging processing algorithm, communication system receives in Signal Matching filtering and is all frequently used, wherein important problem is that typical DIF(frequency domain extracts) input of FFT process data order, the output of result backward, while carrying out IFFT by this structure, before input data, to carry out buffer memory to data, the processing of adjustment order, this not only takies a large amount of storage spaces (the whole storage needing than most of flowing structure FFT processing procedure is also many), and strengthen stream treatment time delay, both improved the demand of system to storage resources, reduce again system real time.

Summary of the invention

The object of the invention is the defect in order to overcome prior art, extra storage demand and the sluggish problem of flowing water that in pulse compression system, traditional FFT structure is brought are solved, a kind of FFT construction design method of backward input sequence output is proposed, this structure is optimized the storage of twiddle factor data in the time realizing simultaneously, has further saved storage resources.

In order to solve the problems of the technologies described above, its basic implementation process is as follows:

A FFT construction design method for backward input sequence output, comprises the steps:

Butterfly processing element in step 1, design FFT structure, this butterfly processing element comprises two inputs, two outputs, totalizer, subtracter and real imaginary part crosspoints, two that be output as that two input data obtain by the totalizer in butterfly processing element and subtracter computing and result and poor results, in the time need to doing result data and be multiplied by the operation of empty unit-j, realize by the real imaginary part of real imaginary part crosspoint exchange result data;

Step 2, the address of input data and output data is re-started to two dimension decompose, the FFT computation model of derivation DIT structure, utilizes two dimension to decompose the coefficient sets modelled signal flow graph that obtains;

Step 3, the signal flow diagram in step 2 is carried out to hardware realization, complete FFT structural design.

After step 3, utilize the symmetry of twiddle factor, only storage

the twiddle factor of counting, in ROM, is then controlled and is produced residue by address

the twiddle factor of counting, to front

sinusoidal wave data carry out about the upset of self axis of symmetry, obtain complete sine waveform data about the positive and negative upset of transverse axis, storage

the twiddle factor of counting is to the optimization of storing in ROM.

In step 3, adopt one-way delay feedback arrangement to realize signal flow diagram.

Beneficial effect of the present invention:

The FFT construction design method of a kind of backward input sequence output that the present invention proposes itself combines the advantage of base 2 butterflies and base 4 butterflies, adopt the stream treatment structure of single channel Delay Feedback can improve the real-time of processing, and the output of backward input sequence can be saved the buffer memory of adjustment output order and adjust the required flowing water of output order and be postponed, thereby further reduces flowing water sluggishness, minimizing storage demand.In a process of pulse-compression process, existing decimation in frequency FFT structure is carried out FFT processing, carries out IFFT processing in conjunction with DIT-FFT Algorithm structure of the present invention, can effectively reduce storage, improves real-time.The present invention contrasts prior art, no matter take fixed-point implementation or floating-point to realize, can both keep under precision, in realization, reduce resource consumption and flowing water sluggishness, thereby reduce take (also the utilizing twiddle factor symmetry further to reduce the demand to storage resources in the present invention) of storage resources, the real-time that improves treatment scheme is obtaining lifting aspect resource and performance two simultaneously.

Accompanying drawing explanation

Fig. 1 is R2 ²the butterfly unit of SDF DIT FFT;

Fig. 2 is the signal flow diagram that calculates a certain output data;

Fig. 3 is the circuit structure block diagram of Fig. 2.

Fig. 4 is twiddle factor symmetry.

Embodiment

Below in conjunction with accompanying drawing, the embodiment of the inventive method is elaborated.

A method for the FFT structural design of backward input sequence output, its concrete steps comprise:

Step 1, design basic processing unit: Figure 1 shows that a R2 ²4 FFT butterfly units of SDF DIT structure, it is mainly made up of 2 butterfly units of two-stage, and so-called butterfly unit comprises two inputs, two output, totalizer, subtracter, the real imaginary part crosspoint (unit that takes advantage of a weak point in opponent's defence-j).Two input results that computing obtains through totalizer are as an output, and the result obtaining through subtracter is exported as another, in the time that result is multiplied by empty unit-j, utilize the real imaginary part exchange of simple data to complete.According to the structural design butterfly unit of Fig. 1, as the most basic arithmetic element in FFT structure.

Step 2, modelled signal flow graph: according to R2 ²sDF calculates ratio juris, the address n of input signal is carried out to two dimension and decompose: $n={\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_1+2{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_2+4{\mathrm{<figure-callout\; id="3"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_3,{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_1=\mathrm{0,1},{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_2=\mathrm{0,1},{\mathrm{<figure-callout\; id="3"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_3=\mathrm{0,1},...,\frac{N}{4}-1,$ Two dimension is also carried out in corresponding output signal address decomposes simultaneously:

$k=\frac{N}{2}{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_1+\frac{N}{4}{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_2+{\mathrm{<figure-callout\; id="3"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_3,{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_1=\mathrm{0,1},{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_2=\mathrm{0,1},{\mathrm{<figure-callout\; id="3"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_3=\mathrm{0,1},...,\frac{N}{4}-1,$ Finally obtain $X\left(k\right)=\underset{{\mathrm{<figure-callout\; id="3"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_3=0}{\overset{\frac{N}{4}-1}{\mathrm{\&Sigma;}}}\left\{\right[x\left(4n_3\right)+x({4\mathrm{<figure-callout\; id="3"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_3+2){(-1)}^{k_2}{W}_N^{{2k}_3}]+{(-1)}^{k_1}{(-j)}^{k_2}[x(4{\mathrm{<figure-callout\; id="3"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_3+1)+x({4\mathrm{<figure-callout\; id="3"\; label="n"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">n</figure-callout>}}_3+3){(-1)}^{k_2}{W}_N^{{2k}_3}\left]W_N^{k_3}\right\}{W}_{\frac{N}{4}}^{n_3{\mathrm{<figure-callout\; id="3"\; label="k"\; filenames="HDA0000462559670000011.png,HDA0000462559670000012.png"\; state="\{\{state\}\}">k</figure-callout>}}_3}$ Calculating ratio juris is exactly repeatedly that recurrence is carried out certain output data that the FFT counting is wherein k for OPADD, it is obtained by butterfly computation and multiplying step by step by input data.Figure 2 shows that 1 16 DIT structure FFT, take the signal flow diagram of the calculating X (0) shown in scheming and (11) two results of X as example, by two-stage totally four row butterflies obtain final Output rusults.The address k value of output signal can obtain one group of unique coefficient sets (k according to the above address decomposition method after determining ₁, k ₂, k ₃), the flow direction of signal is just by (k ₁, k ₂, k ₃) this class value determines, can find out that by formula above the first row butterfly processing element of every one-level carries out additive operation or subtraction is by k ₂control, the secondary series butterfly processing element of every one-level carries out additive operation or subtraction is by k ₁control, whether carry out real imaginary part exchange (be multiplied by-j) by k ₂control, final every one-level result of calculation will be taken advantage of twiddle factor

the numerical value of twiddle factor is by points N and k ₃determine, concrete numerical value can be obtained by the ROM addressing to storing twiddle factor numerical value.X shown in Fig. 2 (0) and X (11) are exactly by corresponding (k ₁, k ₂, k ₃) output that finally obtains through computings such as totalizers, subtracter, multiplier step by step of coefficient, so for each output data, according to the two-dimentional isolation of address, draw its corresponding coefficient (k ₁, k ₂, k ₃) input signal that just can be defined as obtaining this output flows to.The two dimension decomposition of the address of carrying out in the manner described above makes computing have the feature of backward input sequence output, according to the signal flow diagram shown in Fig. 2 step by step invocation step once in butterfly unit can realize the FFT computing of DIT structure, obtain output data X (k) corresponding to each corresponding k value.

Step 3, design concrete hardware implementation structure: in order to guarantee the real-time of FFT computing, should take flowing structure to realize, Figure 3 shows that the flowing structure DIT FFT of 256, adopt single channel Delay Feedback structure, specifically as shown in the figure, be input to data output from data and only have a path, two row butterfly processing elements of every one-level in BFI and BFII difference representative graph 2, the Output rusults temporary cache of the subtracter in each row butterfly is in RAM, the operation result of totalizer is delivered to next stage and proceeds computing, when first order first row data flowing water enters, only need 1 data of buffer memory just can start computing, and after data cached reading, participated in the poor result that subtraction obtains and deposited in the buffer memory having emptied, what participate in additive operation passes to next stage with result, when secondary series data flowing water enters, need 2 data of buffer memory just can start computing, and participated in the poor result that subtraction obtains after carrying out computing and deposited in first room in buffer memory first data cached reading, what participate in additive operation passes to next stage with result, after second data cached reading, participated in the poor result that subtraction obtains and deposit second room in buffer memory in, what participate in additive operation passes to next stage with result, by that analogy, the buffer memory that each column operations needs is according to 1,2,4,8 ... (2 powers) increase progressively, this buffer memory has formed a kind of feedback arrangement, arranges memory node and arithmetic element according to the mode of this feedback buffer memory, can realize the data operation of omnidistance flowing water.

Because every one-level operation result all will multiply each other with corresponding twiddle factor, twiddle factor (being sinusoidal wave data) data are stored in ROM, in order further to save storage resources, can utilize the symmetry of twiddle factor (being sin cos functions) as shown in Figure 4, only storage

the twiddle factor of counting, in ROM, is then controlled and is produced residue by address the twiddle factor of counting, sinusoidal wave symmetry as shown in Figure 4, to front

sinusoidal wave data carry out about the upset of self axis of symmetry, can obtain complete sine waveform data about the positive and negative upset of transverse axis, so storage

the twiddle factor of counting is to the optimization of storing in ROM.

The address mapping mode designing in basic butterfly processing element in integrating step one, step 2, the circuit structure of step 3 design and the optimization that storage is carried out, realize the FFT structure of backward input sequence output of the present invention.

Claims (3)

1. a FFT construction design method for backward input sequence output, is characterized in that, comprises the steps:

Butterfly processing element in step 1, design FFT structure, this butterfly processing element comprises two inputs, two outputs, totalizer, subtracter and real imaginary part crosspoints, two that be output as that two input data obtain by the totalizer in butterfly processing element and subtracter computing and result and poor results, in the time need to doing result data and be multiplied by the operation of empty unit-j, realize by the real imaginary part of real imaginary part crosspoint exchange result data;

Step 2, the address of input data and output data is re-started to two dimension decompose, the FFT computation model of derivation DIT structure, utilizes two dimension to decompose the coefficient sets modelled signal flow graph that obtains;

Step 3, the signal flow diagram in step 2 is carried out to hardware realization, complete FFT structural design.

2. the FFT construction design method of a kind of backward input sequence output as claimed in claim 1, is characterized in that, after step 3, utilizes the symmetry of twiddle factor, only storage

the twiddle factor of counting, in ROM, is then controlled and is produced residue by address

the twiddle factor of counting, to front

sinusoidal wave data carry out about the upset of self axis of symmetry, obtain complete sine waveform data about the positive and negative upset of transverse axis, storage

the twiddle factor of counting is to the optimization of storing in ROM.

3. the FFT construction design method of a kind of backward input sequence output as claimed in claim 1 or 2, is characterized in that, adopts one-way delay feedback arrangement to realize signal flow diagram in step 3.

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