CN102353838A - Rapid high precision frequency measuring realization method by applying FPGA chip - Google Patents

Abstract

The invention relates to a rapid high precision frequency measuring realization method by applying an FPGA chip, belonging to the digital signal processing field. According to the method, an FFT module, a Fife module and an ROM module are added into the FPGA chip, an input signal is divided into three signals, wherein, two signals are subjected to frequency shift, the other signal is not subjected to frequency shift, on a basis of Rife, a real part absolute value and an imaginary part absolute value of an FFT operation result are compared to determine a frequency spectrum maximum value, three frequency measuring results are obtained respectively, and a maximum value is selected as a final frequency measured value. According to the method, frequency measuring precision of a fixed-length receiving signal is raised, a processing speed is accelerated, and a real-time property of a system is raised.

Description

A kind of quick high accuracy frequency measurement method of realizing with fpga chip

Technical field

The present invention relates to a kind of method of using the quick high accuracy frequency measurement of fpga chip realization, belong to digital processing field.

Background technology

Frequency measurement is major issue in the engineering fields such as electronic reconnaissance, radar, communication.Under different signal to noise ratio (S/N ratio) conditions, the resulting frequency measurement accuracy of distinct methods has nothing in common with each other, and still, no matter adopts which kind of frequency measurement method, and the root-mean-square error of its frequency measurement (RMSE) can be less than a lower limit: carat Mei-Luo circle [3] (CLRB).The maximum likelihood frequency measurement method (ML) that document [3] provides can reach this boundary, therefore is called as optimum the measurement.But the ML method will be carried out linear search, and operand is very big, and handling property is poor in real time, is not easy to Project Realization.The frequency measurement method that document [4] provides, though speed is very fast, (less than 6dB) poor performance when signal to noise ratio (S/N ratio) is relatively lower can't reach the practical applications requirement.The frequency measurement method that document [5] provides is a kind of approximate solution to the ML method, and performance is near CLRB, but than low signal-to-noise ratio the time, can occur separating disperse phenomenon, calculated amount is also bigger, is difficult for hardware and realizes.

The frequency measurement method that document [1] provides after input signal is carried out a FFT computing, utilizes the maximum spectral line and the left side thereof or the right one big spectral line to carry out interpolation and confirms actual frequency position, i.e. Rife method.This method only needs a FFT computing, and therefore, operand is little, and hardware is realized easily.The Rife method is very little at the frequency error measurement of sampling frequency central area, and near CLRB, but near the error the FFT sampling frequency is bigger.

MRife method given here makes the frequency of signal be positioned at the central area of sampling frequency all the time through input signal is carried out frequency spectrum shift, has improved frequency measurement accuracy.MRife method frequency measurement accuracy improves greatly, when SNR＞0dB the root-mean-square error of method frequency measurement near CLRB, and in whole frequency band smooth performance.

Summary of the invention

Technical matters to be solved by this invention is the deficiency to the above-mentioned background technology, and a kind of method of using the quick high accuracy frequency measurement of fpga chip realization is provided.The present invention makes the frequency of signal be positioned at the central area of sampling frequency all the time through input signal is carried out frequency spectrum shift, has improved frequency measurement accuracy.The precision of this method survey frequency improves greatly, when SNR＞0dB the root-mean-square error of method frequency measurement near CLRB, and in whole frequency band smooth performance.

The present invention adopts following technical scheme for realizing the foregoing invention purpose:

A kind of method of using the quick high accuracy frequency measurement of fpga chip realization comprises the steps:

Step 1, input signal is divided into parallel three the tunnel, first via input signal translation-1/3FFT sampling frequency, the second road input signal translation 1/3FFT sampling frequency, the Third Road input signal is not done frequency displacement;

Step 2 is done the FFT computing to each road input signal, confirms maximum spectral line value | X (k ₀) |, inferior big spectral line value | X (k ₀+ r) |, the corresponding signal frequency k of maximum spectral line value ₀And the value of translation coefficient r, specifically comprise the steps:

Step 2-1, definition input signal x (n) does the FFT computing to x (n);

Wherein, $x\left(n\right)={\mathrm{ae}}^{j(2\mathrm{\π}{f}_c\mathrm{n\Δt}+{\mathrm{\Φ}}_0)}+v\left(n\right)$ N=0,1, L, N-1 (1)

A is amplitude, f _cBe original frequency, Ф ₀Be first phase, Δ t is that sampling interval, N are sample number,

Real part and imaginary part is separate and all obey N (0, σ ²) distribute σ ²Be that constant is represented noise variance;

Step 2-2-1, the relatively corresponding spectral line value of all signal frequencies on the frequency spectrum;

When signal frequency was in the sampling frequency central area, the maximal value of getting the real part absolute value was as the maximum spectral line value in sampling frequency central area;

When signal frequency was in non-sampling frequency central area, the maximal value of getting the imaginary part absolute value was as the maximum spectral line value in non-sampling frequency central area;

Step 2-2-2, relatively the maximum spectral line value of sampling frequency central area and the maximum spectral line value of non-sampling frequency central area are got the maximum spectral line value of big person as entire spectrum;

Step 2-2-3 gets the corresponding signal frequency of maximum spectral line value as k ₀

Step 2-2-4, repeating step 2-2-1 is to definite big spectral line value of step 2-2-2;

Step 2-3 confirms the value of translation coefficient r, when | X (k ₀+ r) |＜| X (k ₀-r) | the time, r=-1, otherwise, r=1;

Step 3 is calculated the frequency interpolation δ of each road input signal respectively according to following method ₁, according to δ ₁Span confirm the final frequency measured value

Specifically comprise the steps:

Step 3-1 adopts following formula calculated rate interpolation δ ₁:

${\mathrm{\δ}}_1=\frac{\left|X(k_0+r)\right|}{\left|X(k_0+r)\right|+\left|X\left(k_0\right)\right|}---\left(2\right)$

Step 3-2 works as δ ₁During ∈ [1/3,1/2], obtain frequency values with the Rife method Remember that this frequency values is the final frequency measured value

Step 3-3 works as δ ₁During ∈ [0,1/3], with after the parallel moving of signal r/3 times sampling frequency with Rife method calculated rate interpolation δ ₁Then according to recomputating the frequency interpolation δ that obtains ₁Carry out following operation:

Step 3-3-1 works as δ ₁During ∈ [1/3,1/2], obtain frequency measurement with the Rife method Deduct r/3 times of sampling frequency as the final frequency measured value with frequency measurement again

Step 3-3-2 works as δ ₁During ∈ [0,1/3],, return step 3-3 with the r negate;

Step 4, the comparison step 3 calculated the final three-way input signal frequency measurement value

maximum value as the last measurement frequency.

The FPGA chip to achieve rapid precision frequency measurement method, the step 3 by Rife frequency measurement values obtained by the method

is calculated as follows:

$\stackrel{\‾}{f_c}=\frac{1}{T}(k_0+r\frac{\left|X(k_0+r)\right|}{\left|X\left(k_0\right)\right|+\left|X(k_0+r)\right|})---\left(3\right)$

Wherein, FFT T=transformation period Δ t*N.

The present invention adopts technique scheme, has following beneficial effect:

(1), can effectively improve the frequency measurement accuracy that regular length is received signal through the spectral line after the FFT computing is carried out the translation interpolation operation.

(2) adopt FPGA that method is carried out parallelization and handle,, can realize high-speed frequency measurement, accelerated processing speed, improved the real-time of system through 3 tunnel parallel FFT, translation, interpolation.

Description of drawings

Fig. 1 is the RTL figure that realizes this method with fpga chip.

Spectrum diagram when Fig. 2 is translation coefficient r=1.

Fig. 3 is the simulation curve comparison diagram of Rife method and MRife method survey frequency root-mean-square error when SNR=-3dB.

Fig. 4 is the simulation curve comparison diagram of Rife method and MRife method survey frequency root-mean-square error when SNR=0dB.

Fig. 5 is the simulation curve comparison diagram of Rife method and MRife method survey frequency root-mean-square error when SNR=3dB.

Fig. 6 is the sequential simulation waveform figure of MRife method.

Fig. 7 is the sequential simulation waveform figure that the MRife method is amplified at the time ruler place.

Fig. 8 is a process flow diagram of realizing this method with fpga chip.

Embodiment

Be elaborated below in conjunction with the technical scheme of accompanying drawing to invention:

This method is on the basis of Rife method, to improve to obtain, and name this method is MRife method (modified R ife method) at present.

As shown in Figure 1, on fpga chip, add three FFT modules, three Rife modules, two ROM modules.The FFT module is accomplished the FFT computing, and the Rife module is accomplished the Rife algorithm, and the ROM module is used to deposit required complex exponential real part of input signal translation and imaginary part.

As shown in Figure 8: a kind of method of using the quick high accuracy frequency measurement of fpga chip realization comprises the steps:

A kind of method of using the quick high accuracy frequency measurement of fpga chip realization comprises the steps:

Step 1, input signal is divided into parallel three the tunnel, first via input signal translation-1/3FFT sampling frequency, the second road input signal translation 1/3FFT sampling frequency, the Third Road input signal is not done frequency displacement;

Step 2 is done the FFT computing to each road input signal, confirms maximum spectral line value | X (k ₀) |, inferior big spectral line value | X (k ₀+ r) |, the corresponding signal frequency k of maximum spectral line value ₀And the value of translation coefficient r, specifically comprise the steps:

Step 2-1, definition input signal x (n) does the FFT computing to x (n);

Wherein, $x\left(n\right)={\mathrm{ae}}^{j(2\mathrm{\π}{f}_c\mathrm{n\Δt}+{\mathrm{\Φ}}_0)}+v\left(n\right)$ N=0,1, L, N-1 (1)

A is amplitude, f _cBe original frequency, Ф ₀Be first phase, Δ t is that sampling interval, N are sample number,

Real part and imaginary part is separate and all obey N (0, σ ²) distribute σ ²Be that constant is represented noise variance;

Step 2-2-1, the relatively corresponding spectral line value of all signal frequencies on the frequency spectrum;

When signal frequency was in the sampling frequency central area, the maximal value of getting the real part absolute value was as the maximum spectral line value in sampling frequency central area;

When signal frequency was in non-sampling frequency central area, the maximal value of getting the imaginary part absolute value was as the maximum spectral line value in non-sampling frequency central area;

Step 2-2-2, relatively the maximum spectral line value of sampling frequency central area and the maximum spectral line value of non-sampling frequency central area are got the maximum spectral line value of big person as entire spectrum;

Step 2-2-3 gets the corresponding signal frequency of maximum spectral line value as k ₀

Step 2-2-4, repeating step 2-2-1 is to definite big spectral line value of step 2-2-2;

Step 2-3 confirms the value of translation coefficient r, when | X (k ₀+ r) |＜| X (k ₀-r) | the time, r=-1, otherwise, r=1;

Step 3 is calculated the frequency interpolation δ of each road input signal respectively according to following method ₁, according to δ ₁Span confirm the final frequency measured value Specifically comprise the steps:

Step 3-1 adopts following formula calculated rate interpolation δ ₁:

${\mathrm{\&delta;}}_1=\frac{\left|X({\mathrm{<figure-callout\; id="0"\; label="k"\; filenames="HDA0000072484610000012.png,HDA0000072484610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_0+r)\right|}{\left|X({\mathrm{<figure-callout\; id="0"\; label="k"\; filenames="HDA0000072484610000012.png,HDA0000072484610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_0+r)\right|+\left|X\left(k_0\right)\right|}---\left(2\right)$

Step 3-2 works as δ ₁During ∈ [1/3,1/2], obtain frequency values with the Rife method

Remember that this frequency values is the final frequency measured value

Step 3-3 works as δ ₁During ∈ [0,1/3], with after the parallel moving of signal r/3 times sampling frequency with Rife method calculated rate interpolation δ ₁Then according to recomputating the frequency interpolation δ that obtains ₁Carry out following operation:

Step 3-3-1 works as δ ₁During ∈ [1/3,1/2], obtain frequency measurement with the Rife method

Deduct r/3 times of sampling frequency as the final frequency measured value with frequency measurement again

Step 3-3-2 works as δ ₁During ∈ [0,1/3],, return step 3-3 with the r negate;

Step 4, the comparison step 3 calculated the final three-way input signal frequency measurement value

maximum value as the last measurement frequency.

The application of the FPGA chip rapid precision frequency measurement method, the step 3 by Rife frequency measurement values obtained by the method

is calculated as follows:

$\stackrel{\&OverBar;}{f_c}=\frac{1}{T}({\mathrm{<figure-callout\; id="0"\; label="k"\; filenames="HDA0000072484610000012.png,HDA0000072484610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_0+r\frac{\left|X({\mathrm{<figure-callout\; id="0"\; label="k"\; filenames="HDA0000072484610000012.png,HDA0000072484610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_0+r)\right|}{\left|X\left(k_0\right)\right|+\left|X({\mathrm{<figure-callout\; id="0"\; label="k"\; filenames="HDA0000072484610000012.png,HDA0000072484610000022.png"\; state="\{\{state\}\}">k</figure-callout>}}_0+r)\right|})---\left(3\right)$

Wherein, FFT T=transformation period Δ t*N.

Now Rife method and MRife method are done following emulation experiment: seeing that the Rife method is through confirming the frequency spectrum maximal value to FFT operation result delivery; The real part absolute value and the imaginary part absolute value of MRife method comparison FFT operation result are confirmed the frequency spectrum maximal value, in MATLAB, Rife method and MRife method are done MonteCaro emulation respectively.

The emulation of Rife method and MRife method survey frequency root-mean-square error when different signal to noise ratio (S/N ratio): according to the input signal of formula (1) definition, each parameter is set to: signal length N=256, signal amplitude

(SNR is an input signal-to-noise ratio), signal frequency f _c=f _s/ 4+ Δ f _c, Δ f _cGet [f _s/ (2N), f _s/ (2N)] and interval equally spaced 80 Frequency points, sample frequency f _s=200MHz, signal initial phase Ф ₀Get [0,2 π] interval equally distributed random number, the noise average is 0, variances sigma ²=0.5.Each Frequency point is done 1000 MonteCaro emulation.The simulation curve comparison diagram of Rife method and MRife method survey frequency root-mean-square error when SNR=-3dB, SNR=0dB, SNR=3dB such as Fig. 3, Fig. 4, shown in Figure 5.CLRB among the figure (carat Mei-Luo circle) is confirmed by formula (5).

$\mathrm{CLRB}=\sqrt{\frac{12{\mathrm{\&sigma;}}^2}{a^2{T}^{2}N(N^2-1)}}/\left(2\mathrm{\&pi;}\right)---\left(5\right)$

The present invention adopts the EP1S25F780 C5 chip in the STRATIX Series FPGA device of ALTERA company; In QuartusII4.2, programme, comprehensively, placement-and-routing and sequential emulation; The FFT module can be accomplished design through the parameter of the configuration ALTERA FFT of company nuclear, and other modules adopt the VHDL hardware description language to realize.

In QuartusII software, set up engineering, each module that designs is added in the engineering, the resource operating position after comprehensive, placement-and-routing is as shown in table 1.Thus it is clear that, use the EP1S25F785C5 chip can be realized parallel organization in a slice FPGA MRife method.Though the logical block and the DSP module that consume are all many, the processing mode of this parallel, flowing water has been accelerated processing speed, has improved the real-time of system, is adapted at radar, electronic countermeasure etc. to the very high field of processing real-time requirement.

Table 1MRife method FPGA resource consumption table

Processing status	Fitting Successful
		Chip name	MRife
Device for compilation	EP1S25F780C5
		Total logic elements	19，764/25，660(77％)
Total pins	105/598(17％)
		Total memory bits	120，832/l，944，576(6％)
DSP block 9-bit elements	70/80(87％)
		Total PLLs	0/6(0％)

Frequency measuring system to advancing improved FGPA chip formation is done following sequential emulation:

In QuartusII software, carry out placement-and-routing, the delay model that obtains designing generates the required vector file (* .vec file) of emulation with MATLAB software again.System input signal is that two band frequencies are respectively 65.1/N*f _sAnd 109.5/N*f _sSingle-tone complex signal (N=256, f _s=200MHz), f _sBe sample frequency.Two segment signal length all are 256 points, SNR=-3dB.Data_real_in, data_imag_in represent the real part and the imaginary part of input signal, bit wide 16bit respectively.Clock signal of system is clk, and reset signal is reset.System output signal is k ₀, r and deta, wherein k ₀Consistent with in the implication of r and (2) formula, the high and low level representative of r is just being got, is getting negative.The implication of deta is the final correction of modified R ife method, and bit wide is 16bit, is used for representing 16 no symbol fractional fixed points.The sequential simulation waveform of MRife method as shown in Figure 6, the amplification figure at time ruler place is as shown in Figure 7.Sequential emulation shows, the design highest running speed can reach 200MHz, and data are not piled up, and can realize walking abreast, flowing water, handle in real time.Because the influence of quantization error when hardware is realized, frequency measurement accuracy is a little less than the Matlab simulation result.The theoretical value corresponding with Fig. 7, Matlab simulation result, FPGA operation result are respectively: 65.1 (109.5), 65.131 (109.528), 65.134 (109.529), and unit all is 1/N*f _s, the second section emulated data of digitized representation in the bracket.

Visible by simulation result;

(1) the MRife method can be improved the performance of original Rife method, and improvement effect is very good;

(2) root-mean-square error of MRife method (RMSE) variation is very little, and this relatively the real part absolute value and the imaginary part absolute value of FFT operation result confirm that the peaked method of frequency spectrum is effective and feasible;

(3) when SNR＞0dB, can both be in whole sampling frequency scope near CLRB.

(4) logical block and the DSP module that consume of this method is all many, but the processing mode of this parallel, flowing water has been accelerated processing speed, has improved the real-time of system, is adapted at radar, electronic countermeasure etc. to handling the very high field of real-time requirement.

Claims (2)

1. a method of using the quick high accuracy frequency measurement of fpga chip realization is characterized in that comprising the steps:

Step 1, input signal is divided into parallel three the tunnel, first via input signal translation-1/3FFT sampling frequency, the second road input signal translation 1/3FFT sampling frequency, the Third Road input signal is not done frequency displacement;

Step 2 is done the FFT computing to each road input signal, confirms maximum spectral line value | X (k ₀) |, inferior big spectral line value | X (k ₀+ r) |, the corresponding signal frequency k of maximum spectral line value ₀And the value of translation coefficient r, specifically comprise the steps:

Step 2-1, definition input signal x (n) does the FFT computing to x (n);

Wherein, $x\left(n\right)={\mathrm{ae}}^{j(2\mathrm{\&pi;}{f}_c\mathrm{n\&Delta;t}+{\mathrm{\&Phi;}}_0)}+v\left(n\right)$ N=0,1, L, N-1 (1)

A is amplitude, f _cBe original frequency, Ф ₀Be first phase, Δ t is that sampling interval, N are sample number,

Real part and imaginary part is separate and all obey N (0, σ ²) distribute σ ²Be that constant is represented noise variance;

Step 2-2-1, the relatively corresponding spectral line value of all signal frequencies on the frequency spectrum;

When signal frequency was in the sampling frequency central area, the maximal value of getting the real part absolute value was as the maximum spectral line value in sampling frequency central area;

When signal frequency was in non-sampling frequency central area, the maximal value of getting the imaginary part absolute value was as the maximum spectral line value in non-sampling frequency central area;

Step 2-2-2, relatively the maximum spectral line value of sampling frequency central area and the maximum spectral line value of non-sampling frequency central area are got the maximum spectral line value of big person as entire spectrum;

Step 2-2-3 gets the corresponding signal frequency of maximum spectral line value as k ₀

Step 2-2-4, repeating step 2-2-1 is to definite big spectral line value of step 2-2-2;

Step 2-3 confirms the value of translation coefficient r, when | X (k ₀+ r) |＜| X (k ₀-r) | the time, r=-1, otherwise, r=1;

Step 3, were calculated according to the following method for each input signal frequency interpolation δ1, δ1 ranges according to the frequency measurement to determine the final value

specifically includes the following steps:

Step 3-1 adopts following formula calculated rate interpolation δ ₁:

${\mathrm{\&delta;}}_1=\frac{\left|X(k_0+r)\right|}{\left|X(k_0+r)\right|+\left|X\left(k_0\right)\right|}---\left(2\right)$

Step 3-2 works as δ ₁During ∈ [1/3,1/2], obtain frequency values with the Rife method

Remember that this frequency values is the final frequency measured value

Step 3-3 works as δ ₁During ∈ [0,1/3], with after the parallel moving of signal r/3 times sampling frequency with Rife method calculated rate interpolation δ ₁Then according to recomputating the frequency interpolation δ that obtains ₁Carry out following operation:

Step 3-3-1 works as δ ₁During ∈ [1/3,1/2], obtain frequency measurement with the Rife method

Deduct r/3 times of sampling frequency as the final frequency measured value with frequency measurement again

Step 3-3-2 works as δ ₁During ∈ [0,1/3],, return step 3-3 with the r negate;

Step 4 Step 3 comparing the calculated final three input signal frequency measurement value

maximum value as the last measurement frequency.

(2) as claimed in claim 1, wherein the FPGA chip to achieve rapid precision frequency measurement, characterized in that: said step 3 by Rife frequency measurement values obtained by the method

is calculated as follows:

$\stackrel{\&OverBar;}{f_c}=\frac{1}{T}(k_0+r\frac{\left|X(k_0+r)\right|}{\left|X\left(k_0\right)\right|+\left|X(k_0+r)\right|})---\left(3\right)$

Wherein, FFT T=transformation period Δ t*N.

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