CN103794598B - Silicon hole test domain, test structure, preparation method and method for measurement - Google Patents

Silicon hole test domain, test structure, preparation method and method for measurement Download PDF

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CN103794598B
CN103794598B CN201410071731.5A CN201410071731A CN103794598B CN 103794598 B CN103794598 B CN 103794598B CN 201410071731 A CN201410071731 A CN 201410071731A CN 103794598 B CN103794598 B CN 103794598B
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silicon hole
silicon
lead
module
array
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CN103794598A (en
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林宏
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Shanghai IC R&D Center Co Ltd
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Shanghai Integrated Circuit Research and Development Center Co Ltd
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Abstract

The invention provides a kind of silicon hole test domain, silicon hole test structure and preparation method thereof and the method for measurement of silicon hole resistance, in silicon hole test structure, it is provided with mutually in the first silicon hole array and the second silicon hole array of specular distribution in front side of silicon wafer, there is layer of metal layer in silicon chip back side deposition, by the use of the metal level at the back side as the connection resistance between two silicon hole arrays, realize only can carry out the measurement of silicon hole resistance in the positive driving current that applies；Simultaneously, thinking is shunted using equiarm, the silicon hole in each silicon hole array is connected with corresponding test module respectively using identical lead, it ensure that the electric current of each branch road is identical, so as to effectively evade the influence of lead resistance, the accuracy in measurement of silicon hole resistance is improved, is advantageous to the application and exploitation of the silicon hole in later stage.

Description

Silicon hole test domain, test structure, preparation method and method for measurement
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of silicon hole test domain, silicon hole test structure, silicon The preparation method of through hole test structure and the method for measurement of silicon hole resistance.
Background technology
Physics pole is reached as ic manufacturing technology enters 28nm and following technology generation, traditional planar structure Limit, the introducing of new material and new technology bring huge R ＆ D Cost and application charges, and industry generally starts to use 3-D technology. On the one hand, integrated circuit manufacturing industry leaders start FINFET three-dimensional structures being applied to metal-oxide-semiconductor, and semiconductor channel is similar to one Bar mountain range, grid uniform fold dramatically increase control ability of the grid to raceway groove on " mountain range ", with this, effectively improve migration Rate, threshold voltage is reduced, improve device performance.On the other hand, chip maker and encapsulation manufacturer are all being directed to three-dimensional mutually Next, two technology generations integration density can be achieved in cost controlled range, determine from economics for even technological development, three-dimensional interconnection Rule continues to follow Moore's Law to keep technical advance.
Silicon hole TSV technology is one of core of three-dimensional interconnection technology, i.e., etches deep hole in silicon chip surface, is subsequently filled Medium and metal, then be directly interconnected by silicon hole from silicon chip back side and another piece of silicon chip, significantly shorten metal connecting line Length, RC retardation ratio is reduced, while chip package size can also be reduced.The standard process flows of silicon hole technology are silicon hole Dry etching, wet-cleaning, cvd dielectric layer, barrier deposition, inculating crystal layer deposition, copper plating, chemically mechanical polishing.Due to collection Into density requirements, the aperture of silicon hole technology is typically in 5~50um, and depth is in 50~300um.Therefore, the depth of silicon hole technology Wide ratio can reach 10:More than 1.
, it is necessary to be measured to the resistance of silicon hole, so as to the application of the silicon hole in later stage after silicon hole etching is carried out Exploitation.However, because the size of silicon hole is larger, the resistance of silicon hole typically at 0.001~0.05 ohm, this with after copper-connection The leadthrough module resistance of road technique（Typically in 0.02~0.2 ohm/module area）Close, the influence of lead resistance can not neglect Slightly.Silicon hole must enter row metal connection from front and back respectively, could realize three-dimensional interconnection, but related process may introduce Surface defect or copper oxidation, and the Ohmic contact situation between copper and other metals can all cause silicon hole contact resistance Increase.As can be seen here, lead resistance and contact resistance can have a strong impact on the measurement of silicon hole resistance；Therefore, in contact resistance not In the case of evitable, if it is possible to evade out lead resistance, it will effectively improve the accuracy in measurement of silicon hole resistance.
The content of the invention
In order to overcome problem above, the present invention is intended to provide a kind of silicon hole test domain, silicon hole test structure, silicon lead to The preparation method of hole test structure and the method for measurement of silicon hole resistance, so as to effectively evade lead resistance, improve silicon hole The accuracy in measurement of resistance.
The present invention provides a kind of silicon hole test domain, its by silicon hole lithography layer domain and test module and lead light The domain for carving layer is superimposed to be formed, wherein,
The domain of the silicon hole lithography layer includes the first silicon hole array pattern and second of mirror images each other Silicon hole array pattern；
The domain of the test module and lead lithography layer includes：First test module figure of mirror images each other With some the first lead figures and some the second lead figures of the second test module figure, each other mirror images； The first test module figure includes the first electric current and applies module figure and first voltage test module figure, and described second surveys Die trial block graphics includes the second electric current and applies module figure and second voltage test module figure；Wherein,
Each silicon hole figure in the first silicon hole array pattern applies module figure with first electric current and led to Cross the first lead figure to be connected, any one silicon hole figure in the first silicon hole array pattern and described the One voltage test module figure is connected by the first lead figure；
Each silicon hole figure in the second silicon hole array pattern applies module figure with second electric current and led to Cross the second lead figure to be connected, any one silicon hole figure in the second silicon hole array pattern and described the Two voltage test module figures are connected by the second lead figure；
The first lead figure is identical with the second lead figure.
Preferably, the silicon hole test domain also includes contact module figure, the contact module figure and the silicon Via hole image, which corresponds, to be set, and the center of the contact module figure is aligned one by one with the center of circle of the silicon hole figure, often The individual contact module figure is used to a silicon hole figure with the corresponding lead figure being connected.
Preferably, the contact module figure is arranged in the layout patterns of the test module and lead lithography layer.
Preferably, the described first or second silicon hole array pattern be Triangular array figure, quadrate array figure, Rhombus array pattern, fan-shaped array pattern, the hexagonal array figure being centrosymmetric or the array of figure arranged in isosceles trapezoid Shape.
The present invention also provide it is a kind of using above-mentioned silicon hole beta version figure into silicon hole test structure, it includes：
Have mutually in the first silicon hole array and the second silicon hole array of specular in front side of silicon wafer；
There is layer of metal layer in silicon chip back side, for the first silicon hole array to be neutralized into the second silicon hole battle array Silicon hole in row is connected with low resistance；
Also have mutually in the first test module and the second test module of specular, mutually in specular in front side of silicon wafer Some first leads and some second leads；First test module includes the first electric current and applies module and the first electricity Test module is pressed, second test module includes the second electric current and applies module and second voltage test module；Wherein,
Each silicon hole in the first silicon hole array applies module with first electric current and drawn by described first Line is connected, and any one silicon hole in the first silicon hole array and the first voltage test module pass through described the One lead is connected；
Each silicon hole in the second silicon hole array applies module with second electric current and drawn by described second Line is connected, and any one silicon hole in the second silicon hole array and the second voltage test module pass through described the Two leads are connected；
Some first leads are identical with some second leads.
Preferably, the silicon hole test structure also includes contact module, and the contact module and the silicon hole are one by one It is correspondingly arranged, the center of the contact module is aligned one by one with the center of circle of the silicon hole, and each contact module is used for will One silicon hole, and corresponding first lead or second lead are attached.
Preferably, the described first or second silicon hole array is Triangular array, quadrate array, rhombus array, fan Shape array, the hexagonal array being centrosymmetric, the array arranged in isosceles trapezoid.8th, it is a kind of using described in claim 1 Silicon hole tests domain to prepare the method for silicon hole test structure described in the claims 5, it is characterised in that including successively Three silicon hole lithography layer, test module and lead lithography layer and silicon chip back side metal level processes are formed, wherein,
Forming the process of the silicon hole lithography layer includes：
Step S01：Layer of metal diffusion impervious layer is deposited in the front side of silicon wafer；
Step S02：Under the protection on the barrier layer, the domain using the silicon hole lithography layer passes through photoetching and etching Technique forms mutually the first silicon hole array in specular and the second silicon hole array in front side of silicon wafer；
Step S03：Barrier layer is sequentially depositing into the first silicon hole array and the second silicon hole array and is filled out Fill metal；
Step S04：Planarization process is carried out to the top surface of the metal of the filling, until the front side of silicon wafer surface Residual without the metal；
Forming the process of the test module and lead lithography layer includes：
Step S05：One layer of dielectric layer is deposited in the front side of silicon wafer；
Step S06：The domain of the test module and lead lithography layer is aligned with the domain of the silicon hole lithography layer, The front side of silicon wafer formed in the through hole test structure mutually in first test module of specular and described the Two test modules, and mutually some first leads in specular and some second leads；
Step S07：First test module, second test module, first lead and described second are drawn Line enters row metal interconnection process；
Forming the process of the silicon chip back side metal level includes：
Step S08：Reduction process is carried out to the silicon chip back side, until the metal of each silicon hole bottom is exposed Out；
Step S09：In silicon chip back side deposition layer of metal layer, the metal level and the first silicon hole array It is in contact with each silicon hole in second silicon array, so as to form the silicon hole test structure.
Preferably, the step S06, including：Using the test module and the domain of lead lithography layer, lead to the silicon The domain alignment of hole lithography layer, through photoetching and etching technics, on the front side of silicon wafer, and in the top surface of the silicon hole Contact module is formed, the center and the center of circle of the top surface of the silicon hole of the contact module align, in the silicon chip Front forms first test module and second test module, and with it is described contact module be connected it is described some The lead of bar first and some second leads；Then, described metal interconnection process is carried out.
Present invention also offers a kind of method for measurement of silicon hole resistance, and it uses described silicon hole test structure to carry out Measure, specifically include following steps：
Step A01：The first described electric current is applied into module and the second described electric current applies module and is connected with current source Connect, described first voltage test module and described second voltage test module are connected with voltage tester instrument；
Step A02：Using formula R=NU/2I-R'/2, the resistance of single silicon hole is calculated, wherein, N is described the The quantity of one silicon hole array or the silicon hole in the second silicon hole array, I are the output current of the current source, and U is The voltage that the voltage tester instrument is measured, R' are the resistance of the metal layer on back, and R is the resistance of the single silicon hole.
Silicon hole test domain, silicon hole test structure, the preparation method of silicon hole test structure and the silicon of the present invention The method for measurement of through hole resistance, design the first silicon hole array of mirror images each other in front side of silicon wafer and the second silicon leads to Hole array, why design in symmetrical two silicon hole arrays, be due in the case where electrical testing condition is limited, it is difficult to Realize that applying voltage simultaneously from the front and back of silicon chip measures, then, to the silicon hole battle array of two speculars each other Corresponding two silicon holes in row apply voltage, and metal layer on back is equivalent to two mirror images each other as conducting resistance Symmetrical silicon hole series connection, so, only need to apply voltage in front side of silicon wafer can carry out the measurement of silicon hole resistance.
The mentality of designing shunted with reference to the equiarm of analog circuit, for the first or second silicon hole array, by silicon hole with Certain geometry arrangement, is applied each silicon hole in silicon hole array with electric current using the lead of equal length and width Module is added to be connected, because the lead of each silicon hole is identical, then each lead resistance is also identical, then passes through the electricity of each branch road Stream is also identical；Recycle lead that any one silicon hole in silicon hole array is connected with voltage test module, due to drawing Line resistance relative to test voltage U internal resistance very little, it is believed that there is no partial pressure substantially in lead resistance, so, measure Voltage is closer to the virtual voltage of silicon hole, and therefore, the present invention can effectively evade lead resistance, so as to improve silicon hole electricity The accuracy in measurement of resistance.
Brief description of the drawings
Fig. 1 is that the silicon hole of embodiments of the invention one tests the schematic diagram of layout patterns
Fig. 2 is the schematic diagram of the layout patterns of the silicon hole lithography layer of embodiments of the invention one
Fig. 3 be embodiments of the invention one test module and lead lithography layer layout patterns schematic diagram
Fig. 4 is the equivalent circuit schematic of the silicon hole test structure of embodiments of the invention one
Fig. 5 is the schematic flow sheet of the preparation method of the silicon hole test structure of embodiments of the invention one
Fig. 6 is that the silicon hole of embodiments of the invention two tests the schematic diagram of layout patterns
Fig. 7 is that the silicon hole of embodiments of the invention three tests the schematic diagram of layout patterns
Fig. 8 is that the silicon hole of embodiments of the invention four tests the schematic diagram of layout patterns
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art Cover within the scope of the present invention.
As it was previously stated, when actual test silicon hole, the resistance measurement of contact resistance and lead resistance to silicon hole Influence is very big, if the deviation of silicon hole resistance measurement is very big, it will seriously affect development and application of the later stage to silicon hole. Therefore, it is necessary to when silicon hole measurement is carried out, the increase of contact resistance can be effectively prevented from and evade lead resistance.This Invention with this end in view, have devised silicon hole test structure, prepare the domain of the silicon hole test structure, using the domain come Silicon hole test structure method is prepared, and the method for measurement of silicon hole resistance is carried out using silicon hole test structure.The present invention In, the silicon hole array designed can be Triangular array, quadrate array, rhombus array, fan-shaped array, in center pair The hexagonal array of title or the array etc. in isosceles trapezoid arrangement.
Because the resistance and lead resistance of silicon hole approach, the influence of lead resistance be can not ignore, if each lead is electric Resistance is differed, and measurement result will be impacted；Present invention employs the equiarm diversion design thinking of analog circuit, and combine and open You hinder test philosophy by message, and each silicon hole and each test module are connected with identical lead, can so ensure to flow through The current density of each silicon hole is identical, has effectively evaded the influence of lead resistance.
Meanwhile in one layer of thicker metal level of backside deposition of silicon chip, the resistance of the metal level relative to silicon hole electricity Resistance is very low so that two silicon hole arrays can be interconnected from silicon chip back side with low-down resistance, can so ensure Back side resistance will not occupy excessive partial pressure, and make it that the partial pressure measurement in silicon hole is inaccurate；And back side resistance keeps one Cause, also ensure that each branch current is identical, so as to effectively evade the influence of lead resistance, and thus have devised silicon hole The geometrized structure graph and test module and lead distribution map of array.
During traditional test, apply the problem of voltage is difficult to realize simultaneously in front side of silicon wafer and the back side, this Invention front side of silicon wafer design the silicon hole array of the distribution of specular each other, the test module of specular distribution each other and Lead, so, it is equivalent to the silicon hole bottom that should be contacted with driving current from silicon chip back side to be transferred to front side of silicon wafer, In the case where ensureing that design rule is constant, it is only necessary to connect current source on two symmetrical silicon hole arrays of front side of silicon wafer With voltage tester instrument.
In the preparation technology of silicon hole test structure is carried out using the silicon hole of present invention test domain, using two step light Quarter, process completed silicon hole layer, test module and the preparation of trace layer；In this preparation process, it can be, but not limited to using single Or prepared by dual damascene process method, the present invention does not make any requirement to this.
Embodiment one
Below in conjunction with accompanying drawing 1-5 to the present invention the present embodiment silicon hole test domain, silicon hole test structure and its The method for measurement of preparation method and silicon hole resistance is described in further detail.Wherein, Fig. 1 is embodiments of the invention one Silicon hole test layout patterns schematic diagram, Fig. 2 is the layout patterns of the silicon hole lithography layer of embodiments of the invention one Schematic diagram, Fig. 3 be embodiments of the invention one test module and lead lithography layer layout patterns schematic diagram, Fig. 4 for this The equivalent circuit schematic of the silicon hole test structure of the embodiment one of invention, Fig. 5 are the silicon hole of embodiments of the invention one The schematic flow sheet of the preparation method of test structure.It should be noted that accompanying drawing is using very simplified form, using non-accurate Ratio, and only to it is convenient, lucidly reach and aid in illustrating the purpose of the embodiment of the present invention.
First, domain is tested to the silicon hole of the present embodiment with reference to accompanying drawing 1-3 and silicon hole test structure elaborates.
Refer to accompanying drawing 1, the silicon hole test domain in the present embodiment includes：The domain of silicon hole lithography layer, and survey The domain of die trial block and lead lithography layer, the silicon hole that the superposition of the two domains can obtain in the present embodiment test domain.
The domain of silicon hole lithography layer, referring to Fig. 2, the first silicon hole array pattern including mirror images each other 1 and the second silicon hole array pattern 2.It should be noted that in the domain of silicon hole lithography layer in the present invention, mirror image pair each other The the first silicon hole array pattern and the second silicon hole array pattern of figure can be, but not limited to be referred to as Triangular array, may be used also Think quadrate array figure, rhombus array pattern, fan-shaped array pattern, the hexagonal array figure being centrosymmetric or in etc. Array pattern of the trapezoidal arrangement of waist etc..In the present embodiment, the first silicon hole array pattern 1 and the second silicon hole array pattern 2 are equal In Triangular array figure, by taking the first silicon hole array pattern 1 as an example, silicon hole V1, V2 and V3 arrange in equilateral triangle, V1 With V2 in same X-direction, it can be appreciated that V1 and V2 center of circle spacing is V1 and V3, the center of circle of V2 and V3 in the Y-axis direction 2 times of spacing；In the present invention, the diameter of silicon hole can be 5-20um, can adjust silicon according to different silicon hole sizes Center of circle spacing between through hole；In the present embodiment, a diameter of 5um of silicon hole, then between the center of circle in V1 and V2 horizontal direction Away from can be 20um, V1 and V2 vertical direction on center of circle spacing can be 0um；V1 and V3, V2 and V3 in the vertical directions Center of circle spacing be 10um, center of circle spacing in the horizontal direction is also 10um.Due to the second silicon hole array pattern 2 and One silicon hole array pattern 1 is in mutually mirror images, then the arrangement of the geometry of the second silicon hole array pattern 2 and size in The arrangement of silicon hole figure in first silicon hole array pattern 1 is in specular, here to the second silicon hole array pattern 2 not Repeat again.
Meanwhile first silicon hole array pattern 1 and the second silicon hole array pattern 2 spacing it is bigger, the gold of silicon chip back side Belong to crosstalk with regard to smaller, but due to the limitation of chip area, spacing between the two can not possibly be infinitely great, in the present embodiment, The spacing of first silicon hole array pattern 1 and the second silicon hole array pattern 2 can be 50um, in figure between V3 and V4 Distance.
The domain of test module and lead lithography layer, referring to Fig. 3, including：First test of mirror images each other Module figure and the second test module figure, each other some first lead figures 3 of mirror images and some second leads Figure 4；First test module figure includes the first electric current and applies module figure 5 and first voltage test module figure 6, and second surveys Die trial block graphics includes the second electric current and applies module figure 7 and second voltage test module figure 8；
In the present embodiment, contact module figure 9 is also included in the domain of test module and lead lithography layer, contacts module Silicon hole figure in figure 9 and silicon hole array pattern 1 and 2, which corresponds, to be set, the center of contact module figure 9 and these The center of circle of silicon hole figure is aligned one by one, and each module figure 9 that contacts is used for a silicon hole figure and corresponding drawn Line connects.In the present invention, contact module figure should cover silicon hole figure, and the size of contact module figure then should be greater than The size of silicon hole figure, due to a diameter of 5um of silicon hole figure in the present embodiment, then contact the length of module figure and width can To be 6um.In the present invention, if contactless module figure, prepared silicon hole test structure still may be used in domain Contact module figure is set to be more beneficial for contact of the lead with silicon hole to be tested, in the present embodiment.
Each silicon hole figure V1, V2 and V3 in first silicon hole array pattern 1, apply module figure with the first electric current 5 are connected by the lead of the first lead figure 3, and any one in silicon hole figure V1, V2 and V3 passes through the first lead figure One lead of shape 3 is connected with first voltage test module figure 6；
Each silicon hole figure V4, V5 and V6 in second silicon hole array pattern 2, apply module figure with the second electric current 7 are connected by the lead of the second lead figure 4, and any one in silicon hole figure V4, V5 and V6 passes through the second lead figure One lead of shape 4 is connected with second voltage test module figure 8.
Specifically, in the present embodiment, the number of the first lead figure 3 is four, wherein, three lead-in wires are respectively by silicon hole Figure V1, V2 apply module figure 5 with V3 and the first electric current and are connected, and a lead surveys silicon hole figure V2 and first voltage Die trial block graphics 6 connects；The number of second lead figure 4 is four, wherein, three lead-in wires are respectively by silicon hole figure V4, V5 apply module figure 7 with V6 and the second electric current and are connected, and silicon hole figure V6 and second voltage are tested mould by a lead Block graphics 8 connects.
Each bar lead figure all same in the present invention, in the present embodiment, the first lead figure 3 and the second lead figure 4 be identical lead figure.It so may insure that it has identical resistance, so as to evade lead resistance to silicon hole electricity Hinder the influence measured.In the present invention, electric current, which applies module, to be located on the center line of silicon hole array, then in the present embodiment, Electric current applies module 5 and 7 and is located on the center line of Triangular array；In the present invention, each bar lead and each test module Design rule need to be compatible with copper wiring technique, then lead graphic width should be less than 12um, and the size of test module figure should be less than 100um；In the present embodiment, the width of each bar lead figure is 2um, and the length and width of each test module figure are 80um.
It should be noted that the bar number of lead figure is connected by test module figure with silicon hole figure in the present invention Path determines, such as, in the present embodiment, using the first silicon hole array pattern and the first lead figure being attached thereto as Example, each own paths of silicon hole figure V1, V2 and V3 are communicated to the first electric current and apply module figure, and silicon hole figure V2 There are a paths to first voltage test module figure, so add up one and share 4 paths, in the present embodiment, then claim have 4 Bar the first lead figure；Because the length of this 4 paths is identical and width is also identical, the length of this 4 the first lead figures It is also identical to spend identical and width.Accordingly, the second silicon hole array pattern and the second lead figure being attached thereto also have phase Same rule, and the first lead figure and the second lead figure are identical, repeat no more here.
Silicon hole test structure in the present embodiment, employ above-mentioned silicon hole and test domain through photoetching and etching technics system Standby to form, it includes：
Have mutually in the first silicon hole array and the second silicon hole array of specular arrangement in front side of silicon wafer；Each silicon Metal is filled with through hole, and the resistivity of the filling metal is relatively low to ensure good electric conductivity, it is preferred that the filling is golden Category can be copper or silver；In view of production cost, it is preferred that metallic copper can be selected as packing material.
It should be noted that the first silicon hole array and the second silicon hole array mutually arranged in specular of the present invention It can be, but not limited to as Triangular array, can also be quadrate array, rhombus array, fan-shaped array, be centrosymmetric Hexagonal array or the array etc. in isosceles trapezoid arrangement.In the present embodiment, the first silicon hole array and the second silicon hole array For Triangular array.By taking the first silicon hole array as an example, the diameter of silicon hole can be 5-20um, can be according to different silicon Clear size of opening adjusts the center of circle spacing between silicon hole；In the present embodiment, a diameter of 5um of silicon hole, Triangular array The length of side can be 20um, that is to say the center of circle spacing of three silicon holes between any two is 20um.
There is layer of metal layer in silicon chip back side, for the first silicon hole array to be neutralized to the in the second silicon hole array It is in parallel with low resistance between the silicon hole of one silicon hole array and the silicon hole of corresponding second silicon hole array；The metal Layer is deposited on the back side of silicon chip, is connected with the silicon hole bottom of the first silicon hole array and the second silicon hole array；The metal level Material and thickness can be selected according to actual conditions, thickness should be greater than 3 microns, for example the material of metal level can be that silver closes Gold, thickness are 5 microns etc., the invention is not limited in this regard.
Also have mutually in the first test module and the second test module of specular arrangement, mutually in mirror image in front side of silicon wafer Some first leads and some second leads of symmetry arrangement；First test module includes the first electric current and applies module and the One voltage test module, the second test module include the second electric current and apply module and second voltage test module；
Each silicon hole figure in first silicon hole array applies module with the first electric current and is connected by the first lead, Any one silicon hole in first silicon hole array is connected with first voltage test module by the first lead；
Each silicon hole in second silicon hole array applies module with the second electric current and is connected by the second lead, and second Any one silicon hole in silicon hole array is connected with second voltage test module by the second lead；
Specifically, in the present embodiment, the first lead is four, wherein, three lead-in wires are respectively by the first silicon hole array Three silicon holes and the first electric current apply module and be connected, a lead leads to any one silicon in the first silicon hole array Hole connects with first voltage test module；Second lead is four, wherein, three lead-in wires are respectively by the second silicon hole array In three silicon holes and the second electric current apply module and be connected, a lead is by any one silicon in the second silicon hole array Through hole connects with second voltage test module.
In the present embodiment, silicon hole test structure also include contact module, contact module with it is each in silicon hole array Individual silicon hole figure, which corresponds, to be set, and is contacted the center of module and is aligned one by one with the center of circle of these silicon holes, each contacts mould Block is used to a silicon hole and the first corresponding lead or the second lead being attached.In the present invention, contact module should be covered Cover silicon hole, the size for contacting module then should be greater than the size of silicon hole, due in the present embodiment silicon hole it is a diameter of 5um, then it can be 6um to contact the length of module and width.In the present invention, it is prepared if contactless module in domain Silicon hole test structure still can be tested, and set contact module to be more beneficial for lead and silicon hole in the present embodiment Contact.
Each bar lead all same in the present invention, in the present embodiment, the first lead 3 and the second lead 4 are identical Lead.It so may insure that it has identical resistance, so as to evade the influence that lead resistance measures to silicon hole resistance.This In invention, electric current, which applies module, to be located on the center line of silicon hole array, then in the present embodiment, electric current applies module 5 and 7 On the center line of Triangular array；In the present invention, the design rule of lead and test module need to be simultaneous with copper wiring technique Hold, then wire widths should be less than 12um, and test module size should be less than 100um；In the present embodiment, the width of the first and second leads Spend for 2um, the length and width of each test module are 80um.
Below in conjunction with accompanying drawing 5, the preparation method of the silicon hole test structure of the present embodiment is elaborated.
In the present embodiment, domain is tested to prepare the method for above-mentioned silicon hole test structure using above-mentioned silicon hole, including Sequentially form：Silicon hole lithography layer, test module and lead lithography layer and three processes of silicon chip back side metal level, wherein,
Forming the process of silicon hole lithography layer includes：
Step S01：Layer of metal diffusion impervious layer is deposited in front side of silicon wafer；
Specifically, the material on barrier layer here can be, but not limited to can be, but not limited to for silicon nitride, the method for deposition Can also be sputtering method etc. for chemical vapour deposition technique.
Step S02：Under the protection on barrier layer, using the domain of silicon hole lithography layer by photoetching and etching technics in silicon Piece front is formed mutually in the first silicon hole array and the second silicon hole array of specular distribution；
Specifically, in the present embodiment, the design parameter of photoetching and etching technics can be set according to actual process requirement, The arrangement of the first silicon hole array and the second silicon hole array that are formed is identical with above-mentioned silicon hole test structure, This is repeated no more.
Step S03：Barrier layer and filling metal are sequentially depositing into the first silicon hole array and the second silicon hole array；
Step S04：Planarization process is carried out to the metal top surface of filling, until front side of silicon wafer surface is residual without metal Stay；
Specifically, in the present embodiment, filling metal can be, but not limited to as metallic copper, and step S03 and step S04's is whole Process can be, but not limited to include：Cvd dielectric layer, barrier deposition, inculating crystal layer deposition, copper plating and chemically mechanical polishing；For Realize and be electrically isolated from each other between each silicon hole, planarization process is carried out to the metal top surface of filling in the present invention, directly To front side of silicon wafer surface noresidue metal.Need exist for explanation, while being electrically isolated between realizing silicon hole, silicon hole The top of middle filling metal is not required for complete flush with front side of silicon wafer surface, it is possible to which the top for filling metal is less than silicon chip Front face surface, and due to the limitation of planarization process technique, the height of the filling metal after planarization in each silicon hole It is possible to differ.In the present invention, it can also be the less metals of other resistivity such as silver to fill metal.In the present invention, the One silicon hole array and the second silicon hole array are Triangular array, in the present embodiment, a diameter of 5um of silicon hole, just The length of side of triangular array can be 20um, and that is to say the center of circle spacing of three silicon holes between any two is 20um.
Forming the process of test module and lead lithography layer includes：
Step S05：One layer of dielectric layer is deposited in front side of silicon wafer；
Specifically, in the present embodiment, the material of the dielectric layer can be, but not limited to as silica, preferably, can be Doping silicon dioxide；The deposition of dielectric layer can be, but not limited to use chemical vapor deposition method.
Step S06：The domain of test module and lead lithography layer is aligned with the domain of silicon hole lithography layer, in silicon chip just The first test module and the second test module mutually arranged in specular that face is formed in through hole test structure, and be in mutually mirror As some first leads and some second leads of symmetry arrangement；
In the present embodiment, the first test module includes the first electric current and applies module and first voltage test module, and second surveys Die trial block includes the second electric current and applies module and second voltage test module.The test module of use and the domain of lead lithography layer In also include contact module figure；Then step S05 detailed process is：
First, the layout patterns of test module and lead lithography layer are aligned with the domain of silicon hole lithography layer；This be by Silicon hole could be formed in the layout patterns superposition of the layout patterns and silicon hole lithography layer of test module and lead lithography layer to survey Attempt shape, therefore, the alignment of two domains can be realized using the alignment process of routine here, such as, in silicon hole photoetching Overlay mark is designed in the domain and the domain of test module and lead lithography layer of layer, using overlay mark by two domains pair Standard, so as to realize each test module in above-mentioned silicon hole test structure, lead and the position relationship of silicon hole array；Need It is bright, in the present invention, to overlay mark in the domain of silicon hole lithography layer domain, test module and lead lithography layer etc. It is not intended to be limited in any, all methods for being that by alignment process can be applied in the present invention.
Then, using test module and the domain of lead lithography layer, through photoetching and etching technics, on front side of silicon wafer, and Contact module is formed in the top surface of silicon hole, the center of circle for contacting the center of module and the top surface of silicon hole aligns, The first test module and the second test module, and some first leads being connected with contacting module are formed in front side of silicon wafer With some second leads；In the present invention, the position relationship of each test module and lead and above-mentioned silicon hole test structure In position relationship it is identical.In the present embodiment, electric current applies module and is located on the center line of Triangular array.Three first are drawn Three contact modules in first silicon hole array in three silicon holes are applied module with the first electric current respectively and connected by line, One first lead contacts one in module by this three and connected with first voltage test module；Three second leads point Three contact modules in the second silicon hole array in three silicon holes are not applied into module with the second electric current to connect, one Second lead contacts one in module by this three and connected with second voltage test module；
Step S07：Enter row metal interconnection work to the first test module, the second test module, the first lead and the second lead Skill；
Specifically, in the present embodiment, the metal filled in metal interconnection process can be, but not limited to for metallic copper, metal it is mutual Even technique can be, but not limited to include：Barrier deposition, inculating crystal layer deposition, copper plating and chemically mechanical polishing.In the present embodiment The test module and lead of formation are identical with above-mentioned silicon hole test structure, to each test module and the chi of each bar lead Very little and shape repeats no more here.
Forming the process of silicon chip back side metal level includes：
Step S08：Reduction process is carried out to silicon chip back side, until the metal of each silicon hole bottom is exposed；
Step S09：Layer of metal layer is deposited in silicon chip back side, metal level and the first silicon hole array neutralize the second silicon array In each silicon hole be in contact, so as to form silicon hole test structure.
Specifically, in the present embodiment, can be, but not limited to deposit one layer of gold in silicon chip back side using physical vaporous deposition Belong to layer, the material of the metal level can be, but not limited to should be greater than 3 microns for silver alloy, the thickness of this layer of metal level, so can be with Ensure metal level resistance very little because between equivalent to two silicon hole arrays of metal layer on back and with voltage test module, Electric current applies the electric lead of the connected silicon hole of module.
In the present invention, a kind of method for measurement of silicon hole resistance is additionally provided, is characterized in employing the silicon of the present invention Through hole test structure carries out resistance measurement, next, the application of this method in the present embodiment specifically is introduced, but this is not used in limit Protection scope of the present invention processed.
In the present embodiment, measured using above-mentioned silicon hole test structure, specifically include following steps：
Step A01：First electric current is applied into module and the second electric current applies module and is connected with current source, by first voltage Test module and second voltage test module are connected with voltage tester instrument；
Here, in order to ensure each branch road has stable electric current, current source should use constant-current source；Due in the present invention Silicon hole resistance is smaller, and in order to realize accurate measurement, voltage tester instrument should use precision voltmeter.
Step A02：Using formula R=NU/2I-R'/2, the resistance of single silicon hole is calculated, wherein, N is that the first silicon leads to The quantity of hole array or the silicon hole in the second silicon hole array, I are the output current of current source, and U surveys for voltage tester instrument The voltage gone out, R' are the resistance of metal layer on back, and R is the resistance of single silicon hole.
Specifically, in the present embodiment, the silicon hole quantity N in silicon hole array is 3, then can apply mechanically formula R=3U/2I- R'/2, it is as described below using the principle of this formula：
Referring to Fig. 4, in the equivalent circuit schematic of the present embodiment, the resistance and contact electricity of any single silicon hole are defined Resistance sum is R, and the metallic resistance between two silicon hole arrays of silicon chip back side is R', and lead and test equipment impedance are r, are applied The total current added is I, and the voltage measured is U.Because the wire length of each silicon hole in silicon hole array is consistent, respectively The r of individual branch road is identical, and on the premise of overleaf metal thickness is sufficiently thick, the R' of each branch road is essentially identical, therefore, each branch road Electric current it is also identical, i.e. I1=I2=I3=I/3.It is well known that potentiometer may be generally viewed as, impedance is big without holding, and potentiometer branch road is basic There is no electric current process, the r of potentiometer branch road does not have partial pressure substantially, and therefore, the voltage U measured by potentiometer is essentially actual silicon Pressure drop on through hole, it includes two silicon hole resistance R and back metal resistance R'.Back metal resistance R' can pass through known gold Belong to resistivity of material and thickness to be calculated, or directly carry out metallic resistance measurement in silicon chip back side and obtain.Finally, Ke Yitong The resistance R that single silicon hole is calculated is crossed, calculation formula is R=3U/2I-R'/2.
Certainly, in other embodiments in the present invention, principle is same as above, and ignores lead and the test equipment impedance of each branch road R, measured voltage are two silicon holes of each branch road and the total voltage of metal layer on back, then i.e. using formula R= NU/2I-R'/2, the resistance calculations of single silicon hole are come out, for example when N is 4, then can apply mechanically formula R=4U/2I-R'/2 Deng.
It should be noted that during the measurement of the present invention, can be for each silicon hole of same silicon hole array The measurement of above-mentioned resistance is carried out, finally obtains average value, obtains more accurate silicon hole resistance value；Certainly, this just needs pin To the domain of same silicon hole array lithography layer, the domain of different test modules and lead lithography layer is designed, so as to will be same The resistance of each silicon hole in one silicon hole array is all measured.
Embodiment two
In the present embodiment, illustrated so that silicon hole array is quadrate array as an example, the silicon hole in the present embodiment Difference in test domain from the silicon hole test domain in embodiment one is that the geometry arrangement of silicon hole array is different, so as to So that the arrangement of test module and lead is also changed；Accordingly, the silicon hole test structure in the present embodiment and implementation The geometry arrangement that silicon hole test structure difference in example one lies also in silicon hole array is different, so that test module and drawing The arrangement of line is also accordingly changed；So in the present embodiment, the process prepared to silicon hole test structure and implementation Step in example one is identical, therefore, in the present embodiment, silicon hole test domain is described in further detail, to silicon hole Test structure and preparation method thereof is no longer repeated.
Referring to Fig. 6, the silicon hole test domain in the present embodiment includes：The domain of silicon hole lithography layer, and test The domain of module and lead lithography layer, the silicon hole that the superposition of the two domains can obtain in the present embodiment test domain.
The domain of silicon hole lithography layer, including the first silicon hole array pattern of mirror images and the second silicon lead to each other Hole array figure.In the present embodiment, the first silicon hole array pattern and the square array of the second silicon hole array pattern, with Exemplified by first silicon hole array pattern, the square arrangement of silicon hole V11, V12, V13 and V14, the present invention in, silicon hole it is straight Footpath can be 5-20um, can adjust the center of circle spacing between silicon hole according to different silicon hole sizes；In the present embodiment, A diameter of 5um of silicon hole, then the length of side of quadrate array can be 20um, be specially：V11 and V12, V13 and V14 X-axis Center of circle spacing on direction can be 20um, and the center of circle spacing in V1 and V2, V13 and V14 Y direction can be 0um；V11 It is 20um with the center of circle spacing of V13, V12 and V14 in the Y-axis direction, center of circle spacing in the X-axis direction is 0um.Due to Two silicon hole array patterns and the first silicon hole array pattern are in mutually mirror images, then the second silicon hole array pattern Geometry is arranged and the arrangement of silicon hole figure of the size in the first silicon hole array pattern is in specular, here to second Silicon hole array pattern repeats no more.
Meanwhile first silicon hole array pattern and the second silicon hole array pattern spacing it is bigger, the metal of silicon chip back side With regard to smaller, but due to the limitation of chip area, spacing between the two can not possibly be infinitely great for crosstalk, in the present embodiment, the The spacing of one silicon hole array pattern and the second silicon hole array pattern can be 50um, in figure between V13 and V15 away from From.
The domain of test module and lead lithography layer, including：Each other the first test module figure of mirror images and Some the first lead figures and some the second lead figures of second test module figure, each other mirror images；The One test module figure includes the first electric current and applies module figure and first voltage test module figure, the second test module figure Apply module figure and second voltage test module figure including the second electric current；
In the present embodiment, contact module figure is also included in the domain of test module and lead lithography layer, contacts module Silicon hole figure in figure and two silicon hole array patterns, which corresponds, to be set, and contacts center and these silicon of module figure The center of circle of via hole image is aligned one by one, and each module figure that contacts is used for a silicon hole figure and corresponding lead figure Shape connects.In the present invention, contact module figure should cover silicon hole figure, and the size of contact module figure then should be greater than The size of silicon hole figure, due to a diameter of 5um of silicon hole figure in the present embodiment, then contact the length of module figure and width can To be 6um.In the present invention, if contactless module figure, prepared silicon hole test structure still may be used in domain Contact module figure is set to be more beneficial for contact of the lead with silicon hole to be tested, in the present embodiment.
Each silicon hole figure V11, V12, V13 and V14 in first silicon hole array pattern, apply mould with the first electric current Block graphics is connected by the lead of the first lead figure, and any one in silicon hole figure V11, V12, V13 and V14 passes through First lead figure is connected with first voltage test module figure；
Each silicon hole figure V15, V16, V17 and V18 in second silicon hole array pattern, apply mould with the second electric current Block graphics is connected by the lead of the second lead figure, and any one in silicon hole figure V15, V16, V17 and V18 passes through Second lead figure is connected with second voltage test module figure.
Specifically, in the present embodiment, the number of the first lead figure is five, wherein, four leads are respectively by silicon hole Figure V11, V12, V13 and V14 and the first electric current apply module figure and are connected, and one bar of lead is by silicon hole figure V12 and the One voltage test module figure connects；The number of second lead figure is five, wherein, four leads are respectively by silicon hole Figure V15, V16, V17 and V18 and the second electric current apply module figure and are connected, and one bar of lead is by silicon hole figure V18 and the Two voltage test module figures connect.In the present embodiment, electric current applies module and is located on the center line of quadrate array.
Each bar lead all same in the present invention, in the present embodiment, the first lead figure and the second lead figure are Identical lead figure, it so may insure that the distance of test module figure to the silicon hole figure being attached thereto is identical, so as to Ensure that each bar lead has identical resistance, so as to evade the influence that lead resistance measures to silicon hole resistance.In the present invention, Lead and the design rule of test module need to be compatible with copper wiring technique, then lead graphic width should be less than 12um, test module Size should be less than 100um；In the present embodiment, the width of lead figure is 2um, and the length and width of test module figure are 80um.
It should be noted that the bar number of lead figure is connected by test module figure with silicon hole figure in the present invention Path determines, such as, in the present embodiment, using the first silicon hole array pattern and the first lead figure being attached thereto as Example, each own paths of silicon hole figure V11, V12, V13 and V14 are communicated to the first electric current and apply module figure, and silicon leads to Hole pattern V12 has a paths to first voltage test module figure, so adds up one and shares 5 paths, in the present embodiment In, then claim the first lead figure there are 5；Because the length of this 5 paths is identical and width is also identical, the first lead figure The length of shape is identical and width is also identical.Accordingly, the second silicon hole array pattern and the second lead figure being attached thereto With identical rule, and the width of the first lead figure and the second lead figure is identical and length is identical, repeats no more here.
Embodiment three
In the present embodiment, illustrated so that silicon hole array is the hexagonal array being centrosymmetric as an example, this implementation It is the geometry of silicon hole array in silicon hole test domain in example with the difference of the silicon hole test domain in embodiment one Arrangement is different, so that the arrangement of test module and lead is also changed；Accordingly, the silicon hole in the present embodiment is surveyed The geometry arrangement that silicon hole test structure difference in examination structure and embodiment one lies also in silicon hole array is different, so that The arrangement of test module and lead is also accordingly changed；So in the present embodiment, prepared by silicon hole test structure Process it is identical with the step in embodiment one, therefore, in the present embodiment, silicon hole test domain is made further specifically It is bright, silicon hole test structure and preparation method thereof is no longer repeated.
Referring to Fig. 7, the silicon hole test domain in the present embodiment includes：The domain of silicon hole lithography layer, and test The domain of module and lead lithography layer, the silicon hole that the superposition of the two domains can obtain in the present embodiment test domain.
The domain of silicon hole lithography layer, including the first silicon hole array pattern of mirror images and the second silicon lead to each other Hole array figure.In the present embodiment, the first silicon hole array pattern and the second silicon hole array pattern are hexagonal array and are Centrosymmetric image, by taking the first silicon hole array pattern as an example, silicon hole V21, V22, V23, V24, V25 and V26 are in center pair The hexagon arrangement of title, in of the invention, the diameter of silicon hole can be 5-20um, can be adjusted according to different silicon hole sizes Center of circle spacing between whole silicon hole；Because the second silicon hole array pattern and the first silicon hole array pattern are in mutually specular Figure, then the geometry arrangement of the second silicon hole array pattern and silicon hole figure of the size in the first silicon hole array pattern The arrangement of shape is in specular, and the second silicon hole array pattern is repeated no more here.
Meanwhile first silicon hole array pattern and the second silicon hole array pattern spacing it is bigger, the metal of silicon chip back side With regard to smaller, but due to the limitation of chip area, spacing between the two can not possibly be infinitely great for crosstalk, in the present embodiment, the The spacing of one silicon hole array pattern and the second silicon hole array pattern can be 50um, in figure between V26 and V211 Distance.
The domain of test module and lead lithography layer, including：Each other the first test module figure of mirror images and Some the first lead figures and some the second lead figures of second test module figure, each other mirror images；The One test module figure includes the first electric current and applies module figure and first voltage test module figure, the second test module figure Apply module figure and second voltage test module figure including the second electric current；
In the present embodiment, contact module figure is also included in the domain of test module and lead lithography layer, contacts module Silicon hole figure in figure and two silicon hole array patterns, which corresponds, to be set, and contacts center and these silicon of module figure The center of circle of via hole image is aligned one by one, and each module figure that contacts is used to connect in a silicon hole figure and corresponding lead Pick up and.In the present invention, contact module figure should cover silicon hole figure, and the size of contact module figure then should be greater than silicon and lead to The size of hole pattern, due to a diameter of 5um of silicon hole figure in the present embodiment, then contact the length of module figure and width can be equal For 6um.In the present invention, if contactless module figure, prepared silicon hole test structure still can be entered in domain Row is tested, and sets contact module figure to be more beneficial for contact of the lead with silicon hole in the present embodiment.
Each silicon hole figure V21, V22, V23, V24, V25 and V26 in first silicon hole array pattern, with the first electricity Stream applies module figure and is connected by the first lead figure, appointing in silicon hole figure V21, V22, V23, V24, V25 and V26 Meaning one is connected by the first lead figure with first voltage test module figure；
Each silicon hole figure V27, V28, V29, V210, V211 and V212 in second silicon hole array pattern, with Two electric currents apply module figure be connected by the second lead figure, silicon hole figure V27, V28, V29, V210, V211 and Any one in V212 is connected by the second lead figure with second voltage test module figure.
Specifically, in the present embodiment, the number of the first lead figure is 7, wherein, 6 leads are respectively by silicon hole figure Shape V21, V22, V23, V24, V25, V26 and the first electric current apply module figure and are connected, and a lead is by silicon hole figure V22 Connected with first voltage test module figure；The number of second lead figure is 7, wherein, 6 leads respectively lead to silicon Hole pattern V27, V28, V29, V210, V211 apply module figure with V212 and the second electric current and are connected, and a lead leads to silicon Hole pattern V28 connects with second voltage test module figure.In the present embodiment, electric current application module, which is located at, to be centrosymmetric On the center line of the hexagonal array of distribution.
Each bar lead all same in the present invention, in the present embodiment, the first lead figure and the second lead figure are Identical lead figure, it so may insure that the distance of test module figure to the silicon hole figure being attached thereto is identical, so as to Ensure that each bar lead has identical resistance, so as to evade the influence that lead resistance measures to silicon hole resistance.In the present invention, Lead and the design rule of test module need to be compatible with copper wiring technique, then lead graphic width is less than 12um, test module figure Shape size is less than 100um.
It should be noted that the bar number of lead figure is connected by test module figure with silicon hole figure in the present invention Path determines, such as, in the present embodiment, using the first silicon hole array pattern and the first lead figure being attached thereto as Example, each own paths of silicon hole figure V21, V22, V23, V24, V25 and V26 are communicated to the first electric current and apply module map Shape, and silicon hole figure V22 has a paths to first voltage test module figure, so adds up one and shares 7 paths, In the present embodiment of the present invention, then the first lead figure is claimed there are 7；Because the length of this 7 paths is identical and width is also identical, So the length of this 7 the first lead figures is identical and width is also identical.Accordingly, the second silicon hole array pattern and therewith The second connected lead figure also has identical rule, and the first lead figure and the second lead figure are identical, here no longer Repeat.
Example IV
In the present embodiment, illustrated so that silicon hole array is in isosceles trapezoid array arrangement as an example, in the present embodiment Difference in silicon hole test domain with the silicon hole test domain in embodiment one is the geometry arrangement of silicon hole array not Together, so that the arrangement of test module and lead is also changed；Accordingly, the silicon hole test structure in the present embodiment It is different that the geometry arrangement of silicon hole array is lain also in the silicon hole test structure difference in embodiment one, so that test mould The arrangement of block and lead is also accordingly changed；So in the present embodiment, the process prepared to silicon hole test structure It is identical with the step in embodiment one, therefore, in the present embodiment, silicon hole test domain is described in further detail, it is right Silicon hole test structure and preparation method thereof is no longer repeated.
Referring to Fig. 8, the silicon hole test domain in the present embodiment includes：The domain of silicon hole lithography layer, and test The domain of module and lead lithography layer, the silicon hole that the superposition of the two domains can obtain in the present embodiment test domain.
The domain of silicon hole lithography layer, including the first silicon hole array pattern of mirror images and the second silicon lead to each other Hole array figure.In the present embodiment, the first silicon hole array pattern and the second silicon hole array pattern are isosceles trapezoid, with first Exemplified by silicon hole array pattern, silicon hole V31, V32, V33, V34, V35, V36, V37 and V38 two-by-two be one group after be in isosceles Trapezoidal arrangement, in of the invention, the diameter of silicon hole can be 5-20um, can be led to according to different silicon hole sizes to adjust silicon Center of circle spacing between hole；Because the second silicon hole array pattern and the first silicon hole array pattern are in mutually mirror images, Geometry arrangement and silicon hole figure of the size in the first silicon hole array pattern of so the second silicon hole array pattern Arrangement is in specular, and the second silicon hole array pattern is repeated no more here.
Meanwhile first silicon hole array pattern and the second silicon hole array pattern spacing it is bigger, the metal of silicon chip back side With regard to smaller, but due to the limitation of chip area, spacing between the two can not possibly be infinitely great for crosstalk, in the present embodiment, the The spacing of one silicon hole array pattern and the second silicon hole array pattern can be 50um, in figure between V35 and V311 Distance.
The domain of test module and lead lithography layer, including：Each other the first test module figure of mirror images and The the first lead figure and the second lead figure of second test module figure, each other mirror images；First test module figure Shape, which includes the first electric current application module figure and first voltage test module figure, the second test module figure, includes the second electric current Apply module figure and second voltage test module figure；
In the present embodiment, contact module figure is also included in the domain of test module and lead lithography layer, contacts module Silicon hole figure in figure and two silicon hole array patterns, which corresponds, to be set, and contacts center and these silicon of module figure The center of circle of via hole image is aligned one by one, and each module figure that contacts is used to connect in a silicon hole figure and corresponding lead Pick up and.In the present invention, contact module figure should cover silicon hole figure, and the size of contact module figure then should be greater than silicon and lead to The size of hole pattern, due to a diameter of 5um of silicon hole figure in the present embodiment, then contact the length of module figure and width can be equal For 6um.In the present invention, if contactless module figure, prepared silicon hole test structure still can be entered in domain Row is tested, and sets contact module figure to be more beneficial for contact of the lead with silicon hole in the present embodiment.
Each silicon hole figure V31, V32, V33, V34, V35, V36, V37 in first silicon hole array pattern and V38, with the first electric current apply module figure be connected by the lead of the first lead figure, silicon hole figure V31, V32, V33, Any one in V34, V35, V36, V37 and V38 passes through the lead and first voltage test module of the first lead figure Figure is connected；
Each silicon hole figure V39, V310, V311, V312, V313, V314 in second silicon hole array pattern, V315 and V316, apply module figure with the second electric current and be connected by the lead of the second lead figure, silicon hole figure V39, In V310, V311, V312, V313, V314, V315 and V316 any one by a lead of the second lead figure with Second voltage test module figure is connected.
Specifically, in the present embodiment, the number of the first lead figure is 9, wherein, 8 leads are respectively by silicon hole figure Shape V31, V32, V33, V34, V35, V36, V37, V38 and the first electric current apply module figure and are connected, and a lead leads to silicon Hole pattern V34 connects with first voltage test module figure；It is corresponding with the first lead figure, the number of the second lead figure Mesh is 9, wherein, 8 leads are respectively by silicon hole figure V39, V310, V311, V312, V313, V314, V315 and V316 Apply module figure with the second electric current to be connected, a lead connects silicon hole figure V316 and second voltage test module figure Pick up and.In the present embodiment, electric current applies module and is located on the center line of isosceles trapezoid array.
Each bar lead figure all same in the present invention, in the present embodiment, the first lead figure and the second lead figure It is identical lead figure, so may insure that the distance of test module figure to the silicon hole figure being attached thereto is identical, So that it is guaranteed that each bar lead has identical resistance, so as to evade the influence that lead resistance measures to silicon hole resistance.This hair In bright, the design rule of lead and test module need to be compatible with copper wiring technique, then lead graphic width is less than 12um, tests mould Block graphics size is less than 100um.
It should be noted that the bar number of lead figure is connected by test module figure with silicon hole figure in the present invention Path determines, such as, in the present embodiment, using the first silicon hole array pattern and the first lead figure being attached thereto as Example, each own paths of 8 silicon hole figures are communicated to the first electric current and apply module figure, and silicon hole figure V34 has one Paths so add up one and share 9 paths, in the present embodiment of the present invention, then to first voltage test module figure The number of first lead figure is referred to as 9；Because the length of this 9 paths is identical and width is also identical, this 9 first The length of lead figure is identical and width is also identical.Accordingly, the second silicon hole array pattern and the second lead being attached thereto Figure also has identical rule, and the first lead figure and the second lead figure are identical, repeat no more here.
In summary, silicon hole of the invention test domain, silicon hole test structure, the preparation side of silicon hole test structure The method for measurement of method and silicon hole resistance, the mentality of designing shunted using the equiarm of analog circuit, utilizes equal length and width Each silicon hole in silicon hole array is applied module with electric current and is connected by the lead of degree, recycles identical lead to lead to silicon Any one silicon hole in hole array is connected with voltage test module, it is ensured that the resistance of each silicon hole branch road is identical； The the first silicon hole array and the second silicon hole array of specular arrangement each other are designed in front side of silicon wafer, is sunk in silicon chip back side Product layer of metal layer, the measurement of resistance can be carried out so as to which only voltage need to be applied in front side of silicon wafer, has effectively evaded lead electricity Resistance, improves the resistance accuracy in measurement of silicon hole, and application and exploitation for the silicon hole in later stage provide favourable data and supported.
Although the present invention is disclosed as above with preferred embodiment, the right embodiment illustrated only for the purposes of explanation and , the present invention is not limited to, if those skilled in the art can make without departing from the spirit and scope of the present invention Dry change and retouching, the protection domain that the present invention is advocated should be to be defined described in claims.

Claims (9)

1. a kind of silicon hole tests domain, it is characterised in that by domain and test module and the lead photoetching of silicon hole lithography layer The domain of layer is superimposed to be formed, wherein,
The domain of the silicon hole lithography layer is including the first silicon hole array pattern of mirror images and the second silicon lead to each other Hole array figure；
The domain of the test module and lead lithography layer includes：First test module figure of mirror images and each other Some the first lead figures and some the second lead figures of two test module figures, each other mirror images；It is described First test module figure includes the first electric current and applies module figure and first voltage test module figure, the second test mould Block graphics includes the second electric current and applies module figure and second voltage test module figure；Wherein,
Each silicon hole figure in the first silicon hole array pattern applies module figure with first electric current and passes through institute State the first lead figure to be connected, any one silicon hole figure in the first silicon hole array pattern and the described first electricity Pressure test module figure is connected by the first lead figure；
Each silicon hole figure in the second silicon hole array pattern applies module figure with second electric current and passes through institute State the second lead figure to be connected, any one silicon hole figure in the second silicon hole array pattern and the described second electricity Pressure test module figure is connected by the second lead figure；
The first lead figure is identical with the second lead figure；Wherein, the silicon obtained using silicon hole test domain is led to In the test structure of hole, the resistance of single silicon hole is R=NU/2I-R'/2, wherein, N is that the first silicon hole array or the second silicon lead to The quantity of silicon hole in hole array, the electric currents of I first apply the output current for the current source that module is applied, and U is first voltage The voltage that the voltage tester instrument of test module is measured, R' are the resistance of metal layer on back, and R is the resistance of single silicon hole.
2. silicon hole according to claim 1 tests domain, it is characterised in that the silicon hole test domain also includes connecing Touch block graphics, the contact module figure corresponds with the silicon hole figure to be set, in the contact module figure The heart is aligned one by one with the center of circle of the silicon hole figure, and each contact module figure is used for a silicon hole figure It is connected with the corresponding lead figure.
3. silicon hole according to claim 2 tests domain, it is characterised in that the contact module figure is arranged at described In the layout patterns of test module and lead lithography layer.
4. silicon hole according to claim 1 tests domain, it is characterised in that the described first or second silicon hole array of figure Shape be Triangular array figure, quadrate array figure, rhombus array pattern, fan-shaped array pattern, be centrosymmetric six Side shape array pattern or the array pattern arranged in isosceles trapezoid.
5. a kind of silicon hole beta version figure using described in claim 1 into silicon hole test structure, it is characterised in that bag Include：
Have mutually in the first silicon hole array and the second silicon hole array of specular in front side of silicon wafer；
There is layer of metal layer in silicon chip back side, for the first silicon hole array to be neutralized in the second silicon hole array Silicon hole be connected with low resistance；
Also have in front side of silicon wafer mutually in the first test module and the second test module of specular, if mutually in specular The dry lead of bar first and some second leads；First test module includes the first electric current and applies module and first voltage survey Die trial block, second test module include the second electric current and apply module and second voltage test module；Wherein,
Each silicon hole in the first silicon hole array applies module with first electric current and passes through the first lead phase Connect, any one silicon hole in the first silicon hole array is drawn with the first voltage test module by described first Line is connected；
Each silicon hole in the second silicon hole array applies module with second electric current and passes through the second lead phase Connect, any one silicon hole in the second silicon hole array is drawn with the second voltage test module by described second Line is connected；
Some first leads are identical with some second leads；Wherein, single silicon leads in silicon hole test structure The resistance in hole is R=NU/2I-R'/2, wherein, N is the first silicon hole array or the number of the silicon hole in the second silicon hole array Amount, I are applied the output current for the current source that module applies by the first electric current, and U is the voltage tester of first voltage test module The voltage that instrument is measured, R' are the resistance of metal layer on back, and R is the resistance of single silicon hole.
6. silicon hole test structure according to claim 5, it is characterised in that the silicon hole test structure also includes connecing Touch block, the contact module corresponds with the silicon hole to be set, the center of the contact module and the silicon hole The center of circle is aligned one by one, and each contact module is used for a silicon hole, and corresponding first lead or institute The second lead is stated to be attached.
7. silicon hole test structure according to claim 5, it is characterised in that the described first or second silicon hole array is Triangular array, quadrate array, rhombus array, fan-shaped array, the hexagonal array being centrosymmetric, arrange in isosceles trapezoid The array of cloth.
8. a kind of silicon hole using described in claim 1 is tested domain and tested to prepare silicon hole described in the claims 5 The method of structure, it is characterised in that including sequentially forming silicon hole lithography layer, test module and lead lithography layer and silicon chip Three processes of metal layer on back, wherein,
Forming the process of the silicon hole lithography layer includes：
Step S01：Layer of metal diffusion impervious layer is deposited in the front side of silicon wafer；
Step S02：Under the protection on the barrier layer, the domain using the silicon hole lithography layer passes through photoetching and etching technics Mutually the first silicon hole array in specular and the second silicon hole array are formed in front side of silicon wafer；
Step S03：Barrier layer and filling gold are sequentially depositing into the first silicon hole array and the second silicon hole array Category；
Step S04：Planarization process is carried out to the top surface of the metal of the filling, until the front side of silicon wafer surface is without institute State the residual of metal；
Forming the process of the test module and lead lithography layer includes：
Step S05：One layer of dielectric layer is deposited in the front side of silicon wafer；
Step S06：The domain of the test module and lead lithography layer is aligned with the domain of the silicon hole lithography layer, in institute State front side of silicon wafer and form mutually being surveyed in first test module and described second of specular in the through hole test structure Die trial block, and mutually some first leads in specular and some second leads；
Step S07：First test module, second test module, first lead and second lead are entered Row metal interconnection process；
Forming the process of the silicon chip back side metal level includes：
Step S08：Reduction process is carried out to the silicon chip back side, until the metal of each silicon hole bottom is exposed Come；
Step S09：Layer of metal layer is deposited in the silicon chip back side, in the metal level and the first silicon hole array and institute The each silicon hole stated in the second silicon array is in contact, so as to form the silicon hole test structure；Wherein, silicon hole test knot The resistance of single silicon hole is R=NU/2I-R'/2 in structure, wherein, N is in the first silicon hole array or the second silicon hole array Silicon hole quantity, I applies the output current of current source that module applies by the first electric current, and U is that first voltage tests mould The voltage that the voltage tester instrument of block is measured, R' are the resistance of metal layer on back, and R is the resistance of single silicon hole；Wherein, by institute The first electric current stated applies module and the second described electric current applies module and is connected with current source, and described first voltage is surveyed Die trial block and described second voltage test module are connected with voltage tester instrument.
9. the preparation method of silicon hole test structure according to claim 8, it is characterised in that the step S06, bag Include：Using the test module and the domain of lead lithography layer, it is aligned with the domain of the silicon hole lithography layer, through photoetching and quarter Etching technique, contact module is formed on the front side of silicon wafer, and in the top surface of the silicon hole, it is described to contact in module The center of circle of the heart and the top surface of the silicon hole is aligned, and first test module and described is formed in the front side of silicon wafer Second test module, and contact some first leads that module is connected and described some second are drawn with described Line；Then, described metal interconnection process is carried out.
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