CN103782582B - There is the imageing sensor of mixed type heterojunction structure - Google Patents

There is the imageing sensor of mixed type heterojunction structure Download PDF

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CN103782582B
CN103782582B CN201280030139.XA CN201280030139A CN103782582B CN 103782582 B CN103782582 B CN 103782582B CN 201280030139 A CN201280030139 A CN 201280030139A CN 103782582 B CN103782582 B CN 103782582B
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layer
circuit
cmos
pmos
pixel
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CN103782582A (en
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L.科斯洛夫斯基
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Samsung Electronics Co Ltd
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Altasens Inc
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Priority to CN201610809067.9A priority Critical patent/CN106449678B/en
Priority to CN201610809068.3A priority patent/CN106449679B/en
Priority to CN201610809069.8A priority patent/CN106454157B/en
Priority to CN201610808925.8A priority patent/CN106449677B/en
Priority to CN201610809123.9A priority patent/CN106454163B/en
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    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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Abstract

A kind of image sensor architecture provides the SNR more than 100dB, without using mechanical shutter.Circuit block for active pixel sensor array is separated and is vertically disposed at least two different layers in hybrid chip structure.Top layer is preferably used low noise PMOS manufacturing process manufacture, and includes the photodiode for each pixel and amplifier circuit.Bottom is preferably used standard CMOS process and manufactures, and includes any digital circuit needed for NMOS image element circuit parts and signal processing.Compared with using CMOS, by forming top layer in the PMOS technique that low-noise pixel optimizes for being formed, pixel performance can be greatly improved.

Description

There is the imageing sensor of mixed type heterojunction structure
Technical field
Present invention relates in general to solid state image sensor, and relate more specifically to the 3-dimensional image sensor structure of novelty.
Background technology
The visual imaging system with cmos image sensor produced significantly reduces photographing unit cost and power, improves image resolution ratio simultaneously and decreases noise.Cmos image sensor is typically imaging system on sheet (iSoC) product, image detection and signal processing are combined by it with a large amount of supportive intellectual property (IP) blocks, described supportive intellectual property block includes timing controller, clock driver, reference voltage, A/D changes, image procossing level, and other auxiliary circuit.Therefore, the video camera obtained can use and only be assembled by camera lens, shutter and battery backed single CMOS integrated circuit.Result is that the least photographing unit has increasingly longer battery life with the lowest cost.
The improvement provided by CMOS iSoC sensor, especially includes the operating flexibility that the iSoC function embedded by it is capable of, also has been converted into the appearance of double-purpose camera, and it produces the static image of high-resolution and high definition video.This concentration of static capture and video acquisition has been abolished special stillcamera and has utilized previous sensor technology, traditional both Video Cameras that such as CCD produces.The needs to the most dual-purpose imageing sensor the most it are exposed through most preferably to perform two kinds of imaging.
Although CMOS iSoC synthesis sensor is many application produces picture (still) and the video showing acceptable quality, their picture quality is far below the restriction arranged by device physics.Additionally, capture quality the most a little reduces under various lighting condition and is under extreme conditions severely impaired.
One example of challenge situation is to directly being taken a picture as the tree of backlight by the sun；Shade, the many DE Specular Lightings on exposure leaf, and the combination of direct sunlight almost always result in suboptimum picture quality.The Video Capture of backlight tree the most more challenge, if especially wind is combined with the cloud amount of change；Shade, this specific admixture of semi-tone and DE Specular Lighting is especially difficult to capture with optimal fidelity.Joining challenge further, this situation occurs in several seconds of relatively uniform and optimum lighting condition continually and dynamically.The challenge of capture " perfect " image is photographed the fact that the most challenging lighting condition of Shi Chaoxiang tilts so that photo aesthetic feeling to maximize (by utilizing in sunrise and acronical so-called " magic moment ") and complicates further.
Due to the fact that many elements are light activated by direct or non-immediate mode of imageing sensor, change and unstable scene dynamics is not only during time of exposure, and affects final image quality At All Other Times all.The capture of this parasitic signal generates the imaging artifacts reducing picture quality.The sensor with internal electron shutter can not prevent a large amount of parasitic signal to be stained image capturing.Typically facilitate the comprising of mechanical shutter and prevent major part parasitic signal and generate.But, add cost, complexity including mechanical shutter, and reduce photographing unit reliability；Therefore exist in the urgent need to eliminating comprising of it.
But, the best mode for real stop light developed so far is mechanical shutter；Obtained shutter rejection ratio (SRR) can be with approach infinity, i.e. when shutter is closed, and the light being not detected by Anywhere irradiating on cameras in the sensor.Detection needs not to be on actual light detector, but can substitute for other in different circuit local picked to affect performance.The shutter rejection ratio of sensor is also frequently referred to as (when mechanical shutter will be placed on before sensor so that period when collecting zero garbage signal) period in cycle when light capture is invalid and describes the extinction coefficient of the ability that its resistance is in the light.
The monolithic sensor with electronic shutter is invisible to ambient light unlike when a mechanical shutter is used.But, in order to reduce cost further, camera manufactures wishes to eliminate the mechanical shutter mechanism for stillcamera by having the sensor manufacturer feeding mechanism providing high SRR.Therefore, CMOS iSoC needs have the SRR exceeding well over 100dB, and it is outside the delustring limit of modern CMOS and ccd image sensor.
It is the imageing sensor producing and there is electronics Rolling shutter for eliminating a method of mechanical switch.Image be formed in these sensors based on line by line make from the beginning of the exposure of the first row/terminate to start/terminate to be constantly present the delay of a frame time to the exposure of last column.Result is often to go effectively to capture different periods.No matter for static capture or video, for the capture rate of below about 60Hz, making us stinking illusion may be following, and this depends on the speed moved in the scene.On the other hand, the overall performance of Rolling shutter sensor typically superior to has the sensor of global shutter ability, the exposure period that the capture of the most whole sensor is identical, because pixel is easier to design and sets up；The signal to noise ratio of Rolling shutter sensor is greatly better than having those of global shutter.
Mechanical shutter additionally can be replaced by integrated electronic global shutter in the image sensor.In such sensor, each pixel is the signal of its capture integrated during single, identical exposure cycle.Although having more complicated pixel design much, sensor must perform in the case of not infringement so that the performance of measurement is the highest and is not designed by device or Technology limits.Up to now, CMOS global shutter sensor has represented the duty factor lower than the CMOS Rolling shutter sensor of competition and higher noise level.Use system on chip to produce these " snapshot (snapshot) " sensors and the most do not narrow the gap (close the gap).
For the advantage provided by system on chip that manifests in the visual imager of the CMOS of camera product thus excited sizable effort to improve valid pixel sensor (APS) device further by exploitation high-performance global shutter function.Unfortunately, except higher noise, outside the duty factor of difference, and the vulnerability to parasitic signal pickup, the iSoC of cumulative complexity is the most fragile to noise pickup.Undesirable pickup is possible especially in the most desired sensor: static and Video Capture the pattern of high-quality can change sensor.The noise that one unpleasant result is to increase, i.e. relevant clock feedthrough and fixed pattern noise, because double mode use has dynamically changed sensor self EMI and clock feedthrough, thus alternatively affect picture quality.
Having a present image sensor design of snapshot image capture ability thus remain a need for mechanical shutter to perform the dual sampling (CDS) being correlated with most effectively, wherein the frame from the second exposure deducts the first spacer so that reset (or kTC) noise eliminating sensor also reduces fixed pattern noise simultaneously.In the case of not having mechanical shutter, rear CDS noise is increased to far above the basic restriction generally arranged by the time interval between frame subtraction by various parasitic signals.
In the case of there is no mechanical shutter, the modern image sensor design with Rolling shutter image capture capabilities more efficiently works, because Rolling shutter electronic circuit can be used to dead time minimisation, during it some in circuit of sensor by direct or non-immediate in the way of be fragile to light pollution.Therefore throughout sensor, it is included in other optical position sensitive of the many outside the photodetector of each pixel, limits the integrated of undesired signal by the dead time minimisation of careful Rolling shutter timing.
Being to use CMOS technology to produce these devices unchangeably for producing the last major defect of the embedded on-chip CMOS circuit complexity of high-performance image sensors, this CMOS technology is by be modified to add subsequently what imaging aspect " standard " CMOS technology started to be developed.These amendments afterwards have redesigned the CMOS technology for imaging, even if originally Floor layer Technology is optimized produces digital display circuit on sheet for a large amount of.
First result is that these CMOS " imageing sensor " (CIS) technique has many mask layers, thus adds and manufacture relevant cost.
Second result is that the cmos imaging process obtained provides Digital Logic that the benefit of Moore's Law in cmos image sensors is not fully utilized at the technology node far lagging behind prior art.
The final result that empirical results within the past ten years indisputably demonstrates is that correctly to optimize photodiode quality in these monolithics CIS technique be impossible；Although average dark current is substantially comparable to produce, with the CCD of business, the dark current that routine obtains, but when compared with scientific CCDS, this dark current is higher, and most makes people insufferable, and the number of defect pixel wants big several orders of magnitude.Therefore, integrated process integration is still more suitable for Digital Logic rather than more accurate photodetector.This shortcoming is not surprising, because having the enough production requirements to high-quality sensor the most recently to prove to be developed particularly the CIS technique of optimization at world's Semiconductor foundries.
But the much more expensive semiconductor process development that the cmos image sensor technique of exploitation optimization will need special image taking sensor to be target, described imageing sensor has widely different requirement for the mainstream consumer's actuation techniques still driving much bigger yield, the invention provides more tractable solution.
Summary of the invention
The present invention is mixed type imaging sensor, and it is most preferably configured to optimize pixel performance, and including photodiode quality, and iSoC is integrated.Imaging SoC can use zero picture element flaw cost-effectively to manufacture with extremely low dark current, also uses up-to-date available technology node integrated in order to perform SoC simultaneously.
The technology for Vertical collection that the imageing sensor of the present invention is occurred by use is constructed, and as by United States Patent (USP) No.6,504,141 and 6,476,375 illustrations, wherein light detecting layer separates with following signal processor layer.Can use the alternate manner for vertically combining three dimensional integrated circuits (3D-IC), such as United States Patent (USP) No.6,902,987 directly in conjunction with interconnection technique.
By the present invention in that prior art is improved to provide from photodiode and the most damaged pixel performance of first order amplifier by the light detecting layer with PMOS technology constitution optimization respectively.The PMOS transistor made in light detecting layer has the excellent performance much of the elaborate PMOS device than in deep-submicron CMOS process, thus improves performance and potentially eliminate flicker noise.Performance is improved relative to other circuit block in signal to noise ratio and the excellent PMOS transistor of supply to 3D-IC.
Fig. 7 and 8 compares with the PMOS technology optimized obtainable reading noise vs with standard CMOS technologies obtainable reading noise, during wherein source follower is formed at NMOS, this NMOS has the flicker noise lower than the flicker noise being readily available in usual casting technique, i.e. the best compared with being readily available.Even if so, PMOS global shutter may produce 1e-(or hole under the sense capacitance of 5fF) reading noise.There is under 5.5fF the reading noise of 3.5e-NMOS global shutter circuitry instead.The more important thing is long-run development, PMOS solution tends to far below 1e-along with sense capacitance reduces, and NMOS solution reaches stable far above 2e-.(full well is held according to required maximum trap Capacity), the present invention is therefore, it is possible to improve over 15dB by global shutter SNR from the minima of 10dB.Assuming that NMOS flicker noise is represented by many CIS techniques routinely, this advantage increases at least another 6dB.
The present invention dramatically improves the shutter rejection ratio of obtained global shutter sensor by realizing photoresist layer under photosensitive layer and on following signal accumulation layer.In following cmos layer, signal storage is completely isolated.
The present invention also significantly improves the ability for embedding other function in 3D-IC iSOC.Signal processing layer is formed on below photosensitive layer and light blocking interconnection layer.Signal processing layer can at the most up-to-date technology node with substantially any can CMOS technology design.
On the other hand, alternately using extremely ripe technology node, signal processing layer produces with most cost effective CMOS technology with can substitute for, and this technology node instead decreases development cost and production cost.
In either case, multiple digital CMOS technology also is able to the high level capacitor realizing comprising the signal storage efficiency providing high, such as trench capacitor, uses high power capacity dielectric replacement capacitor etc..Therefore, the sampling capacitor of snapshot pixel can utilize the biggest electric capacity manufacture to suppress its kTC noise.
Therefore, the present invention is global shutter 3D-IC iSOC, and it provides currently from by the main stream of CMOS being currently available that fabrication techniques The lower Column Properties that iSOC is unavailable:
Little or zero picture element flaw
There is the global shutter pixel of ultra-low noise and 100% fill factor, curve factor
160dB or higher high shutter rejection ratio
By the high quality P MOS transistor utilizing the perpendicular interconnection technology used throughout mixed type sensor (3DIC) to come in pixel and use throughout iSOC potentially.
Accompanying drawing explanation
By detailed description below in conjunction with the accompanying drawings, the present invention will be easily understood by the following description, the structural detail that the most similar reference number instruction is similar, and wherein:
Fig. 1 illustrates the layer of hybrid architecture according to an embodiment of the invention；
Fig. 2 illustrates the layout of the main circuit component of hybrid architecture according to an embodiment of the invention；
Fig. 3 is the schematic diagram of the example how the valid pixel circuit illustrating and having sampling and holding can be divided between PMOS and cmos layer；
Fig. 4 is the schematic diagram of the example how the valid pixel circuit illustrating and having relevant dual sampling can be divided between PMOS and cmos layer；
Fig. 5 is the schematic diagram of the example illustrating how capacitive character trsanscondutance amplifier (CTIA) has global shutter and sampling and holding；
Fig. 6 is to illustrate to have global shutter, sample and keep and the schematic diagram of example that how the capacitive character trsanscondutance amplifier (CTIA) of relevant dual sampling is divided between PMOS and cmos layer, and wherein capacitor is formed in the intermediate layer；
Fig. 7 assumes that the Mathcad curve of the reading Noise Estimation of the global shutter image element circuit with pmos source follower, and it shows " optimization " PMOS flicker noise behavior；With
Fig. 8 assumes that the Mathcad curve of the reading Noise Estimation of the global shutter image element circuit with nmos source follower, and it shows the behavior of " well " NMOS flicker noise.
Detailed description of the invention
There is provided explained below so that any those skilled in the art can make and use the present invention and proposition illustrate by inventor expect for the best mode embodiment of the present invention.But, various amendments will be apparent to those skilled in the art remaining.Any and all such amendments, equivalent and replacement are intended to fall under in the spirit and scope of the present invention.
Present invention is novel in that image sensor architecture, which overcome the restriction of prior art cmos image sensor, provide more than 100dB and the SRR of even more than 160dB in the case of need not use mechanical shutter simultaneously.More specifically, according to the present invention, the circuit block for active pixel sensor array is separated and is vertically disposed in the layer that at least two in mixed type chip structure is different.Top layer is preferably used low noise PMOS manufacturing process and manufactures, and includes the photodiode for each pixel and amplifier circuit.Bottom is preferably used standard CMOS process and manufactures, and includes any digital circuit needed for NMOS image element circuit parts and signal processing.
By forming top layer in the PMOS technique for the ultra-low noise component optimization needed for formation imaging pixel of future generation, compared with the single chip CMOS technique that use is imaging sensor and/or digital integrated electronic circuit composition, pixel performance is greatly improved.Additionally, because digital circuit separate with imaging circuit with (philosophically) in philosophy physically now, its can use substantially any standard CMOS technology and possibly with recently can technology node manufactured.From many single business Semiconductor foundries can this standard CMOS process be optimized for circuit speed and manufacturing cost rather than for producing imageing sensor.
By contrast, single chip CMOS image sensor (CIS) technique of today generally supports to use the Digital Logic of the technology node of backward prior art at least several generations.Such as, several CIS technique supports have the Digital Logic of 90nm technology and 45nm digital technology is in manufacturing widely.
And form sharp contrast, from a limited number of Semiconductor foundries can cmos image sensor (CIS) technique with following integrated circuit processing technique, photodetector is integrated, its be generally of to numeral IC produce succession；This compromise being capable of supporting for the storehouse of IP widely of digital circuit is relative to compromising the most available photodiode quality.Although being acceptable market by lower quality image product wherein, such as on cellular phone market centralized production, or by adding important image procossing in supportive electronic equipment, such composition is already endowed with business practice, but the photodetector quality the most damaged CIS reprography provided by the most expensive charge coupled device (CCD) manufacturer.
Current CIS technique about 40 to 50 masks of needs manufacture has color filter, the color imaging sensor that the metal level of lenticule and up to level Four is supported.The digital CMOS process technology of standard needs mask layer few as 30.Can utilize and be completed integrated with PMOS transistor and minimum two levels of metal for pinned photodiode by mask layer few as 8 to 14.Unlike the photodetector in CMOS device, it is affected by the many processing steps outside those steps needed for building photodetector, and the photodetector in PMOS device is fully optimized and is provided in original state.
Therefore, by two layers are combined into stacked structure, the top layer (with any intermediate layer) of simplification works to be capable of the production of the photodetector quality of similar CCD, is capable of the complete optics shielding of lower level simultaneously.In the case of need not mechanical shutter, obtained shielding hence allows to the electric charge of required photogenerated and is stored and by photoelectric protection.
Double-layer structure is effectively formed three layers of heterojunction structure, it is preferable to being vertically integrated global shutter pixel, it not only provides low photodiode noise and dark current, and the low noise amplification with extremely low flicker noise is provided, there is the photoresist layer below the highest opacity, and the sampling needed for arranging global shutter operation and the preferable place of holding capacitor device in following cmos layer.Because capacitor is formed in standard digital Technology, the high capacitance technical module of replacement is available, including trench capacitor and the high dielectric constant dielectric of replacement.
Therefore, by two semiconductor layers are combined into stacked structure, it is possible to realize the complete optics shielding of lower level, seamless integration ultra-low noise circuit and photodiode layer, and also be able to realize up to doubling the real estate (real for image element circuit Estate), the present invention is in the case of minimum performance is damaged, it is simple to the pixel operation of global shutter pattern.When operation, the first storage position in the upper layer stores the dynamic scene content limited by electronic shutter.The the second storage position being positioned in lower level processes driven state memory node and is transferred to " snapshot " data of protected node, and this protected node the most optically but also is electrically being isolated with photodetector by new framework.
It is also referred to as global shutter pixel for identical snapshot to be captured in whole sensor the specific device of the snapshot image at each pixel period simultaneously.Global shutter pixel integrated in monolithic CIS Technology lives through many noises, cause the SNR reduced, the SRR of relative mistake, because otherwise it is hardly possible the most optically but also be electrically isolating snapshot memory node, and the biggest pel spacing owing to the many components in Free Region.
Figure 1 illustrates the specific embodiment of this design.In this drawing, using low noise PMOS technique to manufacture top wafer 1, to form high-quality light electric diode, it has the picture element flaw that the picture element flaw more possible than in standard CMOS is less generally.This wafer 1 is also required to less mask, and therefore has relatively low cost.
From its back side illuminaton upper strata in FIG, PMOS layer, because it has been reversed directly PMOS circuit and photodiode layer to be connected to the second cmos layer.Before interconnection or after interconnection, top layer is thinned between 50 and 5 microns and is passivated subsequently, throughout visible spectrum, photocarrier is absorbed maximization aborning.This thinning manufacture PMOS layer on such as SOI or SIMOX wafer at present by sacrificial substrate, or by by CMP(chemical-mechanical planarization) or grinding back surface mechanically remove whole sensor substrate and perform.
Can use the CMOS process of standard to form one or more lower level 2, its have with than current cmos image sensor (CIS) technology lower cost to the advantage supporting low-power digital circuit.Additionally, because the CMOS wafer of standard will include multiple metal level, in the case of need not mechanical shutter, the optics shielding of the reinforcement of this offer charge storage cell.Another benefit is in the case of sensor designer can be used by other real estate now, and much higher value capacitor can be formed in cmos layer 2, further improves integral sensors performance.
Wafer on WoW(wafer can be used) wafer combines by encapsulation technology, and produce stacking or three-dimensional hybrid type imageing sensor, wherein top PMOS wafer 1 is attached to relatively low CMOS wafer 2 by WoW interconnection layer 3.And, because image sensor circuit is divided at least two layer now, the whole surface area of chip can be reduced, and causes the less die-size for each layer.
Figure 2 illustrates more detailed preferred embodiment.This illustrates cross section Figure 10 of embodiments of the invention in the introduction and illustrates various feature or sensor is the top view Figure 20 how being mapped to embodiment.As shown, in the center 122 at the top of top layer 12, form pel array and the pmos source follower amplifier of pinned photodiode.In PMOS, manufacture photodiode and amplifier circuit causes the background noise (noise floor) (1e-contrast 3e-) lower than traditional cmos sensor, and lower dark current.Cover pel array 122 is lenticule and the matrix of color filter 121.The most optional " black " pixel can be formed along the edge of pel array.
The periphery of ring pixel array 122, can form post buffer 123,124 and the PMOS part of analog-digital converter (ADC).There is the big feature performance benefit obtained by dividing ADC between PMOS and cmos layer.In the cmos imager of standard, ADC is normally limited to 10 bit resolutions.The fact that this is due to NMOS restriction 1/f noise and threshold voltage mates, it causes higher flicker noise and relatively low resolution.But, in the pmos case, there is much lower 1/f noise it is thus desirable to less error correcting, cause the resolution of up to 16 bits.There is also more much better threshold voltage to mate to be capable of higher base resolution (base resolution).
Form post buffer in PMOS layer also reduces the reading noise being associated at least partially.In the case of relatively low reading noise, black clamper (black Clamp) function is more efficient.Being additionally, since the noise level of reduction, circuit designers can select to increase gain and frame rate.Utilizing this high quality P-FET, simple changer can provide 100 or more gain, and utilizes cascode amplifier to configure, and gain can be 10000 or more.P-FET available in the deep sub-micron technique of standard produces changer amperage, and its open-loop gain is at most in the rank of units.
Along with the improvement of the ADC performance produced by relatively low noise PMOS layer, ADC power can be reduced up to 9/10, and still generates 12-14 bit resolution.
In the cmos layer 18 of standard, trench capacitor and NMOS FET are formed in pixel array portion 122 area below 181 of top layer 12.Trench capacitor can have relatively large size, and because they are covered, typically with metal layers shielding, the light impact that the electric charge of storage is not irradiated onto on the pixel element in top layer 12.In the cmos image sensor design that many is previous, the capacitor of use is actually formed P/N knot, and is not " really " capacitor.This framework provides simple scheme to build true capacitor, and it can improve sensor performance further.This allows to manufacture has big SRR(> 160dB) imageing sensor, without the need for outside mechanical shutter.
The NMOS of post buffer and ADC is partially disposed within PMOS ADC and the periphery 183 of post buffer district 123,124 cmos layer 18 below of top layer 12, on 184.Wafer (WoW) combined process on wafer is used top layer 12 and cmos layer 18 to be combined.By main array portion 122,181 and periphery 123,124,183,184 being connected through the through hole of WoW binder course 14.
Barrier layer 16 is preferably provided between top layer and bottom to shield NMOS parts and affecting from light.This layer can be physically separated layer, or can be formed the part of each layer.And, capacitor can be formed in barrier layer self, it is provided that layout and performance motility.
It addition, imageing sensor includes digital circuit ring 182,185(i.e. numeral " Nuburgring (Nurburgring) " or the runway ellipse around pel array).As seen in top view Figure 20, digital circuit ring can extend around the whole peripheral of sensor chip, and it includes that digital signal processing circuit is to process the output of pel array.Advantage of this design is that this will be thermally generated logic circuit and be placed at chip edge, and it can significantly reduce the sensor temperature in pel array.
Therefore, this framework allows tructured sheets epigraph sensing system (iSoC), and wherein PMOS forms excellent photodiode and pixel amplifier, remains as back-end processing circuit simultaneously and provides cost and the performance benefit of CMOS.Because charge storage capacitor can be placed in relatively low layer, in the case of need not outside mechanical shutter, sensor additionally provides the optics shielding of signal memory element.
Fig. 3-6 schematically illustrates out and how can divide various pixel component between PMOS and cmos layer for different valid pixel circuit.Fig. 3 illustrates embodiment, " 4T " the valid pixel circuit and the pinned photodiode that wherein use source follower amplifier (at the parts on the dotted line left side) are formed in PMOS layer, and the NMOS device sampled and keep (S/H) circuit (parts on the right of dotted line) to be formed in cmos layer.Actual background noise 3e-from design at current CMOS can be decreased below 1e-by this structure.
Fig. 4 illustrates the embodiment of the image element circuit with correlated double sampling (CDS).Again, pinned photodiode and source follower parts are formed in PMOS layer, and CDS circuit (parts on the right of dotted line) is formed on and has NMOS In the cmos layer of FET.This embodiment makes bypass capacitor can be formed in CMOS device, such as the MIM capacitor in light blocking metal level, or be formed by interconnection layer.Although such as United States Patent (USP) No.6,902,987 be typically result in forming Ohmic contact directly in conjunction with interconnection technique, but those of ordinary skill in the art understand and can revise perpendicular interconnection technique to leave dielectric gap, thus form the original position capacitor of the necessary type for this specific embodiment.
Fig. 5 is the schematic diagram of the image element circuit of the capacitive character trsanscondutance amplifier (CTIA) with global shutter sampling and holding circuit.Pinned photodiode and the PMOS FET(parts on the dotted line left side) it is arranged in PMOS layer, and NMOS parts are arranged in cmos layer.
Fig. 6 illustrates the alternate embodiment of the image element circuit with global shutter sampling and the capacitive character trsanscondutance amplifier (CTIA) of holding circuit and CDS.In this embodiment, during the PMOS transistor of pinned photodiode and support is formed on PMOS layer.But, CDS capacitor 61 is formed in the metal barrier of intermediate layer, such as Fig. 2, and remaining parts is formed in cmos layer.This structure allows in the case of the design not affecting other layer, forms the biggest capacitor in the intermediate layer.
The design conceives the CMOS can also being applied on cmos image sensor framework.Top layer can be formed in CMOS rather than PMOS.This will cause higher noise level, but will provide the advantage of all electronic shutters, because charge storage cell will be shielded.And, this configuration can be used to develop the least sensor, because peripheral electronic device can be easy to be buried in relatively low layer.Alternately, CMOS is used to be capable of the integrated of more complicated circuit in top layer, for many emerging application, such as the transition time sensor for scene content transmission depth information.
Compareing traditional cmos image sensor, the image sensor architecture of uniqueness described herein provides many advantages.Specifically, imageing sensor can be formed with more than 100db and the SNR of even greater than 160dB.By shielded signal storage capacitor optically below barrier layer, sensor can provide " global shutter " operation in the case of need not outside mechanical shutter.This can reduce the cost being associated with design digital still life camera.
Skilled artisans will appreciate that various reorganizations and the amendment of the preferred embodiment just described can be configured to without departing from scope and spirit of the present invention.It will therefore be appreciated that within the scope of the appended claims, can be differently configured from as specifically described herein, implement the present invention.

Claims (15)

1. an imageing sensor, including:
PMOS circuit layer including array of pixel；
Each pixel element includes:
Pinned photodiode；With
Amplifier, described amplifier includes P-FET transistor；
Including the cmos layer of support image element circuit, described support image element circuit includes N-FET transistor；
The support image element circuit that wherein each pixel element in PMOS layer is coupled in cmos layer.
2. the imageing sensor of claim 1, further includes at the barrier layer formed between described PMOS layer and described cmos layer.
3. the imageing sensor of claim 2, wherein the described support image element circuit in described cmos layer includes storing capacitor for the signal of each pixel, and each signal storage capacitor is by described barrier layer light shield.
4. the imageing sensor of claim 2, wherein said barrier layer includes multiple capacitor, the pixel element during wherein capacitor is electrically connected to described PMOS layer, and the support image element circuit in described cmos layer.
5. the imageing sensor of claim 2, wherein said barrier layer is formed as the metal level of a part for described PMOS or cmos layer.
6. the imageing sensor of claim 2, wherein said barrier layer is the metal level being partially formed in described PMOS layer and described cmos layer.
7. the imageing sensor of claim 3, wherein said cmos layer farther includes the peripheral digital circuit formed along described cmos layer.
8. the imageing sensor of claim 3, wherein said PMOS circuit layer farther includes:
Analog-digital converter (ADC) circuit part including P-FET.
9. the imageing sensor of claim 8, wherein said PMOS circuit layer farther includes:
Post buffer circuits part including P-FET.
10. the imageing sensor of claim 9, wherein said cmos circuit layer farther includes:
Analog-digital converter (ADC) circuit part, it includes the N-FET of the corresponding adc circuit part being connected in described PMOS layer.
The imageing sensor of 11. claim 10, wherein said cmos circuit layer farther includes:
Post buffer circuits part, it includes the N-FET of the corresponding post buffer circuits part being connected in described PMOS layer.
The imageing sensor of 12. claim 11, wherein said cmos layer farther includes the peripheral digital circuit formed along described cmos layer.
The imageing sensor of 13. claim 12, wherein uses wafer (WoW) on wafer to combine described layer.
14. 1 kinds of imageing sensors, including:
Including the PMOS circuit layer of pinned photodiode array of pixel, wherein use electronic global shutter to trigger pel array, and need not mechanical shutter；With
Including the cmos circuit layer of support image element circuit, described cmos circuit layer is formed under described PMOS circuit layer, and includes by described PMOS layer or the capacitor of any intermediate layer light shield.
15. 1 kinds of imageing sensors, including:
PMOS circuit layer, including:
Array of pixel, each pixel element includes:
Pinned photodiode；With
Amplifier, described amplifier includes P-FET transistor；
Analog-digital converter (ADC) circuit part including P-FET；With
Post buffer circuits part including P-FET；
Wherein said ADC and post buffer circuits part are formed in the ring of array of pixel；With
Including the cmos circuit layer of support image element circuit, described support image element circuit includes:
Image element circuit, it includes the N-FET of the corresponding image element circuit being connected in described PMOS circuit layer；
Analog-digital converter (ADC) circuit part, it includes the N-FET of the corresponding adc circuit part being connected in described PMOS circuit layer；With
Post buffer circuits part, it includes the N-FET of the corresponding post buffer circuits part being connected in described PMOS circuit layer；
Electronic global shutter is wherein used to trigger array of pixel, it is not necessary to mechanical shutter.
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