CN102226996B - CMOS and manufacture method thereof - Google Patents
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- CN102226996B CN102226996B CN201110164988.1A CN201110164988A CN102226996B CN 102226996 B CN102226996 B CN 102226996B CN 201110164988 A CN201110164988 A CN 201110164988A CN 102226996 B CN102226996 B CN 102226996B
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Abstract
The invention provides a kind of CMOS and manufacture method thereof.CMOS manufacture method according to the present invention includes step: forms CMOS on a semiconductor substrate and processes circuit structure；Form top layer through hole；Forming top-level metallic structure, described top-level metallic structure includes PN junction upper/lower electrode and metal dummy pattern；Depositing first conductive type amorphous silicon material, and the pixel PN junction realizing the first conduction type amorphous silicon material is structure patterning；And depositing second conductive type type amorphous silicon material, and the pixel PN junction realizing the second conduction type amorphous silicon material is structure patterning, wherein forms photodiode PN junction by the first conduction type amorphous silicon material and the contact of the second conduction type amorphous silicon material.The present invention increases considerably the volume of depletion region, thus on the premise of not increasing Pixel size, not increasing lithographic process steps and do not increase technique and operating voltage, improve the sensitivity of pixel, thus improve the Performance And Reliability of product, and detector cost is greatly lowered.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of CMOS manufacture method, and thus relate to
The CMOS obtained.
Background technology
CMOS is compatible with CMOS technology due to it, thus is rapidly developed.Relative to CCD work
Skill, its technique is completely and CMOS technology is compatible, but acts as at silicon lining by photodiode and CMOS are processed circuit structure one
, thus on the basis of ensureing performance, considerably reduce cost at the end, integrated level can be increased substantially simultaneously, manufacture pixel
Higher product.
Conventional CMOS image sensor uses the method for front lighting photograph, and photodiode and CMOS are processed circuit structure one
Acting as and use same level to realize on a silicon substrate, chip interconnection then manufactures and processes on circuit structure at CMOS, and photosensitive two
On the pipe of pole in order to light by and be not interconnected the arrangement of line；The most whole wiring density all concentrates on CMOS process
Circuit structure part, and photodiode accounts for silicon area and is greater than CMOS process circuit structure, so needs higher wiring
Level realizes function, but higher wiring level can cause the loss of light, causes the decline of performance；It addition, CMOS work
Voltage all ratios are relatively low, and how increasing depletion layer volume under keeping low voltage condition is to improve that of image sensor is important to be asked
Topic；In the recent period it has been proposed that use backlight illuminated technology, silicon chip back side is thinning, make light be irradiated to photosensitive two by silicon chip back side
On the pipe of pole, thus improving performance, but whole technique is extremely complex, brings the highest process complexity and cost.
The most also it has been proposed that make photodiode to process on circuit structure at CMOS, but how to solve light and enter
The problem penetrating decay, how on the premise of not increasing area, increases PN junction area and increases light absorption volume, become this technology
One of key issue faced.
Summary of the invention
Therefore, it is an object of the invention to propose a kind of CMOS that can solve the problem that above-mentioned technical problem and
Its manufacture method.
The invention provides a kind of CMOS manufacture method, including step: formed on a semiconductor substrate
CMOS processes circuit structure；Form top layer through hole；Forming top-level metallic structure, described top-level metallic structure includes PN junction power-on and power-off
Pole and metal dummy pattern；Depositing first conductive type amorphous silicon material, and realize the pixel of the first conduction type amorphous silicon material
PN junction is structure patterning；And depositing second conductive type type amorphous silicon material, and realize the second conduction type amorphous silicon material
Pixel PN junction structure patterning；Wherein, by the first conduction type amorphous silicon material and the second conduction type amorphous silicon material
Contact forms photodiode PN junction.
The CMOS manufacture method of the present invention, by the first conduction type amorphous silicon material and the second conductive-type
Type amorphous silicon material contacts and forms photodiode PN junction, thus increases considerably the volume of depletion region, thus is not increasing
Pixel size, do not increase lithographic process steps and do not increase technique and operating voltage on the premise of, improve pixel sensitivity, from
And improve the Performance And Reliability of product, and detector cost is greatly lowered.Further, the distributed architecture of vertical type solves existing
Have present in technology " needing higher wiring level to cause the decline of the loss memory performance of light to realize function "
Problem.
Preferably, in above-mentioned CMOS manufacture method, form photosensitive two poles by top-level metallic dummy pattern
The concavo-convex contact of pipe PN junction, and described top-level metallic dummy pattern do not make any electrical connection use.
Preferably, in above-mentioned CMOS manufacture method, the first conduction type amorphous silicon material is N-type amorphous
Silicon materials, the second conduction type amorphous silicon material is P-type non-crystalline silicon material；Or the first conduction type amorphous silicon material is p-type
Amorphous silicon material, the second conduction type amorphous silicon material is N-type amorphous silicon material.
Preferably, in above-mentioned CMOS manufacture method, CVD technique is used to manufacture non-crystalline silicon P-type material, its
In pass through SiH4Gas is decomposed to form non-crystalline silicon, and passes through B2H6Impurity gas carries out adulterating in situ.
Preferably, in above-mentioned CMOS manufacture method, CVD technique is used to manufacture non-crystalline silicon n type material, its
In pass through SiH4Gas is decomposed to form non-crystalline silicon, and passes through PH3Carry out adulterating in situ Deng impurity gas.
Preferably, in above-mentioned CMOS manufacture method, by CVD process deposits non-crystalline silicon P-type material and
Non-crystalline silicon n type material, and realize adulterating to form N-type and p-type dopant material by the ion implantation technology of donor and acceptor.
Preferably, in above-mentioned CMOS manufacture method, farther include: in depositing second conductive type type
Amorphous silicon material, and after the pixel PN junction that realizes the second conduction type amorphous silicon material is structure patterning, pass through annealing process
Forming the good contact of metal and silicon Si, annealing temperature is 350 DEG C-450 DEG C.
Preferably, in above-mentioned CMOS manufacture method, the CMOS formed on a semiconductor substrate processes electricity
Road is that process for copper CMOS processes circuit or Al technique CMOS processes circuit.
Preferably, in above-mentioned CMOS manufacture method, by top-level metallic one one-step film forming technique and figure
Metallization processes realizes top-level metallic structure.
Preferably, in above-mentioned CMOS manufacture method, top layer through hole is for by photodiode PN junction
Signal is transferred to chip interconnecting line and CMOS processes circuit structure.
Preferably, in above-mentioned CMOS manufacture method, PN junction upper/lower electrode is arranged in above top layer through hole
And contact with top layer through hole.
Preferably, in above-mentioned CMOS manufacture method, form metal semiconductor by individual layer hearth electrode
Contact.
The present invention additionally provides the CMOS image that the CMOS manufacture method described in a kind of basis is made simultaneously
Sensor, wherein, arranges CMOS on substrate and processes circuit structure, and arrange on described CMOS process circuit structure
The photodiode PN junction contacting by the first conduction type amorphous silicon material and the second conduction type amorphous silicon material and being formed.
Further, the distributed architecture of vertical type solve present in prior art " need higher wiring level realizing function thus
Cause light loss memory performance decline " problem.
Equally, the CMOS of the present invention, by the first conduction type amorphous silicon material and the second conduction type
Amorphous silicon material contact (especially with the concavo-convex dummy pattern of top-level metallic) forms photodiode PN junction, thus significantly
Degree increases the volume of depletion region, thus is not increasing Pixel size, do not increasing lithographic process steps and do not increase technique and work
On the premise of voltage, improve the sensitivity of pixel, thus improve the Performance And Reliability of product, and detector is greatly lowered
This.
And, it is preferable that described CMOS is the CMOS manufacturer's legal system according to the present invention
Make.
Preferably, in described CMOS, top-level metallic dummy pattern forms the recessed of photodiode PN junction
Convex contact, and top-level metallic dummy pattern do not make any electrical connection use.
Preferably, in described CMOS, the first conduction type amorphous silicon material is N-type non-crystalline silicon material
Material, the second conduction type amorphous silicon material is P-type non-crystalline silicon material；Or the first conduction type amorphous silicon material is p-type amorphous
Silicon materials, the second conduction type amorphous silicon material is N-type amorphous silicon material.
Preferably, in described CMOS, formed the contact of metal semiconductor by individual layer hearth electrode, logical
Cross the concavo-convex dummy pattern of top-level metallic to form photodiode PN junction.
Preferably, in above-mentioned CMOS, top layer through hole is for transmitting the signal of photodiode PN junction
Circuit structure is processed to chip interconnecting line and CMOS.
Preferably, in above-mentioned CMOS, PN junction upper/lower electrode is arranged in above top layer through hole and and top layer
Through hole contacts.
It will be appreciated by persons skilled in the art that and be capable of equally according to CMOS of the present invention
According to the Advantageous Effects achieved by CMOS manufacture method of the present invention.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 shows the profile of the structure of the CMOS according to one specific embodiment of the present invention；
Fig. 2 shows the profile of the structure of the CMOS according to another specific embodiment of the present invention；And
Fig. 3 shows the flow chart of CMOS manufacture method according to embodiments of the present invention.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Further, in accompanying drawing, identical or class
As element indicate same or like label.Note, represent that the accompanying drawing of structure may be not necessarily drawn to scale.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 1 shows the profile of the structure of CMOS according to embodiments of the present invention.
In this embodiment, the photodiode of this CMOS is positioned at CMOS and processes on circuit structure 1, and
Good contact by individual layer hearth electrode schematic design making metal semiconductor.Photodiode converts the light to the signal of telecommunication, and passes through
Chip interconnection is transferred directly to CMOS and processes circuit structure (being made up of cmos device), through circuit moulds such as amplification, digital-to-analogue conversions
Block realizes the function required for client, as image shows.By by the first conduction type amorphous silicon material and the second conduction
Type amorphous silicon material contact (especially with the concavo-convex dummy pattern of top-level metallic) forms photodiode PN junction, thus
Increase considerably the volume of depletion region, thus do not increase Pixel size, do not increase lithographic process steps and do not increase technique and
On the premise of operating voltage, improve the sensitivity of pixel, thus improve the Performance And Reliability of product, and detection is greatly lowered
Device cost.Further, the distributed architecture of the vertical type of the embodiment of the present invention solves " needs higher cloth present in prior art
Line level realize function thus cause light loss memory performance decline " problem.
Further, one embodiment of the present of invention proposes a kind of CMOS based on silicon chip surface photodiode
Manufacture method.Fig. 3 shows the flow chart of the CMOS manufacture method of a specific embodiment according to the present invention,
Can be used for the CMOS manufactured as shown in Figure 1.
Specifically, the CMOS manufacture method of the embodiment of the present invention can comprise the following steps that
In step sl, form CMOS the most on a semiconductor substrate and process circuit structure 1.
Then, in step s 2, the structure of top layer through hole 2, the top layer through hole of such as W shape are formed.This top layer through hole 2 is used for
Photodiode PN junction signal is transferred to chip interconnecting line and cmos device (CMOS processes circuit structure), but its function is also
It is interconnection, in some sense, it is also possible to be attributed to interconnection structure；Therefore this top layer through hole 2 can be considered of interconnection structure
Point.Further, medium, this medium e.g. silica (SiO are arranged between top layer through hole2) material.
Afterwards, in step s3, on the basis of obtained structure, top-level metallic structure (such as Al), this top are formed
Layer metal structure includes PN junction upper/lower electrode 3 and metal dummy pattern 4.As depicted in figs. 1 and 2, PN junction upper/lower electrode 3 is arranged in top
Contact above layer through hole 2 and with top layer through hole 2.
Afterwards, in step s 4, H is passed through2PN junction upper/lower electrode 3 surface oxide that may be present is removed in reaction reduction,
Then deposited n-type amorphous silicon material 5 such as 3000A, by (in-situ) PH in situ3Doping realizes impurity concentration needed for it.
Afterwards, in step s 5, it is achieved the pixel PN junction of N-type amorphous silicon material 5 is structure patterning, including etching N-type material
Material exposes electrode pattern.
Afterwards, in step s 6, H is passed through2N-type amorphous silicon material 5 is removed in reaction reduction and upper electrode patterned surface may
The oxide existed, deposits P-type non-crystalline silicon material 6 such as 3000A, by original position B2H6Doping realizes impurity concentration needed for it.
Afterwards, in the step s 7, it is achieved the pixel PN junction of P-type non-crystalline silicon material 6 is structure patterning, it is achieved PN junction photosensitive two
Pole tubular construction；The most just by PN junction upper/lower electrode 3 and through hole 2, signal can be introduced CMOS and process on circuit structure 1, be formed
CMOS structure.
More specifically, in some specific embodiments of the present invention, the manufacturing process of non-crystalline silicon P-type material can be
CVD technology, passes through SiH4Gas is decomposed to form non-crystalline silicon, passes through B2H6Deng impurity gas CVD technology original position doping realize
Its manufacturing process, its film-forming temperature is 20 DEG C-50 DEG C.
In some specific embodiments of the present invention, the manufacturing process of non-crystalline silicon n type material is CVD technology, passes through SiH4
Gas is decomposed to form non-crystalline silicon, passes through PH3Deng impurity gas CVD technology original position doping realize its manufacturing process, its become
Film temperature is 20 DEG C-50 DEG C.
In some specific embodiments of the present invention, photodiode PN junction is to be connect by P-type non-crystalline silicon and N-type non-crystalline silicon
Touching formation, the concavo-convex contact of its PN junction is formed by top-level metallic dummy pattern 4, and this dummy pattern 4 does not make any electrical connection
Use.
In some specific embodiments of the present invention, the material of top-level metallic and top layer through hole 2 is metal Ta, TaN, Ti,
The composite bed electrode 3 of TiN, Al, W, Cr and above-mentioned material.
Preferably, upper/lower electrode and top-level metallic dummy pattern (that is, top-level metallic structure) are to be become by top-level metallic one step
Membrane process and patterning process realize.
In some specific embodiments of the present invention, after on top-level metallic, p-type and N-type amorphous silicon material 5 figure are formed, logical
Crossing annealing process and form the good contact of metal and Si, for not affecting lower metal interconnection and cmos device, annealing temperature is 350
℃-450℃。
In some specific embodiments of the present invention, the substrate and CMOS under top-level metallic and top layer through hole 2 processes circuit
The manufacture craft of structure 1 can be that process for copper CMOS processes circuit or Al technique CMOS processes circuit.
In some specific embodiments of the present invention, the manufacturing process of non-crystalline silicon P-type material and n type material is CVD technology,
Its doping requirement can be realized by the ion implantation technology of donor and acceptor.
Further, one of ordinary skill in the art will appreciate that and embodiment can be made various amendment, such as, p-type
Can be replaced by lower floor with the order of n type material is p-type, and upper strata is N-type amorphous silicon material.
Additionally, this structure of photodiode PN junction of the embodiment of the present invention, it is preferable that can be formed by low temperature；Adopt
The reason forming photodiode PN junction with low temperature process is: whole photodiode PN junction photosensitive structure is in CMOS standard work
On skill, the most do not use high temperature, to avoid cmos device and chip are interconnected producing impact.Such as, the low temperature of low temperature process
Scope is between 200 degrees Celsius to 500 degrees Celsius.
One of ordinary skill in the art will appreciate that the device that present disclosure applies equally to which floor interconnection structure there is
Part.Fig. 2 shows the profile of the structure of the CMOS according to another specific embodiment of the present invention.Shown in Fig. 1
The structure difference of CMOS be, the structure of the CMOS shown in Fig. 2 shows that two-layer is mutual
Link structure.Multilayer interconnection structure does not interferes with enforcement and the effect of the present invention.
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
Claims (17)
1. a CMOS manufacture method, it is characterised in that include step:
Form CMOS on a semiconductor substrate and process circuit structure；
Form top layer through hole；
Forming top-level metallic structure, described top-level metallic structure includes PN junction upper/lower electrode and top-level metallic dummy pattern；Deposition the
One conduction type amorphous silicon material, and the pixel PN junction realizing the first conduction type amorphous silicon material is structure patterning；And
Depositing second conductive type amorphous silicon material, and realize the pixel PN junction structure graph of the second conduction type amorphous silicon material
Change,
Wherein, formation photodiode is contacted by the first conduction type amorphous silicon material and the second conduction type amorphous silicon material
PN junction；The concavo-convex contact of photodiode PN junction, and described top-level metallic dummy pattern is formed by top-level metallic dummy pattern
Do not make any electrical connection to use.
CMOS manufacture method the most according to claim 1, it is characterised in that wherein the first conduction type is non-
Crystal silicon material is N-type amorphous silicon material, and the second conduction type amorphous silicon material is P-type non-crystalline silicon material；Or the first conductive-type
Type amorphous silicon material is P-type non-crystalline silicon material, and the second conduction type amorphous silicon material is N-type amorphous silicon material.
CMOS manufacture method the most according to claim 2, it is characterised in that wherein use CVD technique system
Make P-type non-crystalline silicon material, wherein pass through SiH4Gas is decomposed to form non-crystalline silicon, and passes through B2H6Impurity gas carries out adulterating in situ.
CMOS manufacture method the most according to claim 2, it is characterised in that wherein use CVD technique system
Make N-type amorphous silicon material, wherein pass through SiH4Gas is decomposed to form non-crystalline silicon, and passes through PH3Carry out mixing in situ Deng impurity gas
Miscellaneous.
CMOS manufacture method the most according to claim 2, it is characterised in that wherein sunk by CVD technique
Long-pending P-type non-crystalline silicon material and N-type amorphous silicon material, and realize adulterating to be formed by the ion implantation technology of donor and acceptor
N-type and p-type dopant material.
CMOS manufacture method the most according to claim 1, it is characterised in that farther include: in deposition
Second conduction type amorphous silicon material, and after the pixel PN junction that realizes the second conduction type amorphous silicon material is structure patterning,
Formed the good contact of metal and silicon by annealing process, annealing temperature is 350 DEG C-450 DEG C.
CMOS manufacture method the most according to claim 1, it is characterised in that the most on a semiconductor substrate
It is that process for copper CMOS processes circuit or Al technique CMOS processes circuit that the CMOS formed processes circuit.
CMOS manufacture method the most according to claim 1, it is characterised in that wherein by top-level metallic one
One-step film forming technique and patterning process realize top-level metallic structure.
CMOS manufacture method the most according to claim 1, it is characterised in that wherein top layer through hole is by photosensitive
The signal of diode PN junction is transferred to chip interconnecting line and CMOS processes circuit structure.
CMOS manufacture method the most according to claim 1, it is characterised in that wherein PN junction upper/lower electrode
It is arranged in above top layer through hole and contacts with top layer through hole.
11. CMOS manufacture methods according to claim 1, wherein said PN junction upper/lower electrode and described top
Layer metal dummy pattern is positioned in same layer.
12. 1 kinds of CMOS, wherein, arrange CMOS on substrate and process circuit structure, in described CMOS process
Circuit structure surface configuration top layer through hole and the medium being positioned between described top layer through hole, on the described top layer through hole and given an account of
Being provided with top-level metallic structure in matter, described top-level metallic structure includes PN junction upper/lower electrode and top-level metallic dummy pattern, in institute
State and be disposed through the first conduction type amorphous on the described medium of top-level metallic dummy pattern, described PN junction upper/lower electrode and exposure
The photodiode PN junction that silicon materials and the second conduction type amorphous silicon material contact and formed；Wherein top-level metallic dummy pattern shape
Become the concavo-convex contact of photodiode PN junction, and top-level metallic dummy pattern is not made any electrical connection and used.
13. CMOS according to claim 12, wherein said CMOS is according to above-mentioned power
Profit requires what the CMOS manufacture method of one of 1-11 manufactured.
14. according to the CMOS described in claim 12 or 13, wherein said PN junction upper/lower electrode and described top layer
Metal dummy pattern is positioned in same layer.
15. according to the CMOS described in claim 12 or 13, and wherein the first conduction type amorphous silicon material is N-type
Amorphous silicon material, the second conduction type amorphous silicon material is P-type non-crystalline silicon material；Or the first conduction type amorphous silicon material is
P-type non-crystalline silicon material, the second conduction type amorphous silicon material is N-type amorphous silicon material.
16. according to the CMOS described in claim 12 or 13, and wherein top layer through hole is for by photodiode PN
The signal of knot is transferred to chip interconnecting line and CMOS processes circuit structure.
17. according to the CMOS described in claim 12 or 13, and wherein PN junction upper/lower electrode is arranged in top layer through hole
Top also contacts with top layer through hole.
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| US8637800B2 (en) * | 2011-04-19 | 2014-01-28 | Altasens, Inc. | Image sensor with hybrid heterostructure |
| CN106331535A (en) * | 2015-07-06 | 2017-01-11 | 上海瑞艾立光电技术有限公司 | Image collection system |
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| CN101546777A (en) * | 2009-05-08 | 2009-09-30 | 北京思比科微电子技术有限公司 | Soi cmos image sensor structure and manufacturing method thereof |
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| US6501065B1 (en) * | 1999-12-29 | 2002-12-31 | Intel Corporation | Image sensor using a thin film photodiode above active CMOS circuitry |
| US6995411B2 (en) * | 2004-02-18 | 2006-02-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor with vertically integrated thin-film photodiode |
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