CN103779424B - A kind of amorphous state gallium nitride or indium nitride film transistor and preparation method thereof - Google Patents
A kind of amorphous state gallium nitride or indium nitride film transistor and preparation method thereof Download PDFInfo
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- CN103779424B CN103779424B CN201410026623.6A CN201410026623A CN103779424B CN 103779424 B CN103779424 B CN 103779424B CN 201410026623 A CN201410026623 A CN 201410026623A CN 103779424 B CN103779424 B CN 103779424B
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 65
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 57
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 239000010408 film Substances 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000006243 chemical reaction Methods 0.000 claims abstract description 30
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000002019 doping agent Substances 0.000 claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 20
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910000077 silane Inorganic materials 0.000 claims abstract description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 14
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052749 magnesium Inorganic materials 0.000 claims abstract description 11
- 239000011777 magnesium Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000001257 hydrogen Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 6
- 239000012159 carrier gas Substances 0.000 claims abstract description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 95
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000002346 layers by function Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- -1 silicon Alkane Chemical class 0.000 claims description 3
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000008901 benefit Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000004062 sedimentation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003980 solgel method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000001338 self-assembly Methods 0.000 description 2
- 229910052984 zinc sulfide Inorganic materials 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 230000036244 malformation Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 239000002562 thickening agent Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of function film preparation method and application field, a kind of amorphous state gallium nitride or indium nitride film transistor and preparation method thereof are refered in particular to.Using plasma chemical vapour deposition technique, reaction source is used as by the use of organic source, ammonia；By the use of hydrogen or nitrogen as organic source carrier gas source, by the use of silane, trimethyl magnesium as dopant, n-type, p-type amorphous state gallium nitride or indium nitride are prepared respectively on substrate；And the channel layer of thin film transistor (TFT) is used as using n-type, p-type amorphous state gallium nitride or indium nitride film, the amorphous state gallium nitride or indium nitride film and amorphous state gallium nitride or indium nitride film transistor made by this method is obtained on cheap substrate, therefore greatly reduces manufacturing cost；The material uniformity coefficient height of the present invention, low impurity content, device and the advantages of big substrate adhesive force；Other the inventive method have the advantages that it is easy to operate, continuously produced suitable for large area.
Description
Technical field
The present invention relates to a kind of function film preparation method and application field, a kind of amorphous state gallium nitride or indium nitride are refered in particular to
Thin film transistor (TFT) and preparation method thereof.
Background technology
The III nitride semiconductor being made up of InN, GaN, AlN and its alloy is the class broad stopband of currently the most important ones one
Semiconductor, its Thermodynamically stable structure is wurtzite structure, and the wurtzite structure crystal of group III-nitride is with tetrahedral structure
Based on, the order for being the diatomic layer by Hexagonal array regularly by ABAB with six side's symmetry ..., which is stacked, to be formed（<
0111>Direction）, by these characteristics that group III-nitride has, its main application fields includes semiconductor lighting, DVD
Optical storage, detector（Number of patent application：200810019832.2,200810019835.6）And high temperature, high frequency, high power are micro-
Wave device；For example, nearly Thailand of family et al.（Number of patent application：0212445.5）There is provided a kind of compound semiconductor of 3 ~ 5 races, and
Applied to light emitting diode；In addition, Zhao Yanli et al.（Number of patent application：200910060799.2）Utilize semiconductor epitaxial layers
Growth also achieves the research and development of GaN base light emitting；Kang Xiang is peaceful et al.（Number of patent application：200510073285.2,
200610167605.5）Propose a kind of high-luminance chip of luminescent tube in GaN base and preparation method thereof and reduction GaN single crystal film
The method of stress between hetero-substrates.
The preparation method of group III-nitride includes molecular beam epitaxy, organic molecule vapour phase epitaxy, pyrolyzing synthesis powder material
Material and sol-gel process（Number of patent application：03110867.9）Deng；In addition to sol-gel process, group III-nitride is typically different
Matter extension in c surface sapphire substrates, and lattice and thermal mismatching between c surface sapphire substrates and c faces group III-nitride all compared with
Greatly, so cause to produce substantial amounts of dislocation and defect during extension, and cause epitaxial crystal malformation, so as to produce
Piezoelectric polarization fields, piezoelectric polarization fields, which can equally change crystal, the distribution in electronics and hole is staggered with distribution, and make effectively taboo
Bandwidth reduces, and excites Dependent Red Shift；Sol-gel process, which prepares group III-nitride, to be needed to mix some macromolecule material thickeners,
Therefore impurity content is relatively more；In recent years, Zhao Guijuan et al.（Number of patent application：201210313725.7）It is non-in Grown
Polarity A faces InGaN flexible layers, then grow GaN cushions, to non polarity A side InGaN on non polarity A side InGaN flexible layers
Flexible layer and non polarity A side GaN cushions are made annealing treatment, and form self assembly horizontal extension template, and horizontal in self assembly
Growing nonpolar A face GaN films on to epitaxial template；Shut out state with et al.（Number of patent application：201010554940.7）Utilize SiC
The advantage that substrate lattice and GaN are matched, makes a kind of vertical structure light-emitting pipe on sic substrates, meanwhile, multilayer can also be used
Group III-nitride prepares SAW device on diamond thick-film substrate（Number of patent application：201110062224.1）.
As can be seen here, in terms of amorphous state gallium nitride or nitridation phosphide material and device preparation, research staff has been carried out
Substantial amounts of work, but new substrate and new technology are either utilized, current production cost is still higher, and technics comparing is lengthy and jumbled；
The invention provides one kind in general substrate, such as glass, pi flexiplast or monocrystalline silicon piece, chemical gaseous phase is utilized
Deposition technique prepares the system of amorphous state gallium nitride or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor devices
The advantages of Preparation Method, material uniformity coefficient height, low impurity content, device and big substrate adhesive force for being made by this method；Separately
Outer preparation method have it is easy to operate, suitable for large area quantity-produced advantage.
The content of the invention
Present invention aims at provide a kind of amorphous state gallium nitride and amorphous state indium nitride film and amorphous state gallium nitride and
The preparation method of amorphous state indium nitride film semiconductor devices, using plasma chemical vapour deposition technique, using organic source,
Ammonia is used as reaction source；By the use of hydrogen or nitrogen as organic source carrier gas source, by the use of silane, trimethyl magnesium as dopant,
Substrate（Such as silicon chip, glass or plastics）It is upper to prepare n-type, p-type amorphous state gallium nitride or indium nitride respectively；And with n-type, p-type amorphous
State gallium nitride or indium nitride film are as the channel layer of thin film transistor (TFT), and its thin-film transistor structure as depicted in figs. 1 and 2, leads to
The amorphous state gallium nitride or indium nitride film and amorphous state gallium nitride or indium nitride film transistor for crossing this method making are honest and clean
Obtained on the substrate of valency, therefore greatly reduce manufacturing cost；The material uniformity coefficient of the present invention is high, impurity content is low, device
The advantages of part and big substrate adhesive force；Other the inventive method have the advantages that it is easy to operate, continuously produced suitable for large area.
The technical solution adopted for the present invention to solve the technical problems is：Using plasma chemical vapour deposition technique,
Reaction source is used as by the use of organic source, ammonia；By the use of hydrogen or nitrogen as organic source carrier gas source, made using silane, trimethyl magnesium
For dopant, n-type, p-type amorphous state gallium nitride or amorphous state indium nitride film are prepared respectively on substrate；With n-type, p-type amorphous
State gallium nitride or amorphous state indium nitride prepare top-grate structure thin film transistor and bottom grating structure are thin as thin film transistor channel layer
Film transistor.
Preferably, described plasma chemical vapor deposition technique prepares amorphous state gallium nitride or amorphous state indium nitride
In thin-film process, its technological parameter is：Organic source and ammonia mass flow ratio are 1:2~ 1:1, radio-frequency power is 50 ~ 350
W, reaction pressure is 20 ~ 200 Pa；Described underlayer temperature is room temperature to 350 DEG C.
Described dopant is n-type dopant or p-type dopant；Wherein, dopant and organic source mass flow mixing ratio
Example is 1% ~ 20%, and organic source and ammonia mass flow mixed proportion are 1：2~1：1；Wherein described n-type dopant, p-type doping
Agent can select trimethyl magnesium and silane respectively, and described organic source is trimethyl gallium, triethyl-gallium or trimethyl indium.
Described top-grate structure thin film transistor by substrate, barrier layer, channel layer, source electrode, gate dielectric layer, gate electrode and
Drain electrode is constituted, and is barrier layer above substrate, and barrier layer top is that both sides are respectively source-drain electrode above channel layer, channel layer,
It is to be splashed above gate dielectric layer, gate dielectric layer for gate electrode, transistor by chemical vapor deposition and magnetic control in the middle of above channel layer
The superposition growth that each functional layer is completed with reference to mask process is penetrated, concrete structure is as shown in figure 1, manufacturing process is shown in embodiment.
Described bottom grating structure thin film transistor (TFT) by substrate, gate electrode, gate dielectric layer, channel layer, source electrode and drain electrode,
It is gate electrode above composition, substrate, gate electrode top is to be above gate dielectric layer, gate dielectric layer two above channel layer, channel layer
Side is respectively source electrode and drain electrode, and transistor completes each function by chemical vapor deposition and magnetron sputtering combination mask process
The superposition growth of layer, concrete structure is as shown in Fig. 2 manufacturing process is shown in embodiment.
Described top-grate structure thin film transistor by substrate, barrier layer, channel layer, source electrode, gate dielectric layer, gate electrode and
Drain electrode is constituted, and is connected, is first prepared on the substrate through over cleaning with the formation of other films by the film layer of itself per layer film
Barrier layer, in barrier layer surface using PECVD methods channel layer is prepared, then existed using magnetically controlled sputter method combination mask process
Channel layer surface prepares source electrode and drain electrode, recycles PECVD method combination mask process to prepare grid in channel layer surface and is situated between
Matter layer, finally prepares gate electrode, concrete structure as shown in figure 1, manufacturing process is shown in reality on gate dielectric layer surface using magnetron sputtering
Apply example.
Described bottom grating structure thin film transistor (TFT) is by substrate, gate electrode, gate dielectric layer, channel layer, source electrode and drain electrode
Composition, is connected with the formation of other films by the film layer of itself per layer film, is first splashed on the substrate through over cleaning using magnetic control
Penetrate and prepare gate electrode, then prepare gate dielectric layer using PECVD methods in surface gate electrode, then utilized on gate dielectric layer surface
PECVD prepares channel layer, recycles mask plate technique combination magnetron sputtering to prepare source electrode and drain electrode in channel layer surface.
The substrate is glass, pi flexiplast or monocrystalline silicon piece.
Preferably, described top-grate structure thin film transistor, using silica or silicon nitride film as barrier layer,
Thickness is 100 ~ 2000nm.
Preferably, in described amorphous state gallium nitride or indium nitride film transistor, gate dielectric layer selection silica
Or silicon nitride, thickness is 200 ~ 5000 nm；Its silica preparation technology parameter is：It is passed through the oxygen that flow is 30 ~ 90 sccm
Gas, flow is 5 ~ 20 sccm silane；It is 10 ~ 200 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 30 ~ 200W；Lining
Bottom temperature is 20 ~ 200 DEG C；Its silicon nitride preparation technology parameter is：The nitrogen that flow is 30 ~ 90 sccm is passed through, flow is 5 ~ 20
Sccm silane；It is 10 ~ 200 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 30 ~ 200W；Underlayer temperature be 200 ~
400℃。
Preferably, in described amorphous state gallium nitride or indium nitride film transistor, gate electrode, source electrode, drain electrode
From metal and the metal oxide materials of conduction, thickness is 50 ~ 500nm；Wherein, the source electrode of bottom grating structure transistor, leakage
A length of 800 ~ 1200 μm of electrode, a width of 100 ~ 150 μm, spacing is 50 ~ 100 μm between source electrode, drain electrode, and gate electrode is a length of
800 ~ 1200 μm, a width of 250 ~ 400 μm；A length of 800 ~ 1200 μm of the source electrode of top gate structure transistor, drain electrode, a width of 100 ~
150 μm, spacing is 50 ~ 100 μm, a length of 800 ~ 1200 μm, a width of 50 ~ 90 μm of gate electrode between source electrode, drain electrode.
Preferably, in described amorphous state gallium nitride or indium nitride film transistor, channel layer is adulterated from n or p-type
Amorphous state gallium nitride or indium nitride film, thickness be 10 ~ 1000 nm.
Compared with amorphous state gallium nitride or indium nitride semiconductor devices, amorphous state gallium nitride or indium nitride film of the present invention and
Amorphous state gallium nitride or indium nitride film semiconductor devices have following advantage：
Amorphous state gallium nitride or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor devices of the present invention
Preparation method is simple, it is abundant, cheap to make raw material sources, can be prepared by matrix of cheap material；Amorphous state of the present invention
The preparation technology and micro-electronic machining of gallium nitride or indium nitride film and amorphous state gallium nitride or indium nitride film semiconductor devices
Process compatible, varies without other existing equipmenies, and repeatability and uniformity are high, are continuously produced suitable for large area；The present invention
Semiconductor devices can be used widely in fields such as Display Technique, signal switch technology, sensing technologies.
Brief description of the drawings
Top gate structure amorphous state gallium nitride (indium) thin film transistor (TFT) schematic cross-section that Fig. 1 is prepared for the present invention；
1, substrate；2, channel layer；3, source electrode；4, gate dielectric layer；5, gate electrode；6, drain electrode；7, barrier layer.
Bottom grating structure amorphous state gallium nitride (indium) thin film transistor (TFT) schematic cross-section that Fig. 2 is prepared for the present invention；
1, substrate；2, channel layer；3, source electrode；4, gate dielectric layer；5, gate electrode；6, drain electrode.
Embodiment
The present invention is described in further detail with reference to embodiment, in the case where not violating the purport of the present invention, this hair
The bright example laboratory that should be not limited to specifically expresses content.
Raw materials are as follows：
Silane：Purity is 99.9%；Hydrogen：Purity is 99.9%；Trimethyl gallium, triethyl-gallium, trimethyl indium, trimethyl magnesium
Deng purity is 99.99%；Oxygen：Purity is 99.95%；Nitrogen：Purity is 99.95%.
Amorphous state gallium nitride of the present invention, indium nitride film crystal tube preparation method comprise the following steps：
1. substrate prepares：Wherein substrate is from silicon chip, glass or flexible sub- polyamide.
2. prepared by gate electrode, source electrode, drain electrode, from metal and the metal oxide materials of conduction.
3. prepared by gate dielectric layer, wherein gate dielectric layer selection silica or silicon nitride.
4. prepared by channel layer, wherein channel layer selects n-type or p-type amorphous state gallium nitride or amorphous state indium nitride film.
5. barrier layer is used as using silica or silicon nitride film.
Embodiment 1：The preparation of top gate structure amorphous state gallium nitride film transistor
1. a pair glass substrate is cleaned.
2. using the silicon nitride film that PECVD technique growth thickness is 300 nm, it is used as device barrier layer；Being passed through flow is
40 sccm ammonia, flow is 20 sccm silane；It is 35 Pa to control reaction chamber pressure；It is 100 to adjust radio-frequency power
W；Underlayer temperature is 250 DEG C
3. it is used as channel layer by the use of PECVD technique growth thickness for 100 nm n-type amorphous state gallium nitride film；It is passed through stream
Measure as 30 sccm trimethyl gallium, flow is 40 sccm ammonia, flow is used as n-type dopant for 5sccm trimethyl magnesium；
Reaction pressure is 100 Pa, and adjustment radio-frequency power is 150 W, 200 DEG C of underlayer temperature.
4. utilize IZO source electrode and drain electrode of the magnetron sputtering technique growth thickness for 150 nm；Source electrode, drain electrode life
When long, pattern is generated using mask technique, mask plate width is 150 mm, and length is 1000 mm, and electrode spacing is 80mm；Splash
During penetrating, use Ar for protective gas, flow is 14sccm, IZO films, wherein reaction pressure are prepared for using IZO targets
For 0.5 Pa, radio-frequency power is 100W, the min of sputtering sedimentation 15.
5. using self-registered technology using PECVD technique, growth length is 1000mm between source electrode and drain electrode, wide
Spend for 70mm, thickness is 800 nm silica, is used as gate dielectric layer；The oxygen that flow is 40 sccm is passed through, flow is 10
Sccm silane；It is 35 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 100 W；Underlayer temperature is 25 DEG C of room temperature.
6. be that 200 nm, length are 1000 mm using magnetron sputtering technique growth thickness, width for 70 mm ITO grid electricity
Pole；In sputter procedure, use Ar for protective gas, flow is 14sccm, ITO films are prepared for using ITO target, wherein instead
It is 0.5 Pa to answer pressure, and radio-frequency power is 100W, the min of sputtering sedimentation 20.
Embodiment 2：The preparation of bottom grating structure amorphous state indium nitride film transistor
1. utilizing in the ITO gate electrodes that magnetron sputtering technique growth thickness is 100 nm, sputter procedure, Ar is used for guarantor
Gas is protected, flow is 14sccm, prepare ITO films using ITO target, wherein reaction pressure is 0.5 Pa, and radio-frequency power is
100W, the min of sputtering sedimentation 10.
2. it is 1000mm in surface gate electrode growth length to utilize PECVD technique combination mask process, width is 360mm,
Thickness is 800 nm silica, as gate dielectric layer, is passed through the oxygen that flow is 40 sccm, and flow is 10 sccm silicon
Alkane；It is 35 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 100 W；Underlayer temperature is 25 DEG C of room temperature.
3. it is 1000mm in gate dielectric layer superficial growth length to utilize PECVD technique combination mask process, width is 360mm
The p-type amorphous state indium nitride film that thickness is 80 nm is passed through the trimethyl indium that flow is 30 sccm as channel layer, and flow is
40 sccm ammonia, flow is used as p-type dopant for 3sccm silane；Adjustment radio-frequency power is 150 W, underlayer temperature 200
DEG C, reaction pressure is 50 Pa.
4. using IZO source electrode and drain electrode of the magnetron sputtering technique growth thickness for 200 nm, during electrode growth, use
Mask technique generates pattern, and length is 1000 mm, and width is 150 mm, and electrode spacing is 60 mm；In sputter procedure, using Ar
For protective gas, flow is 14sccm, is prepared for IZO films using IZO targets, wherein reaction pressure is 0.5 Pa, radio frequency work(
Rate is 100W, and sputtering time is 20min.
Embodiment 3：The preparation of top gate structure amorphous state gallium nitride film transistor
1. a pair glass substrate is strictly cleaned.
2. by the use of the PECVD technique silica that growth thickness is 800nm on a glass substrate as barrier layer, it is passed through stream
Measure as 40 sccm oxygen, flow is 10 sccm silane；It is 35 Pa to control reaction chamber pressure；Adjusting radio-frequency power is
100 W；Underlayer temperature is 50 DEG C.
3. it is used as channel layer by the use of PECVD technique growth thickness for 40 nm n-type amorphous state gallium nitride film；It is passed through stream
Measure as 30 sccm trimethyl gallium, flow is 40 sccm ammonia, flow is used as n-type dopant for 5sccm trimethyl magnesium；
Adjustment radio-frequency power is 150 W, 200 DEG C of underlayer temperature；Reaction pressure is 150 Pa.
4. using IZO source electrode and drain electrode of the magnetron sputtering technique growth thickness for 100 nm, during electrode growth, use
Mask technique generates pattern, and length is 1200 mm, and width is 150 mm, and spacing is 100mm；In sputter procedure, Ar is used for guarantor
Gas is protected, flow is 14sccm, be prepared for IZO films using IZO targets, wherein reaction pressure is 0.5 Pa, and radio-frequency power is
100W。
5. using self-registered technology using PECVD technique, growth length is 1000mm between source electrode and drain electrode, wide
Spend for 90mm, growth thickness is 800 nm silica, as gate dielectric layer, be passed through the oxygen that flow is 40 sccm, flow
For 10 sccm silane；It is 35 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 100 W；Underlayer temperature is 100 DEG C.
6. being 200 nm using magnetron sputtering technique growth thickness, length is 1000mm, and width is electric for 90mm ITO grid
Pole；In sputter procedure, use Ar for protective gas, flow is 14sccm, ITO films are prepared for using ITO target, wherein instead
It is 0.5 Pa to answer pressure, and radio-frequency power is 100W.
Embodiment 4：The preparation of top gate structure amorphous state indium nitride film transistor
1. a pair glass substrate is strictly cleaned.
2. by the use of the PECVD technique silica that growth thickness is 1000nm on a glass substrate as barrier layer, it is passed through
Flow is 40 sccm oxygen, and flow is 10 sccm silane；It is 35 Pa to control reaction chamber pressure；Adjust radio-frequency power
For 100 W；Underlayer temperature is 50 DEG C.
3. it is used as channel layer by the use of PECVD technique growth thickness for 50 nm n-type amorphous state indium nitride film；It is passed through stream
Measure as 30 sccm trimethyl indium, flow is 40 sccm ammonia, flow is used as n-type dopant for 5sccm trimethyl magnesium；
Adjustment radio-frequency power is 150 W, 200 DEG C of underlayer temperature；Reaction pressure is 200 Pa.
4. using IZO source electrode and drain electrode of the magnetron sputtering technique growth thickness for 150 nm, during electrode growth, use
Mask technique generates pattern, and length is 1000 mm, and width is 120 mm, and electrode spacing is 80 mm, in sputter procedure, using Ar
For protective gas, flow is 14sccm, is prepared for IZO films using IZO targets, wherein reaction pressure is 0.5 Pa, radio frequency work(
Rate is 100W.
5. using self-registered technology using PECVD technique, growth length is 1000mm between source electrode and drain electrode, wide
Spend for 70mm, growth thickness is 1000 nm silica, as gate dielectric layer, be passed through the oxygen that flow is 40 sccm, stream
Measure as 10 sccm silane；It is 35 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 100 W；Underlayer temperature is room temperature
100℃。
6. be that 100 nm, length are 1000mm using magnetron sputtering technique growth thickness, width for 70mm ITO grid electricity
In pole, sputter procedure, use Ar for protective gas, flow is 14sccm, ITO films are prepared for using ITO target, wherein instead
It is 0.5 Pa to answer pressure, and radio-frequency power is 100W, sputtering sedimentation 10min.
Embodiment 5：The preparation of bottom grating structure amorphous state indium nitride film transistor
1. utilizing in the ITO gate electrodes that magnetron sputtering technique growth thickness is 100 nm, sputter procedure, Ar is used for guarantor
Gas is protected, flow is 14sccm, be prepared for ITO films using ITO target, wherein reaction pressure is 0.5 Pa, and radio-frequency power is
100W。
2. it is 1000mm in surface gate electrode growth length to utilize PECVD technique combination mask process, width is 260mm,
Thickness is 800 nm silica, as gate dielectric layer, is passed through the oxygen that flow is 40 sccm, and flow is 10 sccm silicon
Alkane；It is 35 Pa to control reaction chamber pressure；Adjustment radio-frequency power is 100 W；Underlayer temperature is room temperature.
3. it is 1000mm in gate dielectric layer superficial growth length to utilize PECVD technique combination mask process, width is 260mm
The p-type amorphous state indium nitride film that thickness is 30 nm is passed through the trimethyl indium that flow is 30 sccm as channel layer, and flow is
40 sccm ammonia, flow is used as p-type dopant for 10 sccm silane；Adjustment radio-frequency power is 150 W, underlayer temperature
200℃。
4. using IZO source electrode and drain electrode of the magnetron sputtering technique growth thickness for 200 nm, during electrode growth, use
Mask technique generates pattern, and length is 1000 mm, and width is 100 mm, and electrode spacing is 60mm；In sputter procedure, using Ar
For protective gas, flow is 14sccm, is prepared for IZO films using IZO targets, wherein reaction pressure is 0.5 Pa, radio frequency work(
Rate is 100W.
Claims (8)
1. the preparation method of a kind of amorphous state gallium nitride or indium nitride film transistor, it is characterised in that：Using plasma
Gas phase deposition technology is learned, reaction source is used as by the use of organic source, ammonia；By the use of hydrogen or nitrogen as organic source carrier gas source, utilize
Silane, trimethyl magnesium prepare n-type or p-type amorphous state gallium nitride or amorphous state indium nitride film as dopant；With n-type or p-type
Amorphous state gallium nitride film or using the amorphous state indium nitride film of n-type or p-type as thin film transistor channel layer, prepare top-gated
Configuration thin film transistor；
Or using plasma chemical vapour deposition technique, it is used as reaction source by the use of organic source, ammonia；Made using hydrogen or nitrogen
For organic source carrier gas source, by the use of silane, trimethyl magnesium as dopant, n-type or p-type amorphous state gallium nitride or amorphous state nitrogen are prepared
Change indium film；With the amorphous state gallium nitride film or brilliant using the amorphous state indium nitride film of n-type or p-type as film of n-type or p-type
Body pipe trench channel layer, prepares bottom grating structure thin film transistor (TFT)；
Described plasma chemical vapor deposition technique is prepared during amorphous state gallium nitride or amorphous state indium nitride film, its
Technological parameter is：Organic source and ammonia mass flow ratio are 1:2~1:1, radio-frequency power is 50~350W, and reaction pressure is 20
~200Pa；Underlayer temperature is room temperature to 350 DEG C；Described dopant is n-type dopant or p-type dopant；Wherein, dopant
It is 1%~20% with organic source mass flow mixed proportion；Wherein described n-type dopant, p-type dopant select front three respectively
Base magnesium and silane, described organic source are trimethyl gallium, triethyl-gallium or trimethyl indium.
2. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 1, its feature exists
In described amorphous state gallium nitride or indium nitride film transistor, using top gate structure, by substrate, barrier layer, channel layer, source
It is barrier layer above electrode, gate dielectric layer, gate electrode and drain electrode composition, substrate, barrier layer top is on channel layer, channel layer
Square both sides are respectively source-drain electrode, and middle channel layer top is gate dielectric layer, and gate dielectric layer top is gate electrode, and transistor passes through
Chemical vapor deposition and magnetron sputtering combination mask process complete the superposition growth of each functional layer, it is characterised in that：With n-type or p
The amorphous state gallium nitride film of type or the layer using the amorphous state indium nitride film of n-type or p-type as thin film transistor channel.
3. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 1, its feature exists
In, described amorphous state gallium nitride or indium nitride film transistor, using bottom grating structure, by substrate, gate electrode, gate dielectric layer,
It is gate dielectric layer, gate dielectric layer top above gate electrode, gate electrode to be above channel layer, source electrode and drain electrode, composition, substrate
For channel layer, channel layer top both sides are respectively source electrode and drain electrode, and transistor passes through chemical vapor deposition and magnetron sputtering
The superposition growth of each functional layer is completed with reference to mask process, it is characterised in that：With the amorphous state gallium nitride film of n-type or p-type or
The layer using the amorphous state indium nitride film of n-type or p-type as thin film transistor channel.
4. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 2 or claim 3, its feature
It is：The substrate is glass, pi flexiplast or monocrystalline silicon piece.
5. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 2, its feature exists
In：Described top-grate structure thin film transistor, using silica or silicon nitride film as barrier layer, thickness is 100~
2000nm。
6. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 2 or claim 3, its feature
It is：In described amorphous state gallium nitride or indium nitride film transistor, gate dielectric layer selection silica or silicon nitride, thickness
For 200~5000nm；Its silica preparation technology parameter is：Be passed through flow be 30~90sccm oxygen, flow be 5~
20sccm silane；It is 10~200Pa to control reaction chamber pressure；Adjustment radio-frequency power is 30~200W；Underlayer temperature is 20
~200 DEG C；Its silicon nitride preparation technology parameter is：The nitrogen that flow is 30~90sccm is passed through, flow is 5~20sccm silicon
Alkane；It is 10~200Pa to control reaction chamber pressure；Adjustment radio-frequency power is 30~200W；Underlayer temperature is 200~400 DEG C.
7. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 2 or claim 3, its feature
It is：The gate electrode, source electrode, drain electrode are from metal and the metal oxide materials of conduction, and thickness is 50~500nm；
Wherein, a length of 800~1200 μm of the source electrode of bottom grating structure transistor, drain electrode, a width of 100~150 μm, source electrode, electric leakage
Spacing is 50~100 μm, a length of 800~1200 μm, a width of 250~400 μm of gate electrode between pole；The source of top gate structure transistor
A length of 800~1200 μm of electrode, drain electrode, a width of 100~150 μm, spacing is 50~100 μm, grid between source electrode, drain electrode
A length of 800~1200 μm, a width of 50~90 μm of electrode.
8. a kind of preparation method of amorphous state gallium nitride or indium nitride film transistor as claimed in claim 2 or claim 3, its feature
It is：Channel layer thickness is 10~1000nm.
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