CN103778100A - 向量处理器的存储器互连网络体系结构 - Google Patents
向量处理器的存储器互连网络体系结构 Download PDFInfo
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- CN103778100A CN103778100A CN201310501553.0A CN201310501553A CN103778100A CN 103778100 A CN103778100 A CN 103778100A CN 201310501553 A CN201310501553 A CN 201310501553A CN 103778100 A CN103778100 A CN 103778100A
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- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
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Abstract
Description
Claims (20)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US201261717561P | 2012-10-23 | 2012-10-23 | |
US61/717,561 | 2012-10-23 | ||
US13/720,624 | 2012-12-19 | ||
US13/720,624 US9201828B2 (en) | 2012-10-23 | 2012-12-19 | Memory interconnect network architecture for vector processor |
Publications (2)
Publication Number | Publication Date |
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CN103778100A true CN103778100A (zh) | 2014-05-07 |
CN103778100B CN103778100B (zh) | 2017-01-11 |
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CN201310501553.0A Active CN103778100B (zh) | 2012-10-23 | 2013-10-23 | 向量处理器的存储器互连网络体系结构 |
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Country | Link |
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US (1) | US9201828B2 (zh) |
EP (1) | EP2725485A2 (zh) |
CN (1) | CN103778100B (zh) |
DE (1) | DE202013012281U1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107636640A (zh) * | 2016-01-30 | 2018-01-26 | 慧与发展有限责任合伙企业 | 具有求反指示符的点积引擎 |
CN109478252A (zh) * | 2016-05-07 | 2019-03-15 | 英特尔公司 | 用于神经网络硬件加速的多播网络和存储器转移优化 |
CN111124967A (zh) * | 2019-11-20 | 2020-05-08 | 安徽中骄智能科技有限公司 | 基于高通量计算平台的可局部强化互连的扩展系统 |
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US9342306B2 (en) | 2012-10-23 | 2016-05-17 | Analog Devices Global | Predicate counter |
US9092429B2 (en) | 2012-10-23 | 2015-07-28 | Analog Devices Global | DMA vector buffer |
US9201828B2 (en) | 2012-10-23 | 2015-12-01 | Analog Devices, Inc. | Memory interconnect network architecture for vector processor |
US9606803B2 (en) | 2013-07-15 | 2017-03-28 | Texas Instruments Incorporated | Highly integrated scalable, flexible DSP megamodule architecture |
US9928190B2 (en) * | 2015-06-15 | 2018-03-27 | International Business Machines Corporation | High bandwidth low latency data exchange between processing elements |
US10360163B2 (en) | 2016-10-27 | 2019-07-23 | Google Llc | Exploiting input data sparsity in neural network compute units |
US9959498B1 (en) | 2016-10-27 | 2018-05-01 | Google Llc | Neural network instruction set architecture |
US10175980B2 (en) | 2016-10-27 | 2019-01-08 | Google Llc | Neural network compute tile |
US10338919B2 (en) | 2017-05-08 | 2019-07-02 | Nvidia Corporation | Generalized acceleration of matrix multiply accumulate operations |
DE102018110607A1 (de) | 2017-05-08 | 2018-11-08 | Nvidia Corporation | Verallgemeinerte Beschleunigung von Matrix-Multiplikations-und-Akkumulations-Operationen |
US11157441B2 (en) * | 2017-07-24 | 2021-10-26 | Tesla, Inc. | Computational array microprocessor system using non-consecutive data formatting |
FR3083350B1 (fr) * | 2018-06-29 | 2021-01-01 | Vsora | Acces memoire de processeurs |
US11860782B2 (en) * | 2019-08-13 | 2024-01-02 | Neuroblade Ltd. | Compensating for DRAM activation penalties |
CN113094099A (zh) * | 2019-12-23 | 2021-07-09 | 超威半导体(上海)有限公司 | 矩阵数据广播架构 |
WO2021187027A1 (ja) * | 2020-03-18 | 2021-09-23 | 日本電気株式会社 | 情報処理装置及び情報処理方法 |
US20230004385A1 (en) * | 2021-06-30 | 2023-01-05 | Advanced Micro Devices, Inc. | Accelerated processing device and method of sharing data for machine learning |
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CN101052947A (zh) * | 2004-11-03 | 2007-10-10 | 皇家飞利浦电子股份有限公司 | 支持simd指令的可编程数据处理电路 |
US20110022754A1 (en) * | 2007-12-06 | 2011-01-27 | Technion Research & Development Foundation Ltd | Bus enhanced network on chip |
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DE68928980T2 (de) | 1989-11-17 | 1999-08-19 | Texas Instruments Inc | Multiprozessor mit Koordinatenschalter zwischen Prozessoren und Speichern |
WO1991017507A1 (en) * | 1990-05-07 | 1991-11-14 | Mitsubishi Denki Kabushiki Kaisha | Parallel data processing system |
CA2129882A1 (en) | 1993-08-12 | 1995-02-13 | Soheil Shams | Dynamically reconfigurable interprocessor communication network for simd multiprocessors and apparatus implementing same |
WO1995009399A1 (fr) | 1993-09-27 | 1995-04-06 | Ntt Mobile Communications Network Inc. | Multiprocesseur |
US5903771A (en) | 1996-01-16 | 1999-05-11 | Alacron, Inc. | Scalable multi-processor architecture for SIMD and MIMD operations |
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US9201828B2 (en) | 2012-10-23 | 2015-12-01 | Analog Devices, Inc. | Memory interconnect network architecture for vector processor |
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2013
- 2013-10-16 DE DE202013012281.1U patent/DE202013012281U1/de not_active Expired - Lifetime
- 2013-10-16 EP EP13188947.9A patent/EP2725485A2/en not_active Withdrawn
- 2013-10-23 CN CN201310501553.0A patent/CN103778100B/zh active Active
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CN101052947A (zh) * | 2004-11-03 | 2007-10-10 | 皇家飞利浦电子股份有限公司 | 支持simd指令的可编程数据处理电路 |
US20110022754A1 (en) * | 2007-12-06 | 2011-01-27 | Technion Research & Development Foundation Ltd | Bus enhanced network on chip |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107636640A (zh) * | 2016-01-30 | 2018-01-26 | 慧与发展有限责任合伙企业 | 具有求反指示符的点积引擎 |
CN107636640B (zh) * | 2016-01-30 | 2021-11-23 | 慧与发展有限责任合伙企业 | 点积引擎、忆阻器点积引擎以及用于计算点积的方法 |
CN109478252A (zh) * | 2016-05-07 | 2019-03-15 | 英特尔公司 | 用于神经网络硬件加速的多播网络和存储器转移优化 |
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CN109478252B (zh) * | 2016-05-07 | 2023-07-25 | 英特尔公司 | 用于神经网络硬件加速的多播网络和存储器转移优化 |
CN111124967A (zh) * | 2019-11-20 | 2020-05-08 | 安徽中骄智能科技有限公司 | 基于高通量计算平台的可局部强化互连的扩展系统 |
Also Published As
Publication number | Publication date |
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US20140115224A1 (en) | 2014-04-24 |
DE202013012281U1 (de) | 2016-01-18 |
EP2725485A2 (en) | 2014-04-30 |
US9201828B2 (en) | 2015-12-01 |
CN103778100B (zh) | 2017-01-11 |
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