CN103762184B - 芯片封装和用于制造芯片封装的方法 - Google Patents

芯片封装和用于制造芯片封装的方法 Download PDF

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CN103762184B
CN103762184B CN201310330942.1A CN201310330942A CN103762184B CN 103762184 B CN103762184 B CN 103762184B CN 201310330942 A CN201310330942 A CN 201310330942A CN 103762184 B CN103762184 B CN 103762184B
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conductive
electrically insulating
insulating material
layer
conductive structure
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CN103762184A (zh
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J.费尔斯特
W.哈特纳
J.希尔特赖特
U.瓦赫特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及芯片封装和用于制造芯片封装的方法。本发明提供了一种用于制造芯片封装的方法。该方法包括：在芯片侧上形成电绝缘材料；选择性地移除所述电绝缘材料的至少一部分，由此在所述电绝缘材料中形成沟槽；将导电材料沉积在所述沟槽中，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘；在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接；以及在所述导电结构上沉积接合结构。

Description

芯片封装和用于制造芯片封装的方法
技术领域
各种实施例总体上涉及芯片封装和用于制造芯片封装的方法。
背景技术
在芯片封装技术中，例如在制造芯片102的封装中，可以将流电沉积的铜用于铜线（例如铜导线104、或铜焊盘106）的处理，如图1A中示出的那样。如在图1B中进一步示出的那样，可以沉积通常可以为Cu的薄种子层108。另外，可以用作例如粘附力促进剂、用作例如扩散势垒层、用作金属离子势垒的粘附层112可以被布置在薄Cu种子层108下面。用于粘附层和/或势垒层112的典型材料可以是TiW、TiN、TaN。后续的光刻工艺可以被实施，该光刻工艺可以包括经过图案化的抗蚀剂114的形成，如图1C中示出的那样。如在图1D中示出的那样，通过光刻工艺，诸如通过抗蚀剂114以及下面沉积的金属种子层108的使用，可以沉积凸块下金属化（UBM, under-bump metallization）铜 。UBM铜可以包括可被流电沉积在掩模层级上的铜材料的第一部分116，以及，可以在第一部分116上以及在介电层上形成铜材料118的另一部分。如图1E中所示的那样，抗蚀剂114可以被移除。另外，如图1F中所示的那样，在形成UBM铜118、116之后，该UBM铜118、116可以被用于连接到金属球122，例如焊料球，其可以被用作芯片部件（例如芯片102）和印刷电路板（PCB）之间的电互连。UBM铜118、116不仅可以增加总体提供的铜厚度，因为铜可能被消耗，例如通过经由金属间相形成而进行铜消耗，例如通过后续的焊接工艺，例如通过温度暴露。此外，UBM铜118、116还可以改变球122到芯片102之间的连接的结构构造。具有UBM铜118、116的机械构造的这些改变可能导致较高的循环稳定性。例如，对于显著多于1000个循环，板上温度循环（TCOB）可以是稳定的，从-40℃到125℃。
与已经被用于制造铜线104（例如焊盘106）的那些工艺步骤相类似的工艺步骤可以被用于生产UBM铜118，包括铜材料116。在沉积铜焊盘106和焊接停止部124（例如电介质2、粘附层112和种子层108）之后，UBM铜118、116通常可以被形成。此外，在光刻之后，可以实施用于形成UBM铜118、116的UBM铜镀。
发明内容
各种实施例提供了一种用于制造芯片封装的方法，该方法包括：在芯片侧上形成电绝缘材料；选择性地移除所述电绝缘材料的至少一部分，由此在所述电绝缘材料中形成沟槽；将导电材料沉积在所述沟槽中，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘；在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接；以及在所述导电结构上沉积接合结构。
附图说明
在附图中，遍及不同视图，相似的附图标记通常指代相同部分。附图不必按照比例来绘制，而是通常将重点放在图示本发明的原理上。在下面的描述中，参考下面的附图来描述本发明的各种实施例，在附图中：
图1A到1F示出用于制造芯片封装的方法；
图2A示出电介质材料上的UBM翼（wing）的分层；
图2B示出重分布层RDL铜上的UBM翼的分层；
图2C和2D示出UBM铜的整个分层；
图3A示出根据一个实施例的具有和不具有UBM的板上温度循环的Weibull曲线图；
图3B示出不具有UBM的板上温度循环之后的铜撕裂；
图4示出根据一个实施例的用于制造芯片封装的方法；
图5A到5G示出根据一个实施例的用于制造芯片封装的方法；
图6示出根据一个实施例的用于制造芯片封装的方法；
图7A到7D示出根据一个实施例的用于制造芯片封装的方法；
图8示出根据一个实施例的用于制造芯片封装的方法。
具体实施方式
下面的详细描述参考通过图示的方式示出可以在其中施行本发明的实施例和具体细节的附图。
词“示例性”在本文中用来意指“用作示例、实例或图示”。本文中被描述为“示例性”的任何实施例或设计不必被理解为与其他实施例或设计相比优选或有利。
在本文中用于描述“在”侧或表面“之上”形成特征（例如层）的词“在……之上”可以被用来意指该特征（例如层）可以“直接”形成“在”所暗指的侧或表面“上”，例如与其直接接触。在本文中用于描述“在”侧或表面“之上”形成特征（例如层）的词“在……之上”可以被用来意指该特征（例如层）可以“间接”形成“在”所暗指的侧或表面“上”，其中在所暗指的侧或表面与所形成的层之间布置一个或多个附加层。
如在图1B到1F中示出的那样，通过使用粘附层112（例如TiW粘附层），可以存在朝向在介电层124（例如电介质2）上的更好粘附的趋势。然而，如已经发现的那样，UBM铜118和介电层124（例如电介质2）之间的粘附在温度循环之后可能不再存在，或者可能不再如之前那么好地被粘附。如图2A中示出的那样，发生UBM铜118从介电层124（例如电介质2）的分层（沿由箭头指示的方向），即UBM翼升起。
此外，可以观察到，在温度循环之后，在UBM铜118和底部焊盘或重分布层（RDL）铜104之间存在非常小的粘附。UBM铜118抬起离开（heave off），并且可以发生RDL铜104上的UBM铜118的分层，如图2B、2C和2D所示。图2C和2D特别示出UBM铜118的整个分层。换言之，TiW界面层112可以导致UBM铜118和RDL铜104之间的较低粘附（例如较差的粘附）。
各种实施例提供了一种构造，其中可以避免诸如UBM翼升起之类的现象，并且此外，其可以改进UBM铜118和RDL Cu 104之间的粘附。根据各种其他实施例，UBM翼升起可以被用来创建柔性的UBM结构118。
通过省略UBM（例如诸如UBM铜118），UBM翼升起问题以及UBM与RDL之间（例如UBMCu与RDl Cu之间）的粘附问题都不会发生。然而，如在图3A中的具有UBM和不具有UBM的TCOB的Weibull曲线图中示出的那样，UBM的省略进一步与较低循环强度TCOB相关联。如累积故障率326相对于循环的数目328的曲线图中示出的那样，与对于具有UBM的封装334、336相比，对于具有没有UBM（No UBM）的封装332，在较低的循环数目处出现较高的故障率。此外，如在图3B中示出的那样，不具有UBM的芯片封装可能具有在TCOB之后遭受铜撕裂338的较高风险。
各种实施例提供了一种用于制造芯片封装的方法和一种芯片封装，其中通过在UBM工艺期间省略势垒层（例如TiW），可能在UBM和RDL之间（例如在UBM Cu和RDL Cu之间）不存在界面层。
各种实施例提供了一种用于制造芯片封装的方法和一种芯片封装，其中在没有界面层的情况下两种材料（即UBM和RDL，例如UBM Cu和RDL Cu）的均质结构是可能的。因此，相同材料的较高可能的粘附可以是可能的。
图4示出根据一个实施例的用于制造芯片封装的方法400。
方法400可以包括：
在芯片侧上形成电绝缘材料（在410中）；
选择性地移除所述电绝缘材料的至少一部分，由此在所述电绝缘材料中形成沟槽（在420中）；
将导电材料沉积在所述沟槽中，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘（在430中）；
在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接（在440中）；以及
在所述导电结构上沉积接合结构（在450中）。
图5A到5F示出根据一个实施例的用于制造芯片封装的方法500。
方法500可以包括在第一芯片侧544上形成第一电绝缘层542。
芯片502可以包括第一芯片侧544和第二芯片侧546。
第一芯片侧544可以包括芯片顶侧，其还可以被称为芯片的“第一侧”、“正侧”或“上侧”。在下文中，术语“顶侧”、“第一侧”、“正侧”或“上侧”可以被可互换地使用。第二芯片侧546可以包括芯片底侧，其还可以被称为芯片的“第二侧”或“背侧”。在下文中，术语“第二侧”、“背侧”或“底侧”可以被可互换地使用。可以理解，通常，至少一个接触焊盘506可以被形成在第一芯片侧544上，例如直接被形成在第一芯片侧上的芯片表面上。
芯片502可以至少部分被模具复合物548包围。例如，模具复合物548可以被形成在芯片502的第二芯片侧546和一个或多个侧壁552上。一般而言，第一芯片侧544可以基本上脱离模具复合物，因为它可以是芯片502的承载至少一个接触焊盘506的侧。一般地，在前端处理期间，薄钝化材料（未示出）和至少一个接触焊盘506可能已经被形成在第一芯片侧544上。薄钝化材料可以包括例如聚酰亚胺、或例如氮化硅、或例如二氧化硅，其可以被布置在所述至少一个接触焊盘506之间。
至少一个接触焊盘506可以包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、铝、银、锡、金、钯、锌、镍、铁、钛、钒。至少一个接触焊盘506可以包括一个或多个贵金属。
工艺510示出第一电绝缘层542可以被形成在第一芯片侧544上。第一电绝缘层542可以被称为电介质1。第一电绝缘层542可以被形成在第一芯片侧544以及模具复合物548的侧554上。侧554可以面向与第一芯片侧544所面向的方向相同的方向，并且侧554可以基本上与544齐平。这可以是由于与嵌入式晶片级封装有关的工艺，其中多个芯片可以被布置在共同的临时衬底上，例如其中，第一芯片管芯向下面朝共同的衬底上，并共同被铸模有模具复合物548，模具复合物548可以将多个芯片保持在一起。保持多个芯片的模具复合物548的该布置可以被称为重组晶片。因此，可以理解，芯片502可以是由模具复合物548类似地保持的多个芯片中的一个芯片。
第一电绝缘层542可以基本上覆盖模具复合物548的侧554和第一芯片侧544。第一电绝缘层542可以包括电介质材料。第一电绝缘层542可以包括来自下面的材料组的至少一种材料，该材料组由下述各项构成：光敏电介质（例如WPR）；聚酰亚胺（例如光敏型聚酰亚胺（Durimide）7320或低温固化光敏型聚酰亚胺7320）；聚合物（例如苯并环丁烯（BCB））；环氧树脂。第一电绝缘层542可以具有范围从约1μm到约50μm（例如约1μm到约20μm，例如约1μm到约10μm）的厚度。第一电绝缘层542可以具有约6μm的厚度。
随后，可以在第一电绝缘层542中形成沟槽或孔。沟槽556的侧壁561可以由第一电绝缘层542的侧限定。沟槽556可以被形成在至少一个接触焊盘506上，以使得至少一个接触焊盘506可以被从第一电绝缘层542释放；换言之，以使得至少一个接触焊盘506可以被暴露。
第一中间导电层558可以被沉积（例如直接沉积）在第一电绝缘层542上；被沉积（例如直接沉积）在沟槽556的侧壁561上；以及被沉积（例如直接沉积）在至少一个接触焊盘506上。第一中间导电层558可以包括粘附层和/或是粘附层，例如类似于粘附层112，并可以用作例如粘附力促进剂，用作例如扩散势垒层和/或金属离子势垒。第一中间导电层558可以包括过渡金属的氮化物、硼化物或碳化物中的至少一个。第一中间导电层558可以包括来自下面的材料组的至少一种材料，该组由下述各项构成：钛（Ti）、钛-钨（TiW）、氮化钛（TiN）、氮化钽（TaN）。第一中间导电层558可以具有范围从约15nm到约500nm（例如从约30nm到约100nm，例如约45nm到约55nm）的厚度。第一中间导电层558可以具有约50nm的厚度。第一中间导电层558的至少一部分可以与形成在第一芯片侧544上的至少一个接触焊盘506直接物理和电接触。
随后，第一导电层504可以被形成在第一中间导电层542上。第一导电层504可以经由第一中间导电层558电连接到至少一个接触焊盘506。第一导电层504可以被称为重分布层（RDL），例如RDL Cu。第一导电层504可以包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、铝、银、锡、金、钯、锌、镍、铁。第一导电层504可以具有范围从约1μm到约50μm（例如约1μm到约20μm，例如约1μm到约10μm）的厚度。第一导电层504可以具有约6μm的厚度。第一导电层504可以被形成（例如直接形成）在第一中间导电层542上，并进一步被形成在沟槽556中。例如，第一导电层504可以基本上填充沟槽556并因此与至少一个接触焊盘506电连接。第一导电层504可以被沉积并可选地被进一步处理，以使得第一导电层504可以被基本上齐平地形成在第一中间导电层558上。
随后，电绝缘材料524（例如电介质2）可以进一步被形成在第一芯片侧544上。例如，电绝缘材料524可以被形成（例如直接形成）在第一导电层504上。电绝缘材料524可以被形成在形成于第一芯片侧544上的至少一个接触焊盘506上。电绝缘材料524可以被形成在第一芯片侧544上，其中电绝缘材料524可以包括形成在第一芯片侧544上的最上面的电绝缘层和/或可以是所述最上面的电绝缘层。电绝缘材料524可以被形成在一个或多个导电层（例如558、例如504）上，所述一个或多个导电层电连接到形成在第一芯片侧544上的至少一个接触焊盘506。
电绝缘材料524可以类似于第一电绝缘层542。电绝缘材料524可以包括电介质材料。电绝缘材料524可以包括来自下面的材料组的至少一种材料，该材料组由下述各项构成：光敏电介质（例如WPR）；聚酰亚胺（例如光敏型聚酰亚胺7320或低温固化光敏型聚酰亚胺7320）；聚合物（例如苯并环丁烯（BCB））；环氧树脂。电绝缘材料524可以具有范围从约1μm到约50μm（例如约1μm到约20μm，例如约1μm到约10μm）的厚度。电绝缘材料524可以具有约6μm的厚度。
随后，电绝缘材料524的至少一部分可以被选择性地移除，由此在电绝缘材料524中形成沟槽562。一个或多个导电层（例如504）的一个或多个部分可以被从电绝缘材料524释放。例如，第一导电层504的部分564可能因电绝缘材料524的一部分的选择性移除而被暴露。该电绝缘材料524的至少一部分可以通过来自下面的方法组的至少一种方法而被选择性地移除，该方法组由下述各项构成：钻孔、激光钻孔、蚀刻、离子铣削、显影。显影可以被用来移除电绝缘材料524的至少一部分，其中电绝缘材料包括光敏电介质材料。
如图5B中所示的那样，在工艺520中，可选种子层566可以被形成在电绝缘材料524上。种子层566可以另外被连续形成在第一导电层504的暴露部分564以及沟槽562的一个或多个侧壁568上。种子层566可以被用作导电材料的生长种子层，所述导电材料可以经由种子层566电接触到第一导电层504。种子层566可以是导电的，并可以由与第一导电层504相同的材料形成。这可以允许将种子层566用作具有与第一导电层504的材料相同的材料的种子生长层的任何后续材料沉积。种子层566可以特别被用作用于流电沉积导电材料516和导电结构518的种子层。种子层566可以具有范围从约15nm到约500nm（例如从约30nm到约100nm，例如约45nm到约55nm）的厚度。种子层566可以具有约50nm的厚度。
为了在芯片封装的所选区域中选择性地沉积导电材料，可以使用光刻来限定这些选择性区域。
如图5C中所示的那样，在工艺530中，抗蚀剂514可以被沉积在电绝缘材料524上并被选择性地图案化。在没有种子层566的情况下，使得第一导电层504的部分564可以被暴露和/或电绝缘材料524的至少一部分（例如电绝缘材料524的顶表面的一部分574和电绝缘材料524的侧壁576）也可以可选地被从抗蚀剂514释放。在种子层566被用作生长层的情况下，种子层566的被形成在部分564上的部分和/或种子层566的被形成在电绝缘材料524的顶表面的部分574以及电绝缘材料524的侧壁576上的部分可以被从抗蚀剂514释放。
图7、8示出各种其他实施例，其中顶表面574未被从抗蚀剂514释放。
如图5D中所示的那样，在工艺540中，将选择性地图案化的抗蚀剂514用作沉积掩模，导电材料516可以被沉积在沟槽572中。例如，沟槽572可以至少部分填充有导电材料516。导电材料516可以电连接到形成在芯片侧上的至少一个接触焊盘。此外，导电材料516可以被沉积以使得导电材料进一步被形成在电绝缘材料524的侧壁576和表面574上。沟槽572中的以及电绝缘材料524的侧壁576和表面574上的导电材料516可以被称为导电结构518。导电材料516可以被沉积在从电绝缘材料524选择性地释放的一个或多个导电层（例如第一导电层504）的一个或多个部分564上。
导电结构518可以被形成在电绝缘材料524上，其中导电结构518的至少一部分可以与导电材料516直接物理和电连接。
可以理解，包括导电材料516的导电结构518可以可选地从种子层566生长。换言之，包括可以可选地从种子层556（例如从流电沉积）生长的导电材料516的导电结构518可以与导电材料504直接物理和电连接。即使流电沉积未被选择为沉积方法，包括导电材料516的所沉积的导电结构518也可以被形成以使得它可以与导电材料504直接物理和电连接。
包括导电材料516的导电结构518可以包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、镍、镍掺杂的铜、钛、碳化钛、钨、碳化钨、氧化铪、氧化铱。导电结构518通常可以包括导电金属、或导电碳化物、或导电氧化物。其他材料也可以被用于导电结构518，例如UBM，然而，可以在复杂度和附加成本方面考虑它们，该附加成本可能由例如与通过化学气相沉积（CVD）或原子层沉积（ALD）的势垒沉积相关联的成本引起。
导电结构518可以包括形成在电绝缘材料524上的凸块下金属化（UBM）结构，其中导电结构518的至少一部分可以与导电材料504直接物理和电连接。包括导电材料516的导电结构518可以包括相同的材料。此外，包括导电材料516的导电结构518可以包括与导电材料504相同的材料。
如图5E中所示的那样，在工艺550中，可以移除经过图案化的抗蚀剂514。此外，可以移除抗蚀剂514下面的种子层566的其他部分。
如图5F中所示的那样，在工艺560中，可以将接合结构578沉积在导电结构518上。接合结构578可以包括焊接结构。接合结构578可以包括来自下面的接合结构组的至少一个接合结构，该接合结构组由下述各项构成：焊料球、焊料凸块。
导电结构518可以包括与导电材料516相同的材料，并且接合结构578可以与导电结构518直接物理和电接触。导电结构518可以包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍（NiP）、磷化镍-钯-金（NiP-Pd-Au）。
接合结构578可以包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：银、锌、锡、铟、铜、金、钯、铅。
根据方法500的各种实施例，可以制造芯片封装（诸如芯片封装570）。芯片封装570可以包括：形成在芯片侧544上的电绝缘材料524；形成在电绝缘材料524中的沟槽562；沉积在沟槽562中的导电材料516，其中导电材料516可以电连接到形成在芯片侧544上的至少一个接触焊盘506；形成在电绝缘材料524上的导电结构518，其中导电结构518的至少一部分可以与导电材料516直接物理和电连接；以及形成在导电结构518上的接合结构578。
可以理解，导电结构518和第一导电层504之间的物理粘附可以比导电结构518和电绝缘材料524之间的粘附更好。
在传统的芯片封装的情况下，通常不容忍或期望因UBM铜从介电层的分层以及UBM从RDL铜的分层而引起的UBM翼升起。图5G示出根据各种实施例的芯片封装的一部分，其中，归因于导电结构518和第一导电层504之间的极好粘附，导电结构518的至少另一部分582可以从电绝缘材料524分离，例如类似于UBM翼升起。另一部分582可以包括和/或可以是导电结构518的柔性部分，其可以改进因导电结构518的柔性而引起的芯片封装的热可靠性。因此，导电结构518可以被理解成包括基本上可以为刚性的部分（例如导电材料516）以及可比基本上刚性的部分更柔性的另一部分582。例如，导电结构518可以包括：导电材料516，其与第一导电层504直接物理和电连接；以及另一部分582，其被布置在电绝缘材料524上，所述另一部分582可以比粘附到电绝缘材料524更好地粘附到导电材料516。另一部分582可以被布置在接合结构578和导电材料516之间。此外，因为接合结构578可以经由另一部分582物理和电连接到导电材料516，所以在不影响导电材料516和第一导电层504之间的极好粘附的情况下，可以因而实现另一部分582和接合结构578的横向移动。
通过省略通过UBM列队的TiW势垒层并且使用无电镀工艺，可以产生新的可能性和变型。
图6示出根据一个实施例的芯片封装610。可以根据方法500来制造芯片封装610；然而，该芯片封装610可以进一步包括下面的工艺：例如在沉积接合结构578之前，在导电结构518上形成层684，并且随后，在层684上形成接合结构578。层684可以包括来自下面的材料组的至少一种材料，该组由下述内容构成：磷化镍。层684可以具有范围从约2μm到约20μm（例如从约2μm到约50μm，例如从约4μm到约6μm）的厚度。层684可以具有约5μm的厚度。层684可以通过无电镀镀层来沉积。根据其他实施例，层684可以通过来自下面的沉积方法组的至少一种沉积方法来沉积，该沉积方法组由下述各项构成：电化学镀、无电镀沉积、溅射工艺、化学气相沉积、热蒸发。
图7A到7C示出根据一个实施例的用于制造芯片封装的方法700。方法700可以包括已经关于方法500描述的工艺中的一个或多个。然而，在方法700中，导电结构718（类似于导电结构518）可以通过无电镀方法来沉积。因此，方法700可以包括已经关于工艺510描述的所有工艺和特征或其中的一个或多个。然而，对于无电镀导电结构718的沉积来说，种子层566可能不是需要的，并且可以被省略。
如图7B中所示的那样，在工艺720中，导电结构718可以被无电镀地沉积在第一导电层504的部分564上，例如与部分564直接物理和电连接。导电结构718的一部分（例如导电材料716（其可以与导电材料516类似））可以被形成在沟槽562中，并与部分564直接物理和电连接。导电结构718可以比沟槽562的高度更厚，并可以在沟槽562之外形成凸起。归因于没有种子层566的无电镀沉积，导电结构518的形成在电绝缘材料524的顶表面的部分574上的伸出部分可以不存在于导电结构718中。此外，通过无电镀工艺，直接在焊盘（例如铜焊盘）和电绝缘材料524（例如电介质2）的处理之后，可以沉积Cu层，例如导电材料716，以及最终，导电结构718。因此，工艺序列可以被进一步简化，以使得为了制造UBM金属化，光刻可能不再是必需的。
铜的无电镀沉积可以根据下面的工艺步骤来实施：清洗、微蚀刻、激活、铜沉积、冲洗和干燥。
无电镀溶液可以包括：金属离子的源、还原剂（例如甲醛）、用于将金属离子保持在溶液中的配位剂、pH缓冲剂、以及可选地，其他化学品。
无电镀沉积温度可以在从25℃到约90℃之间的范围内变动。
无电镀沉积时间可以在从约1分钟到约60分钟的范围内变动。
过滤可以被实施以便移除较大的颗粒。
如图7C中所示的那样，在可类似于工艺560的工艺730中，可以在导电结构718上沉积接合结构578。
如在图7D中的另一实施例中所示的那样，在工艺740中，可以在导电结构718上形成层684，例如在沉积接合结构578之前。换言之，例如，在导电结构718（例如，其可以包括UBM铜）的无电镀形成之后，跟随的可能是硬无电镀层684（例如NiMo层）。随后，可以在层684上形成接合结构578。层684可以包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍（NiP）、磷化镍-钯-金（NiP-Pd-Au）。
通过如关于图6和图7D中的实施例描述的层684（例如NiMo），可以对抗机械力（例如温度循环）产生导电结构518、718（例如铜结构）的进一步稳定。
图8示出根据一个实施例的用于制造芯片封装的方法800。方法800可以包括已经关于方法500、600、700描述的工艺中的一个或多个。
特别地，如图8中所示，导电结构818可以通过无电镀沉积来沉积并可以包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍（NiP）、磷化镍-钯-金（NiP-Pd-Au）。导电结构818与导电结构518和导电结构718的不同之处可以在于：导电结构818可以基本上被形成在沟槽562内。也就是说，导电结构818以及电绝缘材料524的顶表面（例如顶表面的一部分574）可以基本上齐平。导电结构818可以包括经过沉积的稳定无电镀层，例如类似于层684的层。换言之，UBM铜结构可以被完全省略。
尽管到目前为止已经根据各种实施例示出导电结构518或718或818可以被形成在重分布层RDL上（例如被形成在第一导电层504上），但是可以理解：根据其他实施例，例如其中未使用或沉积重分布层，导电结构518或718或818可以被形成在接触焊盘506上。例如，导电结构518或718或818可以与接触焊盘506直接物理和电连接。例如，导电结构518或718或818可以被形成在沟槽556中且在第一电绝缘层542（例如电介质1）上，其中第一电绝缘层542（例如电介质1）可以被直接形成在第一芯片侧544上，并且还可以是被形成在第一芯片侧544上的最上面的电绝缘层。
可以理解，根据上文描述的各种实施例而制造的芯片封装可以包括晶片级封装（WLP），其可以包括根据扇入和/或扇出技术的封装。
各种实施例提供了一种用于制造芯片封装的方法，该方法包括：在芯片侧上形成电绝缘材料；选择性地移除所述电绝缘材料的至少一部分，由此在所述电绝缘材料中形成沟槽；将导电材料沉积在所述沟槽中，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘；在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接；以及在所述导电结构上沉积接合结构。
根据一个实施例，在芯片侧上形成电绝缘材料包括在芯片侧上形成介电层。
根据一个实施例，在芯片侧上形成电绝缘材料包括在形成于所述芯片侧上的至少一个接触焊盘上形成电绝缘材料。
根据一个实施例，在芯片侧上形成电绝缘材料包括形成包括来自下面的材料组的至少一种材料的电绝缘材料，该材料组由下述各项构成：光敏电介质、聚酰亚胺、聚合物、苯并环丁烯（BCB）、环氧树脂。
根据一个实施例，在芯片侧上形成电绝缘材料包括直接在所述芯片侧上形成电绝缘材料。
根据一个实施例，在芯片侧上形成电绝缘材料包括在所述芯片侧上形成电绝缘材料，其中所述电绝缘材料包括形成在所述芯片侧上的最上面的电绝缘层。
根据一个实施例，在芯片侧上形成电绝缘材料包括在形成于所述芯片侧上的第一导电层上形成电绝缘材料；其中所述第一导电层被形成在第一中间导电层上，其中所述第一中间导电层被形成在第一电绝缘层上；其中所述第一中间导电层的至少一部分与形成在所述芯片侧上的至少一个接触焊盘直接物理和电接触；并且其中所述第一导电层经由所述第一中间导电层电连接到所述至少一个接触焊盘。
根据一个实施例，所述第一导电层包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、铝、银、锡、金、钯、锌、镍、铁。
根据一个实施例，所述第一中间导电层可以包括过渡金属的氮化物、硼化物或碳化物中的至少一个。
根据一个实施例，在芯片侧上形成电绝缘材料包括在一个或多个导电层上形成电绝缘材料，所述一个或多个导电层电连接到形成于所述芯片侧上的至少一个接触焊盘。
根据一个实施例，选择性地移除所述电绝缘材料的至少一部分由此在所述电绝缘材料中形成沟槽还包括从所述电绝缘材料选择性地释放所述一个或多个导电层的一个或多个部分。
根据一个实施例，选择性地移除所述电绝缘材料的至少一部分包括通过来自下面的方法组的至少一种方法来选择性地移除所述电绝缘材料的至少一部分，所述方法组由下述各项构成：钻孔、激光钻孔、蚀刻、离子铣削、显影。
根据一个实施例，将导电材料沉积在所述沟槽中、其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘包括在从所述电绝缘材料选择性地释放的一个或多个导电层的一个或多个部分上沉积导电材料。
根据一个实施例，将导电材料沉积在所述沟槽中、其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘包括利用导电材料来至少部分地填充所述沟槽。
根据一个实施例，所述导电材料包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、镍、镍掺杂的铜、钛、碳化钛、钨、碳化钨、氧化铪、氧化铱。
根据一个实施例，在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接包括在所述电绝缘材料上形成包括凸块下金属化结构的导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接。
根据一个实施例，在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接包括在所述电绝缘材料上形成包括与所述导电材料相同的材料的导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接。
根据一个实施例，在所述导电结构上沉积接合结构包括在所述导电结构上沉积来自下面的接合结构组的至少一种接合结构，所述接合结构组由下述各项构成：焊料球、焊料凸块。
根据一个实施例，所述导电结构包括与所述导电材料相同的材料，并且其中所述接合结构与所述导电结构直接物理和电接触。
根据一个实施例，所述接合结构与所述导电结构直接物理和电接触，并且其中所述导电结构包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍（NiP）、磷化镍-钯-金（NiP-Pd-Au）。
根据一个实施例，所述接合结构包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：银、锌、锡、铟、铜、金、钯、铅。
根据一个实施例，在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接还包括形成导电结构，其中所述导电结构与所述第一导电层之间的物理粘附比所述导电结构与所述电绝缘材料之间的粘附更好。
根据一个实施例，在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接还包括形成导电结构，其中所述导电结构的至少另一部分从所述电绝缘材料分离。
根据一个实施例，所述方法还包括：在所述导电结构上形成层，以及随后在所述层上形成接合结构。
根据一个实施例，所述层包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍（NiP）、磷化镍-钯-金（NiP-Pd-Au）。
各种实施例提供了一种芯片封装，其包括：形成在芯片侧上的电绝缘材料；形成在所述电绝缘材料中的沟槽，沉积在所述沟槽中的导电材料，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘；形成在所述电绝缘材料上的导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接；以及形成在所述导电结构上的接合结构。
尽管已经参考特定实施例特别示出和描述了本发明，但是本领域技术人员应该理解，在不偏离如所附权利要求限定的本发明的精神和范围的情况下，可以在本发明中做出形式和细节上的各种改变。因此，本发明的范围由所附权利要求来指示，并且因此意图包括落入权利要求的等同物的含义和范围内的所有改变。

Claims (26)

1.一种用于制造芯片封装的方法，该方法包括：
在芯片侧上形成电绝缘材料；
选择性地移除所述电绝缘材料的至少一部分，由此在所述电绝缘材料中形成沟槽；
将导电材料沉积在所述沟槽中，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘；
在所述电绝缘材料上形成导电结构，其中所述导电结构包括第一导电层和凸块下金属化结构的均质结构，并且其中所述导电结构的至少一部分与所述导电材料直接物理和电连接；以及
在所述导电结构上沉积接合结构。
2.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：在芯片侧上形成介电层。
3.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：在形成于所述芯片侧上的至少一个接触焊盘上形成电绝缘材料。
4.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：形成包括来自下面的材料组的至少一种材料的电绝缘材料，该材料组由下述各项构成：光敏电介质、聚酰亚胺、聚合物、苯并环丁烯BCB、环氧树脂。
5.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：直接在所述芯片侧上形成电绝缘材料。
6.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：在所述芯片侧上形成电绝缘材料，其中所述电绝缘材料包括形成在所述芯片侧上的最上面的电绝缘层。
7.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：在形成于所述芯片侧上的第一导电层上形成电绝缘材料；
其中所述第一导电层被形成在第一中间导电层上，其中所述第一中间导电层被形成在第一电绝缘层上；
其中所述第一中间导电层的至少一部分与形成在所述芯片侧上的至少一个接触焊盘直接物理和电接触；并且其中
所述第一导电层经由所述第一中间导电层电连接到所述至少一个接触焊盘。
8.根据权利要求7所述的方法，其中所述第一导电层包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、铝、银、锡、金、钯、锌、镍、铁。
9.根据权利要求7所述的方法，其中所述第一中间导电层包括过渡金属的氮化物、硼化物或碳化物中的至少一个。
10.根据权利要求1所述的方法，其中在芯片侧上形成电绝缘材料包括：在一个或多个导电层上形成电绝缘材料，所述一个或多个导电层电连接到形成于所述芯片侧上的至少一个接触焊盘。
11.根据权利要求10所述的方法，其中选择性地移除所述电绝缘材料的至少一部分由此在所述电绝缘材料中形成沟槽还包括：从所述电绝缘材料选择性地释放所述一个或多个导电层的一个或多个部分。
12.根据权利要求1所述的方法，其中选择性地移除所述电绝缘材料的至少一部分包括：通过来自下面的方法组的至少一种方法来选择性地移除所述电绝缘材料的至少一部分，所述方法组由下述各项构成：钻孔、激光钻孔、蚀刻、离子铣削、显影。
13.根据权利要求11所述的方法，其中将导电材料沉积在所述沟槽中、其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘包括：
在从所述电绝缘材料选择性地释放的一个或多个导电层的一个或多个部分上沉积导电材料。
14.根据权利要求1所述的方法，其中将导电材料沉积在所述沟槽中、其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘包括：
利用导电材料来至少部分地填充所述沟槽。
15.根据权利要求1所述的方法，其中所述导电材料包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：铜、镍、镍掺杂的铜、钛、碳化钛、钨、碳化钨、氧化铪、氧化铱。
16.根据权利要求1所述的方法，其中在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接包括：
在所述电绝缘材料上形成包括凸块下金属化结构的导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接。
17.根据权利要求1所述的方法，其中在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接包括：
在所述电绝缘材料上形成包括与所述导电材料相同的材料的导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接。
18.根据权利要求1所述的方法，其中在所述导电结构上沉积接合结构包括：在所述导电结构上沉积来自下面的接合结构组的至少一种接合结构，所述接合结构组由下述各项构成：焊料球、焊料凸块。
19.根据权利要求1所述的方法，其中所述导电结构包括与所述导电材料相同的材料，并且其中所述接合结构与所述导电结构直接物理和电接触。
20.根据权利要求1所述的方法，其中所述接合结构与所述导电结构直接物理和电接触，并且其中所述导电结构包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍NiP、磷化镍-钯-金NiP-Pd-Au。
21.根据权利要求1所述的方法，其中所述接合结构包括来自下面的材料组的至少一种材料、元件或合金，该组由下述各项构成：银、锌、锡、铟、铜、金、钯、铅。
22.根据权利要求1所述的方法，其中在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接还包括：
形成导电结构，其中所述导电结构与所述第一导电层之间的物理粘附比所述导电结构与所述电绝缘材料之间的粘附更好。
23.根据权利要求1所述的方法，其中在所述电绝缘材料上形成导电结构、其中所述导电结构的至少一部分与所述导电材料直接物理和电连接还包括：
形成导电结构，其中所述导电结构的至少另一部分从电绝缘材料分离。
24.根据权利要求1所述的方法，还包括：
在所述导电结构上形成层，以及随后在所述层上形成接合结构。
25.根据权利要求24所述的方法，其中所述层包括来自下面的材料组的至少一种材料，该组由下述各项构成：磷化镍NiP、磷化镍-钯-金NiP-Pd-Au。
26.一种芯片封装，包括：
形成在芯片侧上的电绝缘材料；
形成在所述电绝缘材料中的沟槽;
沉积在所述沟槽中的导电材料，其中所述导电材料电连接到形成在所述芯片侧上的至少一个接触焊盘；
形成在所述电绝缘材料上的导电结构，其中所述导电结构包括第一导电层和凸块下金属化结构的均质结构，并且其中所述导电结构的至少一部分与所述导电材料直接物理和电连接；以及
形成在所述导电结构上的接合结构。
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