CN103761939B - Display - Google Patents
Display Download PDFInfo
- Publication number
- CN103761939B CN103761939B CN201410058207.4A CN201410058207A CN103761939B CN 103761939 B CN103761939 B CN 103761939B CN 201410058207 A CN201410058207 A CN 201410058207A CN 103761939 B CN103761939 B CN 103761939B
- Authority
- CN
- China
- Prior art keywords
- transistor
- shift
- signal
- fegister
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of display, including panel, data driver and scanner driver.Panel includes pixel, data wire and scan line.Data wire is in order to pass data signals to pixel, and scan line is in order to transmit scanning signal to pixel.Data driver is in order to provide data signal, and scanner driver is in order to provide scanning signal.Scanner driver includes shift-register circuit.Shift-register circuit includes multistage feedback with carry shift fegister and at least one first order buffer shift register.Multistage feedback with carry shift fegister includes the first feedback with carry shift fegister and the second feedback with carry shift fegister.First feedback with carry shift fegister starts the second feedback with carry shift fegister in order to produce the first enabling signal.First enabling signal startup first order buffer shift register is to produce the first output signal, and the first output signal corresponds to described at least scan signal.
Description
The application is that the invention of filing date in December, 2010 Application No. of 6 days 201010593646.7 is special
The divisional application of profit application (denomination of invention: display).
Technical field
The invention relates to a kind of display, and independently produce enabling signal in particular to one
And the display of output signal.
Background technology
The schematic diagram of conventional shift register circuit, Fig. 2 it is schematically shown as referring to Fig. 1 and Fig. 2, Fig. 1
It is schematically shown as the signal timing diagram of Fig. 1.Conventional shift register circuit 122 includes several levels shift register.For
For the sake of convenient explanation, say as a example by the 1st grade of shift register SR1 to the 4th grade of shift register SR4 at this
Bright.1st grade of shift register SR1 to the 4th grade of shift register SR4 is in order to produce the 1st grade of output signal
O1 to the 4th grade of output signal O4.1st grade of output signal O1 of the 1st grade of shift register SR1 can be defeated
Enter to the 2nd grade of shift register SR2, and start the 2nd grade of shift register SR2 produce the 2nd grade output letter
Number O2.2nd grade of output signal O2 of the 2nd grade of shift register SR2 can input to 3rd level shift LD
Device SR3, and start 3rd level shift register SR3 generation 3rd level output signal O3.3rd level shifts
3rd level output signal O3 of depositor SR3 can input to the 4th grade of shift register SR4, and starts
4 grades of shift register SR4 produce the 4th grade of output signal O4, by that analogy.
Refer to Fig. 3, Fig. 3 and be schematically shown as the circuit diagram of the first conventional shift depositor.1st grade of displacement is posted
Storage SR1 includes transistor T1 to T4.Transistor T1 exports the 1st grade according to clock pulse signal CK1
Output signal O1, and transistor T2 coupling transistors T1 be controlled by the 2nd grade of shift register SR output
The 2nd grade of output signal O2.Transistor T3 is controlled by the of the 2nd grade of buffer shift register SR2 output
2 grades of output signals O2, and transistor T4 coupling transistors T3, and according to the 1st grade of enabling signal STV
Drive transistor T1.Transistor T2 coupled electric capacity Cb is coupled to transistor T1 and transistor T2.2nd
The circuit design of level shift register SR2 with the 1st grade feedback with carry shift fegister SR1 is identical goes to live in the household of one's in-laws on getting married the most separately at this
State.
Refer to Fig. 4, Fig. 4 and be schematically shown as the circuit diagram of the second conventional shift depositor.Fig. 4 Yu Fig. 3 is not
It is that with part the shift register SR1 ' and SR2 ' of Fig. 4 further include transistor T5.Transistor T5 is controlled
Current potential in node B shifts optionally to start according to clock pulse signal CK1 output enabling signal C2
Depositor SR2.
But, display floater can viewing area (or referred to as AA district), its scan line and data wire interlock,
When the voltage on data wire changes, the related voltage affected in scan line.So conventional shift is deposited
The output signal of device circuit can be disturbed by noise.When the output signal by noise jamming is as next stage
During the input of shift register, cause the operation exception of shift-register circuit by making noise be exaggerated.
Summary of the invention
The invention relates to a kind of display, it uses the output of carry (Carry) shift register independence to open
Dynamic signal also uses the output of buffering (Buffer) shift register independence to carry out output signal.Owing to buffering displacement is posted
It is two independent loops that storage and feedback with carry shift fegister separate, and therefore buffer shift register generation is defeated
Going out signal will not be as the enabling signal of next stage.Consequently, it is possible to when buffer shift register is done by noise
When disturbing, noise will not be input to next stage.So shift register electricity will not be caused because noise amplifies
The situation generation that dataway operation is abnormal.
According to another aspect of the invention, it is proposed that a kind of display.Display includes panel, data driver
And scanner driver.Panel includes pixel, data wire and scan line.Data wire is in order to pass data signals to
Pixel, and scan line is in order to transmit scanning signal to pixel.Data driver in order to provide data signal, and
Scanner driver is in order to provide scanning signal.Scanner driver includes shift-register circuit.Shift register
Circuit includes multistage feedback with carry shift fegister and at least one first order buffer shift register.Multistage carry shifts
Depositor includes the first feedback with carry shift fegister and the second feedback with carry shift fegister.First feedback with carry shift fegister
The second feedback with carry shift fegister is started in order to produce the first enabling signal.First enabling signal starts the first order and delays
Detrusion bit register is to produce the first output signal, and the first output signal is believed corresponding to described at least one scan
Number.
Accompanying drawing explanation
For the above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing to this
Bright detailed description of the invention elaborates, wherein:
Fig. 1 is schematically shown as the schematic diagram of conventional shift register circuit.
Fig. 2 is schematically shown as the signal timing diagram of Fig. 1.
Fig. 3 is schematically shown as the circuit diagram of the first conventional shift depositor.
Fig. 4 is schematically shown as the circuit diagram of the second conventional shift depositor.
Fig. 5 is schematically shown as the schematic diagram of a kind of display.
Fig. 6 is schematically shown as the schematic diagram of a kind of panel.
Fig. 7 is schematically shown as the partial schematic diagram of the shift-register circuit according to first embodiment.
Fig. 8 is schematically shown as the first circuit diagram of feedback with carry shift fegister and buffer shift register.
Fig. 9 is schematically shown as the signal timing diagram of Fig. 8.
Figure 10 is schematically shown as the second circuit diagram of feedback with carry shift fegister and buffer shift register.
Figure 11 is schematically shown as the signal timing diagram of Figure 10.
Figure 12 is schematically shown as the partial schematic diagram of the shift-register circuit according to second embodiment of the invention.
Figure 13 is schematically shown as the partial schematic diagram of the shift-register circuit according to third embodiment of the invention.
Main element symbol description:
50: display
122: conventional shift register circuit
510: panel
512: pixel
514: scan line
516: data wire
520: scanner driver
522,524,526: according to the shift-register circuit of present pre-ferred embodiments
530: data driver
SR1～SR4, SR1 '～SR4 ', SR1a～SR5a, SR1b～SR5b: shift register
B, B ': node
T1～T5, T1a～T5a, T1b～T5b: transistor
Cb, Cb ': coupling electric capacity
C1～C3: electric capacity of voltage regulation
Detailed description of the invention
Be schematically shown as the schematic diagram of a kind of display referring to Fig. 5 and Fig. 6, Fig. 5, Fig. 6 is schematically shown as one
Plant the schematic diagram of panel.Display 50 includes panel 510, scanner driver 520 and data driver 530.
Panel 510 includes pixel 512, scan line 514 and data wire 516.Data driver 530 is in order to provide
Data signal D1 to Dm, and scanner driver 520 is in order to provide scanning signal S1 to Sn.Data wire
516 in order to transmit data signal D1 to Dm to pixel 512, and scan line 514 is in order to transmit scanning letter
Number S1 to Sn is to pixel 512.Aforementioned scanner driver 520 for example, amorphous silicon gate driver
(Amorphous Silicon Gate, ASG), and it is formed at panel 510.
Scanner driver 520 include shift-register circuit in order to provide correspond respectively to scan signal S1 extremely
The output signal of Sn.Shift-register circuit uses the output of carry (Carry) shift register independence to start
Signal also uses the output of buffering (Buffer) shift register independence to carry out output signal.Owing to buffering displacement is posted
It is two independent loops that storage and feedback with carry shift fegister separate, and therefore buffer shift register produces
Output signal will not be as the enabling signal of next stage.Consequently, it is possible to when buffer shift register is made an uproar
During sound interference, noise will not be input to next stage.So displacement will be caused to post because noise amplifies
The facts of latch circuit operation exception occurs.Following hereby further illustrate shift register with several embodiments
The composition of circuit.
First embodiment
Refer to Fig. 7, Fig. 7 and be schematically shown as the partial schematic diagram of the shift-register circuit according to first embodiment.
First embodiment is explanation as a example by one-level feedback with carry shift fegister collocation first-level buffer shift register.Before
State scanner driver 520 and farther include shift-register circuit 522.Shift-register circuit 522 in order to
Output corresponds respectively to scan the 1st grade of output signal O1 of signal S1 to S4 to the 4th grade of output signal
O4.Shift-register circuit 522 includes the 1st grade of grading bit shift of feedback with carry shift fegister SR1a to the 4th
Depositor SR4a and the 1st grade of buffer shift register SR1b are to the 4th grade of buffer shift register SR4b.
It follows that the number of the feedback with carry shift fegister of shift-register circuit 522 and buffer shift register
Identical.1st grade of feedback with carry shift fegister SR1a to the 4th grade of feedback with carry shift fegister SR4a produces respectively
2nd grade of enabling signal C2 is to the 5th grade of enabling signal C5, and the 1st grade of buffer shift register SR1b is extremely
4th grade of buffer shift register SR4b produces the 1st grade of output signal O1 respectively to the 4th grade of output signal
O4.1st grade of output signal O1 is to the 4th grade of output signal O4 respectively with the 1st grade of enabling signal C1 extremely
4th grade of enabling signal C4 is generated synchronously with.
1st grade of enabling signal STV starts the 1st grade of feedback with carry shift fegister SR1a and produces the 2nd grade of startup
Signal C2, the 1st grade of enabling signal STV also starts the 1st grade of buffer shift register SR1b output the 1st
Level output signal O1.2nd grade of enabling signal C2 starts the 2nd grade of feedback with carry shift fegister SR2a and produces the
3 grades of enabling signals C3, the 2nd grade of enabling signal C2 to start the 2nd grade of buffer shift register SR2b defeated
Go out the 2nd grade of output signal O2.3rd level enabling signal C3 starts 3rd level feedback with carry shift fegister SR3a
Producing the 4th grade of enabling signal C4,3rd level enabling signal C3 also starts 3rd level buffer shift register
SR3b exports 3rd level output signal O3.4th grade of enabling signal C4 starts the 4th grading bit shift and deposits
Device SR4a produces the 5th grade of enabling signal C5, and the 4th grade of enabling signal C4 also starts the 4th grade of buffering displacement
Depositor SR4b exports the 4th grade of output signal O4.By that analogy, subsequent stages feedback with carry shift fegister
Similar to aforementioned to buffer shift register operating principle, repeat the most separately at this.
Display floater can viewing area (or referred to as AA district), its scan line and data wire interlock, work as data
When voltage on line changes, the related voltage affected in scan line.So shift-register circuit
Output signal can be disturbed by noise.When output signal the inputting as next stage by noise jamming
Time, cause the operation exception of shift-register circuit by making noise be exaggerated.
On the contrary, be two owing to the buffer shift register of first embodiment and feedback with carry shift fegister separate
Individual independent loop, the output signal that therefore buffer shift register produces will not be posted as next stage displacement
The enabling signal of storage unit.Consequently, it is possible to when buffer shift register is by noise jamming, noise
Next stage shift register cell will not be input to.So displacement will be caused to post because noise amplifies
The facts of storage operation exception occurs.
It is schematically shown as feedback with carry shift fegister and buffer shift register referring to Fig. 8 and Fig. 9, Fig. 8
The first circuit diagram, Fig. 9 is schematically shown as the signal timing diagram of Fig. 8.1st grade of feedback with carry shift fegister SR1a
Including transistor T1a to T4a, and buffer shift register SR1b includes transistor T1 to T4.Wherein
The area ratio of transistor T1 and transistor T1a is about 5～20.Transistor T1 is according to clock pulse signal
CK1 exports the 1st grade of output signal O1, and transistor T2 coupling transistors T1 be controlled by the 2nd grade and delay
2nd grade of output signal O2 of detrusion bit register SR2b output.Transistor T3 is controlled by the 2nd grade of buffering
2nd grade of output signal O2 of shift register SR2b output, and transistor T4 coupling transistors T3,
And drive transistor T1 according to the 1st grade of enabling signal STV.Transistor T2 coupled electric capacity Cb is coupled to
Transistor T1 and transistor T2.The circuit design of the 2nd grade of feedback with carry shift fegister SR2a is grading with the 1st
Bit shift register SR1a is identical to be repeated the most separately at this.
The circuit design of the 1st grade of buffer shift register SR1b and the 1st grade of feedback with carry shift fegister SR1a
It is substantially the same.Transistor T1a exports the 2nd grade of enabling signal C2 according to clock pulse signal CK1, and
Transistor T2a coupling transistors T1a is also controlled by the 2nd of the 2nd grade of buffer shift register SR2b output
Level output signal O2.Transistor T3a is controlled by the 2nd of the 2nd grade of buffer shift register SR2b output
Level output signal O2, and transistor T4a coupling transistors T3a, and according to the 1st grade of enabling signal STV
Drive transistor T1a.Transistor T2a coupled electric capacity Cb ' is coupled to transistor T1a and transistor T2a.
The circuit design of the 2nd grade of buffer shift register SR2b is identical with the 1st grade of buffer shift register SR1b,
Repeat the most separately at this.
Refer to Figure 10 and Figure 11, Figure 10 and be schematically shown as feedback with carry shift fegister and buffer shift register
The second circuit diagram, Figure 11 is schematically shown as the signal timing diagram of Figure 10.Feedback with carry shift fegister moves with buffering
The circuit of bit register, in addition to illustrating such as Fig. 8, also can illustrate such as Figure 10.It is the 1st grading that Figure 10 illustrates
Bit shift register SR1a ' the 1st grade of feedback with carry shift fegister SR1a difference illustrating with Fig. 8 be:
1st grade of feedback with carry shift fegister SR1a ' further includes transistor T5a, electric capacity of voltage regulation C1, electric capacity of voltage regulation C2
And electric capacity of voltage regulation C3, and transistor T3a is controlled by the 3rd output signal O3.Transistor T5a is coupled to
Transistor T1a, transistor T3a and transistor T4a, and it is controlled by clock pulse signal CK3.Voltage stabilizing electricity
The one end holding C1 is coupled to the control end of transistor T1a, and the other end of electric capacity of voltage regulation C1 receives clock
Pulse signal CK2.One end of electric capacity of voltage regulation C2 is coupled to the control end of transistor T1a, and electric capacity of voltage regulation
The other end of C2 receives clock pulse signal CK3.One end of electric capacity of voltage regulation C3 is coupled to transistor T1a
Control end, and electric capacity of voltage regulation C3 the other end receive clock pulse signal CK4.2nd grading bit shift
The circuit design of depositor SR2a ' with the 1st grade feedback with carry shift fegister SR1a ' is identical goes to live in the household of one's in-laws on getting married the most separately at this
State.
It addition, the 1st grade of buffer shift register SR1b illustrating of Figure 10 ' the 1st grading with what Fig. 8 illustrated
Bit shift register SR1b difference is: the 1st grade of feedback with carry shift fegister SR1b ' further includes crystal
Pipe T5, and transistor T3 is controlled by 3rd level output signal O3.Transistor T5 be coupled to transistor T1,
Transistor T3 and transistor T4, and it is controlled by clock pulse signal CK3.2nd grade of buffering shift LD
The circuit design of device SR2b ' and the 1st grade of buffer shift register SR1b ' identical, repeat the most separately at this.
Specifically, the design of electric capacity of voltage regulation C1, electric capacity of voltage regulation C2 and electric capacity of voltage regulation C3 can be entered
One step restrains noise produced by clock pulse signal CK1.For example, as clock pulse signal CK1
When current potential rises, owing to grid and the source electrode of transistor T1a also exist parasitic capacitance, therefore can related shadow
Ring the current potential of node B.So, by clock pulse signal CK2, clock pulse signal CK3 and clock
The current potential of pulse signal CK4 declines the current potential of payment clock pulse signal CK1 and rises, to guarantee that displacement is posted
The regular event of latch circuit.
Second embodiment
Refer to Figure 12, Figure 12 and be schematically shown as the portion of the shift-register circuit according to second embodiment of the invention
Divide schematic diagram.Second embodiment is with first embodiment difference: feedback with carry shift fegister and buffering
The number of shift register is different.Second embodiment is by one-level feedback with carry shift fegister collocation several levels buffering
Shift register, for convenience of description for the sake of, the second embodiment be use one-level feedback with carry shift fegister collocation
Explanation as a example by the shift-register circuit of two-stage buffer shift register.
Aforementioned scanner driver 520 farther includes shift-register circuit 524.Shift-register circuit
524 is defeated to the 5th grade in order to export the 1st grade of output signal O1 corresponding respectively to scan signal S1 to S5
Go out signal O5.Shift-register circuit 524 includes that the 1st grade of feedback with carry shift fegister SR1a is to 3rd level
Feedback with carry shift fegister SR3a and the 1st grade of buffer shift register SR1b are to the 5th grade of buffering shift LD
Device SR5b.It follows that the number of the feedback with carry shift fegister of shift-register circuit 522 is less than buffering
Shift register.1st grade of feedback with carry shift fegister SR1a divides to 3rd level feedback with carry shift fegister SR3a
Not Chan Sheng the 2nd grade of enabling signal C2 to 3rd level enabling signal C4, and the 1st grade of buffer shift register
It is defeated to the 5th grade that SR1b to the 5th grade of buffer shift register SR5b produces the 1st grade of output signal O1 respectively
Go out signal O5.
1st grade of enabling signal STV starts the 1st grade of feedback with carry shift fegister SR1a and produces the 2nd grade of startup
Signal C2, the 1st grade of enabling signal STV also starts the 1st grade of buffer shift register SR1b output the 1st
Level output signal O1 and the 2nd grade of buffer shift register SR2b of startup export the 2nd grade of output signal O2.
2nd grade of enabling signal C2 starts the 2nd grade of feedback with carry shift fegister SR2a and produces 3rd level enabling signal C3,
2nd grade of enabling signal C2 also starts 3rd level buffer shift register SR3b output 3rd level output signal
O3 and the 4th grade of buffer shift register SR4b of startup export the 4th grade of output signal O4.By that analogy,
Subsequent stages feedback with carry shift fegister is similar to aforementioned to buffer shift register operating principle, the most another at this
Row repeats.
3rd embodiment
Refer to Figure 13, Figure 13 and be schematically shown as the portion of the shift-register circuit according to third embodiment of the invention
Divide schematic diagram.3rd embodiment is with first embodiment difference: feedback with carry shift fegister and buffering
The number of shift register is different.3rd embodiment is several levels carry of being arranged in pairs or groups by first-level buffer shift register
Shift register, for convenience of description for the sake of, the 3rd embodiment be use first-level buffer shift register collocation
Explanation as a example by the shift-register circuit of two-stage feedback with carry shift fegister.
Aforementioned scanner driver 520 farther includes shift-register circuit 526.Shift-register circuit
526 is defeated to the 2nd grade in order to export the 1st grade of output signal O1 corresponding respectively to scan signal S1 to S2
Go out signal O2.Shift-register circuit 526 includes the 1st grade feedback with carry shift fegister SR1a to the 5th grade
Feedback with carry shift fegister SR5a and the 1st grade of buffer shift register SR1b are to the 2nd grade of buffering shift LD
Device SR2b.It follows that the number of the feedback with carry shift fegister of shift-register circuit 526 is moved with buffering
Bit register is different.1st grade of feedback with carry shift fegister SR1a to the 5th grade of feedback with carry shift fegister SR5a
The 2nd grade of enabling signal C2 of generation is to the 6th grade of enabling signal C6 respectively, and the 1st grade of buffering shift LD
Device SR1b to the 2nd grade of buffer shift register SR2b produces the 1st grade of output signal O1 respectively to the 2nd
Level output signal O2.
1st grade of enabling signal STV starts the 1st grade of feedback with carry shift fegister SR1a and produces the 2nd grade of startup
Signal C2, the 2nd grade of enabling signal C2 starts the 2nd grade of feedback with carry shift fegister SR2a generation 3rd level and opens
Dynamic signal C3.2nd grade of enabling signal C2 and 3rd level enabling signal C3 start the displacement of the 1st grade of buffering and post
Storage SR1b exports the 1st grade of output signal O1.
3rd level enabling signal C3 starts 3rd level feedback with carry shift fegister SR3a and produces the 4th grade of startup letter
Number C4, the 4th grade of enabling signal C4 starts the 4th grade of feedback with carry shift fegister SR4a and produces the 5th grade of startup
Signal C5.4th grade of enabling signal C4 and the 5th grade of enabling signal C5 start the 2nd grade of buffering shift LD
Device SR2b exports the 2nd grade of output signal O2.By that analogy, subsequent stages feedback with carry shift fegister is with slow
Detrusion bit register operating principle is similar to aforementioned, repeats the most separately at this.
Shift-register circuit disclosed by the above embodiment of the present invention and display, have multiple advantages,
Hereinafter only enumerate certain advantages to be described as follows:
One, suppression is because of noise produced by clock pulse signal, to guarantee the normal of shift-register circuit
Action.
Two, suppression panel can noise produced by viewing area, to guarantee the normal dynamic of shift-register circuit
Make.
Although the present invention discloses as above with preferred embodiment, so it is not limited to the present invention, any
Those skilled in the art, without departing from the spirit and scope of the present invention, when making a little amendment and complete
Kind, therefore protection scope of the present invention is when with being as the criterion that claims are defined.
Claims (10)
1. a display, including:
One panel, including:
Multiple pixels；
A plurality of data lines, in order to transmit multiple data signal to described pixel；And
Multi-strip scanning line, in order to transmit multiple scanning signal to described pixel；
One data driver, in order to provide described data signal；And
Scan driver, in order to provide described scanning signal, this scanner driver includes a shift register
Circuit, this shift-register circuit includes:
Multistage feedback with carry shift fegister, described multistage feedback with carry shift fegister includes:
One first feedback with carry shift fegister, this first feedback with carry shift fegister receives one first and opens
Dynamic signal；And
One second feedback with carry shift fegister, this first enabling signal starts the displacement of this first carry
Depositor and this first feedback with carry shift fegister in order to produce one second enabling signal start this
Binary bit shift register；And
At least one first order buffer shift register, this first enabling signal starts this first order buffering
Shift register is to produce one first output signal, and this first output signal corresponds to described scanning signal
At least scan signal.
2. display as claimed in claim 1, it is characterised in that this first output signal be with this first
Enabling signal is generated synchronously with.
3. display as claimed in claim 1, it is characterised in that described feedback with carry shift fegister is with described
The number of buffer shift register is different.
4. display as claimed in claim 1, it is characterised in that described shift-register circuit also includes:
One second level buffer shift register, this second enabling signal also starts this second level buffering shift LD
Device is to produce one second output signal, and this second level buffer shift register is that this first order buffers shift LD
The next stage of device.
5. display as claimed in claim 1, it is characterised in that this first order buffer shift register bag
Include:
One the first transistor, exports this first output signal according to one first clock pulse signal；
One transistor seconds, couples this first transistor and is controlled by one second output signal；
One third transistor, is controlled by this second output signal；
One the 4th transistor, couples this third transistor, and drives this first crystalline substance according to one the 3rd enabling signal
Body pipe；And
One first coupling electric capacity, this third transistor and the 4th transistor are coupled to through this first coupling electric capacity
This transistor seconds.
6. display as claimed in claim 5, it is characterised in that this first feedback with carry shift fegister includes:
One the 5th transistor, exports this first enabling signal according to this first clock pulse signal；
One the 6th transistor, couples the 5th transistor and is controlled by one second output signal；
One the 7th transistor, is controlled by this second output signal；
One the 8th transistor, couples the 7th transistor, and drives the 5th crystalline substance according to the 3rd enabling signal
Body pipe；And
One second coupling electric capacity, the 7th transistor and the 8th transistor are coupled to through this second coupling electric capacity
6th transistor.
7. display as claimed in claim 6, it is characterised in that this first transistor and the 5th crystal
The area ratio of pipe is 5～20.
8. display as claimed in claim 1, it is characterised in that this first order buffer shift register bag
Include:
One the first transistor, exports this first output signal according to one first clock pulse signal；
One transistor seconds, couples this first transistor and is controlled by one second output signal；
One third transistor, is controlled by this second output signal；And
One the 4th transistor, couples this third transistor, and drives this first crystalline substance according to one the 3rd enabling signal
Body pipe；
One the 5th transistor, couples this first transistor, this third transistor and the 4th transistor, and is subject to
Control in one the 3rd clock pulse signal；And
One first coupling electric capacity, this third transistor and the 4th transistor are coupled to through this first coupling electric capacity
This transistor seconds.
9. display as claimed in claim 8, it is characterised in that this first feedback with carry shift fegister includes:
One the 6th transistor, exports this first enabling signal according to this first clock pulse signal；
One the 7th transistor, couples the 6th transistor and is controlled by one second output signal；
One the 8th transistor, is controlled by this second output signal；
One the 9th transistor, couples the 8th transistor, and drives the 6th crystalline substance according to the 3rd enabling signal
Body pipe；
The tenth transistor, couples the 6th transistor, the 8th transistor and the 9th transistor, and is subject to
Control in the 3rd clock pulse signal；
One second coupling electric capacity, the 8th transistor and the 9th transistor are coupled to through this second coupling electric capacity
7th transistor；
One first electric capacity of voltage regulation, one end of this first electric capacity of voltage regulation is coupled to the control end of the 5th transistor,
And the other end of this first electric capacity of voltage regulation receives a second clock pulse signal；
One second electric capacity of voltage regulation, one end of this second electric capacity of voltage regulation is coupled to the control end of the 5th transistor,
And the other end of this second electric capacity of voltage regulation receives the 3rd clock pulse signal；And
One the 3rd electric capacity of voltage regulation, one end of the 3rd electric capacity of voltage regulation is coupled to the control end of the 5th transistor,
And the 3rd electric capacity of voltage regulation the other end receive one the 4th clock pulse signal.
10. display as claimed in claim 9, it is characterised in that this first transistor is brilliant with the 6th
The area ratio of body pipe is 5～20.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410058207.4A CN103761939B (en) | 2010-12-06 | 2010-12-06 | Display |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010593646.7A CN102486909B (en) | 2010-12-06 | 2010-12-06 | Displayer |
| CN201410058207.4A CN103761939B (en) | 2010-12-06 | 2010-12-06 | Display |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010593646.7A Division CN102486909B (en) | 2010-12-06 | 2010-12-06 | Displayer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103761939A CN103761939A (en) | 2014-04-30 |
| CN103761939B true CN103761939B (en) | 2016-08-24 |
Family
ID=50529168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410058207.4A Active CN103761939B (en) | 2010-12-06 | 2010-12-06 | Display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103761939B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304008B (en) * | 2015-11-18 | 2018-10-30 | 深圳市华星光电技术有限公司 | Gate drivers and touch panel with the gate drivers |
| CN112925135B (en) * | 2021-03-29 | 2024-03-15 | 绵阳惠科光电科技有限公司 | Control switch of driving circuit, array substrate and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030128180A1 (en) * | 2001-12-12 | 2003-07-10 | Kim Byeong Koo | Shift register with a built in level shifter |
| US20030189542A1 (en) * | 2002-04-08 | 2003-10-09 | Samsung Electronics Co., Ltd. | Liquid crystal display device |
| CN1841565A (en) * | 2005-03-30 | 2006-10-04 | 三菱电机株式会社 | Shift register circuit and image display apparatus containing the same |
| US20060291298A1 (en) * | 2005-06-28 | 2006-12-28 | Lg Philips Lcd Co., Ltd. | Liquid crystal display and driving method thereof |
-
2010
- 2010-12-06 CN CN201410058207.4A patent/CN103761939B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030128180A1 (en) * | 2001-12-12 | 2003-07-10 | Kim Byeong Koo | Shift register with a built in level shifter |
| US20030189542A1 (en) * | 2002-04-08 | 2003-10-09 | Samsung Electronics Co., Ltd. | Liquid crystal display device |
| CN1841565A (en) * | 2005-03-30 | 2006-10-04 | 三菱电机株式会社 | Shift register circuit and image display apparatus containing the same |
| US20060291298A1 (en) * | 2005-06-28 | 2006-12-28 | Lg Philips Lcd Co., Ltd. | Liquid crystal display and driving method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103761939A (en) | 2014-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105405383B (en) | Shifting deposit unit, shift register and its driving method, display device | |
| CN105895011B (en) | Shift register cell, gate driving circuit and display panel | |
| US11087855B2 (en) | Shift register unit and driving method, gate drive circuit and display device | |
| CN104575419B (en) | Shift register and driving method thereof | |
| CN108682397A (en) | Shift register cell, gate driving circuit, display device and driving method | |
| CN101303896B (en) | Shift buffer capable of reducing frequency coupling effect and shift buffer unit | |
| CN105096803B (en) | Shift register and its driving method, gate driving circuit, display device | |
| CN105355187B (en) | GOA circuits based on LTPS semiconductor thin-film transistors | |
| CN104103244B (en) | Liquid-crystal display and bi-directional shift apparatus for temporary storage thereof | |
| CN104835442B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN106847221A (en) | Shift register cell, gate driving circuit and driving method | |
| CN101594135B (en) | Bootstrap circuit, shift register employing the same and display device | |
| US20120105393A1 (en) | Shift register unit, gate driving device and liquid crystal display | |
| CN106898319A (en) | A kind of GOA circuits and liquid crystal display panel | |
| CN109935208A (en) | Shift register cell, gate driving circuit, display device and driving method | |
| CN101587752A (en) | Displacement register | |
| CN101783124A (en) | Grid electrode driving circuit unit, a grid electrode driving circuit and a display device | |
| CN104718568A (en) | Display device and drive method thereof | |
| CN109346007A (en) | Shifting deposit unit, gate driving circuit, display device and driving method | |
| CN101971242A (en) | Display panel driving circuit, liquid crystal display device, shift register, liquid crystal panel, and display device driving method | |
| CN103456259A (en) | Grid electrode driving circuit, grid line driving method and display device | |
| WO2019218625A1 (en) | Shift register unit and driving method therefor, gate driving circuit and display device | |
| CN106157893A (en) | Shift register cell and driving method, drive circuit and display device | |
| CN108694894A (en) | Shifting cache and gate driving circuit, display panel and equipment and driving method | |
| CN109935197A (en) | Shift register cell, gate driving circuit, display device and driving method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |