CN103744818B - Crossbar bus and the data Bridge equipment of ahb bus - Google Patents
Crossbar bus and the data Bridge equipment of ahb bus Download PDFInfo
- Publication number
- CN103744818B CN103744818B CN201310465421.7A CN201310465421A CN103744818B CN 103744818 B CN103744818 B CN 103744818B CN 201310465421 A CN201310465421 A CN 201310465421A CN 103744818 B CN103744818 B CN 103744818B
- Authority
- CN
- China
- Prior art keywords
- port
- signal
- data
- write
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Multi Processors (AREA)
Abstract
The present invention relates to the data Bridge equipment of a kind of Crossbar bus and ahb bus, include apparatus body, it is characterized in: in apparatus body, be provided with Crossbar bus, in Crossbar bus connect have mutual data communication function control device, read data FIFO, write data FIFO, address FIFO device, control FIFO device, address producing device, the data selector MUX101 of at least 3 N positions, data selector MUX102 and data selector MUX103, two input or doors.Thus, pass through ahb bus, match with each function FIFO device, constitute effective connection-bridge structure, realize the read/write operation initiated from equipment in ahb bus of main equipment in Crossbar bus, make the data can communicating with zero defect while meeting the respective timing sequence specification of both sides bus.
Description
Technical field
The present invention relates to a kind of data Bridge equipment, particularly relate to the data of a kind of Crossbar bus and ahb bus
Bridge equipment.
Background technology
AHB (Advanced High-performance Bus) bus specification is a part for AMBA bus specification.AMBA
Bus specification is the bus specification that ARM company proposes.Owing to the specification of AMBA is opening, utilize license terms designer
The AMBA interface of exploitation that can be free oneself so that AMBA on-chip bus technology is widely used.
Ahb bus specification is used as the inner high speed bus of SoC design, carry high-speed equipment.Ahb bus system is by leading
Equipment, constitute from equipment and infrastructure device.Infrastructure device is controlled MUX by moderator, data multiplex selector, address
Constitute with decoder.By needing the main equipment taking bus to propose to take bus request to moderator, arbiter grants is given and is specified
Main equipment.Any time cycle only one of which main equipment can access bus, is written and read operation to what it was specified from equipment.
Bus unified planning is from the address of equipment, and according to address choice, which carries out data communication from equipment and main equipment to decoder.Award
Power access mechanism realizes by MUX: moderator is transferred to address and to write data many by obtaining the main equipment sequence number authorized
Which main equipment road, to select access bus；Address decoder needs the address choice main equipment accessed according to main equipment, and is
Writing data multiplex provides control signal corresponding from equipment with gating.
Main equipment must obtain mandate and access bus, just can carry out AHB transmission.This process starts from bus to arbitration
Device sends request signal, and then moderator determines which main equipment can obtain mandate and access bus.
Obtain the bus authorized and start AHB transmission, first send address and control signal.These signals provide address letter
Breath, transmission direction and bandwidth and burst type.Determine main equipment according to address and control signal and which be from linking of devices,
Carrying out data transmission, data transmission is completed by data/address bus.For avoiding the occurrence of tristate bus line, AHB will read and write bus separately, write
Data/address bus is for transmitting to from the data of equipment from main equipment, and read data bus is for passing from the data from equipment to main equipment
Defeated.Often include an address and control cycle, one or more data cycles than transmission.The address control cycle can not be expanded,
Therefore must be at a periodic sampling address signal from equipment.The data cycle can pass through HREADY signal extension.But HREADY
A wait state is added so that obtaining the extra time from equipment from equipment and providing or sampled data for giving transmission time low.Separately
Transmission state is reflected by response signal HRESP outward from equipment.
The complete burst transmission that generally main equipment completes, moderator just can license to other main equipment and connect
Enter bus.But interrupt burst transmission for avoiding excessive decision delay, moderator to be likely to.Main equipment in this case
Must ask again to access bus to carry out the transmission of the remainder of burst interrupted.
Crossbar(i.e. CrossPoint) it is referred to as corsspoint switch matrix or crossbar switching matrix, it is that industry is generally acknowledged
For building the first-selected switch network architecture of hicap.Bus switch, annular exchange and shared drive switching fabric are all
It is shared bandwidth in a way, and the switching network of crossbar fabric breaches this restriction completely, in exchange network
Portion does not has the bottleneck of bandwidth, will not produce obstruction not because of bandwidth resources.The switching network of crossbar fabric have employed one
Plant matrix structure and achieve nonblocking switching.Crossbar exchange network does not has any bottleneck at datum plane.Exactly because this
Crossbar introduces this new exchanged form of switching matrix, has abandoned the exchanged form of shared bandwidth, in data exchange side
It it is a kind of revolutionary change in formula.The extended capability of Crossbar switching network is very strong, and it is very big that exchange capacity can do, base
This is not limited by hardware condition, and the most single chips exchange capacity is between 256G-700G, and multiple chips can build T level and be
To the large-scale switching network of a few T capacity, it is sufficient to meet several years networks of the current and future demand to exchange capacity, and along with firmly
The progress of part integrated technology, the capacity of single Crossbar chip support can be bigger.
Each incoming line has a crosspoint with each outlet line.In intersection by a semiconductor switch
Connect incoming line and outlet line.When needing to exchange to the output point of another interface from the incoming line of certain interface
Time, under the control of CPU or switching matrix controller, the switch in crosspoint being connected, data are sent to another interface.
Summary of the invention
The purpose of the present invention is contemplated to solve the above-mentioned problems in the prior art, it is provided that a kind of Crossbar bus
Data Bridge equipment with ahb bus.
The purpose of the present invention is achieved through the following technical solutions:
Crossbar bus and the data Bridge equipment of ahb bus, include apparatus body, wherein: described equipment
Basis is the most internal is provided with Crossbar bus, and connecting in Crossbar bus has the function control device of mutual data communication, reading
Data FIFO, write data FIFO, address FIFO device, control FIFO device, address producing device, at least 3 N positions
Data selector MUX101, data selector MUX102 and data selector MUX103, two input or doors；If ahb bus number
It is that M, L are less than or equal to M according to the bit wide that bit wide is L, Crossbar, and defines P=M/L.
Above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described address producing device
Address input end mouth is din101, output port is dout101～dout10P, and address wire Caddr by Crossbar bus is defeated
Enter the din101 port to address producing device；Address signal daddr101～daddr10P input is produced by address producing device
FPDP daddr_in101～daddr_in10P is write to address FIFO device；Wherein address signal daddr101～
Relation between daddr10P is, daddr101=Cdaddr, daddr102=Caddr+1, daddr103=Caddr+2, until
daddr10P=Caddr+P。
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described control
FIFO device, includes and writes input end of clock mouth wclk101, reads input end of clock mouth rclk101, controls input port
Writen_in101 and readen_in101, controlling information input terminal mouth is write_in10, controls information output mouth
Write_out101～write_out10P, empty full State-output port read_out101, write_out101, by
Crossbar bus clock TCLK input to control FIFO device write clock port wclk101, by the bus clock HCLK of AHB
Input to control FIFO device and read clock port rclk101；Produced by function control device cout101a and cout101b port
Read_en101 and write_en101 signal be input to control input port writen_in101 and readen_in101；By
Cwrite signal in Crossbar bus is input to information input terminal write_in10 port, to be the most also input to or door
Input 1 port of Or10；Read_full101, Write_ is produced by read_out101 port and write_out101 port
Full101 inputs to control coin101a and the coin101b port of function control device；By write_out101～write_
Out10P port P control signal write101 of generation～write10P are input to the data of the data selector MUX101 of P position
Port.
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described ground
Location FIFO device, includes: write input end of clock mouth wclk102, reads input end of clock mouth rclk102, controls input port
Writen_in102 and readen_in102, address information input port is addr_in10, controls information output a port ddr_
Out101～addr_out10P, empty full State-output port read_out102, empty full State-output port write_out102；
By Crossbar bus clock TCLK input to control FIFO device write clock port wclk102, by the bus clock of AHB
HCLK inputs to control FIFO device and reads clock port rclk102；By function control device cout102a and cout102b port
Read_en102 and the write_en102 signal produced is input to control input port writen_in102 and readen_
in102；It is input to information input terminal addr_in10 port by the Caddr signal in Crossbar bus；By read_out102
Port and write_out102 port produce Read_full102, Write_full102 and input to the control of function control device
Coin102a and coin102b port；By addr_out101～addr_out10P port produce P address signal addr101～
Addr10P, is input to the FPDP of the data selector MUX102 of P position.
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described writes
Data FIFO, includes and writes input end of clock mouth wclk103, reads input end of clock mouth rclk103, controls input port
Writen_in103 and readen_in103, data message input port is wdata_in10, controls information output mouth
Wdata_out101～wdata_out10P, empty full State-output port read_out103, write_out103, by
Crossbar bus clock TCLK input to control FIFO device write clock port wclk103, by the bus clock CCLK of AHB
Input to control FIFO device and read clock port rclk103；Produced by function control device cout103a and cout103b port
Read_en103 and write_en103 signal be input to control input writen_in103 and readen_in103 port；By
Cwdata signal in Crossbar bus is input to information input terminal wdata_in10 port；By read_out103 port and
Write_out103 port produces Read_full103, Write_full103 and inputs to the control of function control device
Coin103a and coin103b port；P data-signal addr101 is produced by wdata_out101～wdata_out10P port
～addr10P is input to the FPDP of data selector MUX103 of P position.
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described reading
Data FIFO, including writing input end of clock mouth wclk104, reads input end of clock mouth rclk104, controls input port
Writen_in104 and readen_in104, data message input port is rdata_in10, controls information output mouth
Rdata_out10, empty full State-output port read_out104, write_out104；The annexation of port: by
Crossbar bus clock TCLK input to control FIFO device write clock port wclk104, by the bus clock HCLK of AHB
Input to control FIFO device and read clock port rclk104；Produced by function control device cout104a and cout104b port
Read_en104 and write_en104 signal be input to control input writen_in104 and readen_in104 port；By
Hrdata signal in ahb bus is input to information input terminal rdata_in10 port；By read_out104 port and write_
Out104 port produce Read_full104, Write_full104 input to function control device control coin104a and
Coin104b port；Produced reading data signal Crdata10 by rdata_out10 port and be transported to the reading of Crossbar bus
According in line Hrdata.
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described merit
Device can be controlled, including, clock signal input terminal mouth: clk10；Control signal input port include coin101a port,
Coin101b port, coin102a port, coin102b port, coin103a port, coin103b port, coin104a end
Mouth, coin104b port, Hsel10 port, Hready port, Hgrant port；Control signal output port includes cout101a
Port, cout101b port, cout102a port, cout102b port, cout103a port, cout103b port,
Cout104a port, cout104b port, selo101 port, selo102 port, selo103 port；By Crossbar bus
Clock TCLK inputs to function control device clock port clk10；Function is inputed to by Crossbar bus selected signal Csel
Control device control signal input port Csel10；Function control device control is inputed to by ahb bus selected signal Hgrant
Signal input port Hgrant10；Function control device control signal input is inputed to by ahb bus selected signal Hready
Mouth Hready10；By control the read_out101 port of FIFO device and write_out101 port produce Read_full101,
Write_full101 inputs to coin101a port and the coin101b port of function control device；By address FIFO device
Read_out102 port and write_out102 port produce Read_full102, Write_full102 signal and input to function
Control coin102a port and the coin102b port of device；By write data FIFO read_out103 port and
Write_out103 port generation Read_full103 signal, Write_full103 signal input to the control of function control device
Coin103a port processed and coin103b port；By the read_out104 port and the write_out104 that read data FIFO
Port generation Read_full104 signal, Write_full104 signal input to the control coin104a end of function control device
Mouth and coin104b port；The read_en101 produced respectively by function control device cout101a port and cout101b port
Signal and write_en101 signal are input to control writen_in101 port and the readen_in101 port of FIFO device；
The read_en102 signal produced respectively by function control device cout102a port and cout102b port and write_en102
Signal is input to writen_in10 the port 2 and readen_in102 port of address FIFO device；By function control device
Read_en103 signal and write_en103 signal that cout103a port and cout103b port produce respectively are input to write number
Writen_in103 port and readen_in103 port according to FIFO device；By function control device cout104a port and
Read_en104 signal and write_en104 signal that cout104b port produces respectively are input to read data FIFO
Writen_in104 and readen_in104 port, Read_en104 signal also to input to the defeated of two inputs or door Or10 simultaneously
Enter 2 ports；By the selection port of function control device selo101 port output sel101 signal to data selector MUX101,
Selo102 port output sel102 signal is to the selection end of data selector MUX102, selo103 port output sel103 signal
Selection port to data selector MUX103；Total to AHB by function control device burst10 port output Hburst10 signal
The Hburst interface of line；Connect by the Hburst of function control device burst10 port output Hburst10 signal to ahb bus
Mouthful；Hsize interface by function control device size10 port output Hsize10 signal to ahb bus；By function control device
Burst10 port output Hburst10 signal is to the Hburst interface of ahb bus；Defeated by function control device busreq10 port
Go out the Hbusreq10 signal Hbusreq interface to ahb bus.
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described merit
Device can be controlled and include nine kinds of duties, holding state, start state, write the address of data, control information transmission state, single
The data message solely write sends state；The data message write continuously sends state, hold mode, reads the address of data, controls letter
Breath transmission state, reads the wait state of data, reads data and sends state；Being converted to of each state described, 1) at holding state
Under, enter beginning state when Hsel10 is high, rest on this holding state the most always；2) state is started；Work as Hgrant10
Signal rests on this state when of being low；Judging when Hgrant10 signal is high when will be to the control letter operated from machine again
Number Cwrite, when Cwrite10 signal is high, NextState is for writing data latency state；When Cwrite10 signal is low,
NextState is address, control, data message transmission state；3) write the address of data, control information sends state；This state is entered
Entering NextState precondition is when Hready10 is high, if now Read_full102=1, then enters the data individually write
Information sends state；If now Read_full102=1, then enter the data message write continuously and send state；Hready10 is
Low, rest on this state the most always；4) data message individually write sends state, and NextState is holding state；5) write continuously
Data message send state；If Hready10=1, and Read_full102=1, then control FIFO device according to press-in before
Next control bit be read or write order is to determine NextState, if control FIFO device next bit be height, then jump to list
The data message solely write sends state；If the next bit controlling FIFO device is low, then jump to read the address of data, control letter
Breath transmission state；If Hready10=1, and Read_full102=0, then rest on this state；If Hready10=0, no matter
What value Read_full102 is, enters hold mode；6) hold mode；If Hready10=0, no matter what two other signal is
State, all remains in this state；If Hready10=1, judge still further below, if Read_full102=0, then enter and write continuously
Data message send state；If Read_full102=1, the most still further below one layer of judgement, if the next bit controlling FIFO device is
Height, then the data message jumping to individually write sends state；If the next bit controlling FIFO device is low, then jump to read data
Address, control information send state；7) read the address of data, the information that controls sends state, and NextState is for reading data latency
State；8) wait state of data is read；If Read_full104=0, then jump to read data and send state；If Read_
Full104=1, the most still rests on this state；9) reading data and send state, NextState is holding state.
Further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: 1) standby shape
State, for initializing to Bridge, enters holding state and four FIFO device is emptied initialization, empty data choosing
Select the selection signal of device, remove the enable of the read and write of FIFO device；2) under beginning state, OPADD FIFO device is write and is made
Can signal, control FIFO device write enable signal and write the write enable signal of data FIFO for storing address, controlling letter
Breath and data message；Send Hbusreq10 signal to the moderator in ahb bus；Remaining signal still keeps laststate
Value；3) under writing the address of data, control information transmission state, the reading sending address FIFO device enables signal, controls FIFO
The reading of device enables signal；Wherein selection signal sel1=sel1+1, sel2=sel2+1 of MUX；On remaining signal still keeps
The value of one state；4) under the data message transmission state individually write, the reading enable signal of data FIFO is write in transmission, empties
The reading reading to enable signal and control FIFO device of address FIFO device enables signal；Remaining signal still keeps laststate
Value；5) under the data message transmission state write continuously, the reading enable signal of data FIFO is write in transmission, and maintains address
The reading reading to enable signal and control FIFO device of FIFO device enables signal；Wherein MUX selection signal sel1=sel1+1,
sel2=sel2+1、sel3=sel3+3；And this state in ahb bus from equipment sending data group traffic information；
Remaining signal still keeps the value of laststate；6) in the hold state, all signals of this state keep the value of laststate；7)
Reading the address of data, controlling under information transmission state, the reading sending address FIFO device enables signal, controls FIFO device
Read enable signal and read the write enable signal of data FIFO；Remaining signal still keeps the value of laststate；8) at reading
According to wait state under, all signals of this state keep laststate value；9) under reading data transmission state, send and read data
The reading of FIFO device enables signal；Remaining signal still keeps the value of laststate.
Yet further, above-mentioned Crossbar bus and the data Bridge equipment of ahb bus, wherein: described number
The control line Cwrite that Cwrite10 signal is transported in Crossbar bus, data selector is produced according to selector MUX101
MUX102 produces Caddr10 signal and is transported to address wire Caddr in Crossbar bus, and data selector MUX103 produces
Cwdata10 signal is transported to the write data line Cwdata in Crossbar bus, and described two inputs or door produce Hready10 letter
Number input to ahb bus gets out signal Hready.
The advantage of technical solution of the present invention is mainly reflected in: by ahb bus, match with each function FIFO device,
Constitute effective connection-bridge structure, it is achieved the main equipment read/write behaviour initiated from equipment in ahb bus in Crossbar bus
Make, make the data can be without communicating of makeing mistakes while meeting the respective timing sequence specification of both sides bus.
Accompanying drawing explanation
Fig. 1 is the write operation schematic diagram of Crossbar to AHB equal bit wide data transmission.
Fig. 2 is that the write operation (AHB-32 position, Crossbar-128 position) of Crossbar to AHB difference bit wide data transmission shows
It is intended to.
Fig. 3 is the read operation schematic diagram of Crossbar to AHB equal bit wide data transmission.
Fig. 4 is the data Bridge equipment equal bit width conversion bridge connecting structure of process of Crossbar bus and ahb bus
Schematic diagram.
Fig. 5 Crossbar bus processes different bit width conversion bridge connecting structure from the data Bridge equipment of ahb bus and shows
It is intended to.
Fig. 6 is Crossbar to AHB Bridge state machine diagram.
Detailed description of the invention
Crossbar bus as shown in figs. 1 to 6 and the data Bridge equipment of ahb bus, include apparatus body, its
Being particular in that and be: be provided with Crossbar bus in apparatus body, connecting in Crossbar bus has mutual data
The function control device of communication, read data FIFO, write data FIFO, address FIFO device, control FIFO device,
Location generation device, the data selector MUX102 of data selector MUX101, N position of at least 3 N positions and the data of N position select
Device MUX103, two input or door Or10.Data selector MUX101 produces Cwrite10 signal and is transported in Crossbar bus
Control line Cwrite, data selector MUX102 produce Caddr10 signal be transported to the address wire in Crossbar bus
Caddr, data selector MUX103 produce the write data line Cwdata that Cwdata10 signal is transported in Crossbar bus, institute
That states that two inputs or door Or10 produce that Hready10 signal inputs to ahb bus gets out signal Hready.Meanwhile, for the ease of
Realize data to process, if the bit wide that ahb bus data bit width is L, Crossbar is M(L≤M), and define P=M/L.
From the point of view of the present invention one preferably embodiment, the address input end mouth of address producing device is din101, output
Port is dout101～dout10P, address wire Caddr of Crossbar bus be input to the din101 of address producing device
Port.Data terminal is write by what address producing device produced that address signal daddr101～daddr10P be input to address FIFO device
Mouth daddr_in101～daddr_in10P.Wherein the relation between address signal daddr101～daddr10P is,
Daddr101=Cdaddr, daddr102=Caddr+1, daddr103=Caddr+2, until daddr10P=Caddr+P.
For controlling FIFO device, include and write input end of clock mouth wclk101, read input end of clock mouth
Rclk101, controls input port writen_in101 and readen_in101, and controlling information input terminal mouth is write_in10,
Control information output mouth write_out101～write_out10P, empty full State-output port read_out101, write_
out101.Time actually used, by Crossbar bus clock TCLK input to control FIFO device write clock port
Wclk101, is inputed to control FIFO device by the bus clock HCLK of AHB and reads clock port rclk101.By function control device
Read_en101 and the write_en101 signal that cout101a and cout101b port produces is input to control input port
Writen_in101 and readen_in101.It is input to information input terminal write_ by the Cwrite signal in Crossbar bus
In10 port, to be the most also input to or input 1 port of door Or10.By read_out101 port and write_out101 end
Mouth produces Read_full101, Write_full101 and inputs to control coin101a and the coin101b end of function control device
Mouthful.By write_out101～write_out10P port produce P(P=M/L) individual control signal write101～write10P defeated
Enter the FPDP of the data selector MUX101 to P position.
Meanwhile, the address FIFO device of employing, include: write input end of clock mouth wclk102, read input end of clock mouth
Rclk102, controls input port writen_in102 and readen_in102, and address information input port is addr_in10, control
Information processed output a port ddr_out101～addr_out10P, empty full State-output port read_out102, empty completely state are defeated
Go out port write_out102.During actual motion, Crossbar bus clock TCLK input to control when writing of FIFO device
Clock port wclk102, is inputed to control FIFO device by the bus clock HCLK of AHB and reads clock port rclk102.By function control
Read_en102 and the write_en102 signal that device cout102a processed and cout102b port produce is input to control input
Mouth writen_in102 and readen_in102.It is input to information input terminal addr_ by the Caddr signal in Crossbar bus
In10 port.Read_full102, Write_full102 is produced defeated by read_out102 port and write_out102 port
Enter the control coin102a to function control device and coin102b port.Produced by addr_out101～addr_out10P port
Raw P address signal addr101～addr10P, is input to the FPDP of the data selector MUX102 of P position.
From the point of view of further, write data FIFO, include and write input end of clock mouth wclk103, read input end of clock mouth
Rclk103, controls input port writen_in103 and readen_in103, and data message input port is wdata_in10,
Control information output mouth wdata_out101～wdata_out10P, empty full State-output port read_out103, write_
out103.So, by Crossbar bus clock TCLK input to control FIFO device write clock port wclk103, by AHB
Bus clock CCLK input to control FIFO device read clock port rclk103.By function control device cout103a and
Cout103b port produce read_en103 and write_en103 signal be input to control input writen_in103 and
Readen_in103 port.It is input to information input terminal wdata_in10 port by the Cwdata signal in Crossbar bus.
Produced Read_full103, Write_full103 by read_out103 port and write_out103 port and input to function control
The control coin103a of device processed and coin103b port.P(P=M/ is produced by wdata_out101～wdata_out10P port
L) individual data-signal addr101～addr10P is input to the FPDP of data selector MUX103 of P position.
Meanwhile, read data FIFO, including writing input end of clock mouth wclk104, read input end of clock mouth rclk104,
Controlling input port writen_in104 and readen_in104, data message input port is rdata_in10, controls information
Output port rdata_out10, empty full State-output port read_out104, write_out104.The connection of each port is closed
System is: by Crossbar bus clock TCLK input to control FIFO device write clock port wclk104, by the bus of AHB
Clock HCLK inputs to control FIFO device and reads clock port rclk104.By function control device cout104a and cout104b
Read_en104 and the write_en104 signal that port produces is input to control input writen_in104 and readen_in104
Port.It is input to information input terminal rdata_in10 port by the Hrdata signal in ahb bus.By read_out104 port
Produce Read_full104, Write_full104 with write_out104 port and input to the control of function control device
Coin104a and coin104b port.Produced reading data signal Crdata10 by rdata_out10 port and be transported to Crossbar
In the read data line Hrdata of bus.
From the point of view of binding function controls device, it includes clock signal input terminal mouth, clk10.Control signal input port bag
Coin101a port, coin101b port, coin102a port, coin102b port, coin103a port, coin103b are included
Port, coin104a port, coin104b port, Hsel10 port, Hready port, Hgrant port.Control signal exports
Port include cout101a port, cout101b port, cout102a port, cout102b port, cout103a port,
Cout103b port, cout104a port, cout104b port, selo101 port, selo102 port, selo103 port.By
Crossbar bus clock TCLK inputs to function control device clock port clk10.By Crossbar bus selected signal
Csel inputs to function control device control signal input port Csel10.Merit is inputed to by ahb bus selected signal Hgrant
Device control signal input port Hgrant10 can be controlled.Function control device is inputed to by ahb bus selected signal Hready
Control signal input port Hready10.Produced by the read_out101 port and write_out101 port controlling FIFO device
Raw Read_full101, Write_full101 input to coin101a port and the coin101b port of function control device.By
The read_out102 port of address FIFO device and write_out102 port produce Read_full102, Write_full102
Signal inputs to coin102a port and the coin102b port of function control device.By the read_ writing data FIFO
Out103 port and write_out103 port produce Read_full103 signal, Write_full103 signal inputs to function
Control control coin103a port and the coin103b port of device.By read data FIFO read_out104 port and
Write_out104 port generation Read_full104 signal, Write_full104 signal input to the control of function control device
Coin104a port processed and coin104b port.Produced respectively by function control device cout101a port and cout101b port
Read_en101 signal and write_en101 signal be input to control FIFO device writen_in101 port and
Readen_in101 port.The read_en102 produced respectively by function control device cout102a port and cout102b port
Signal and write_en102 signal are input to writen_in10 the port 2 and readen_in102 port of address FIFO device.
The read_en103 signal produced respectively by function control device cout103a port and cout103b port and write_en103
Signal is input to write the writen_in103 port of data FIFO and readen_in103 port.By function control device
Read_en104 signal and write_en104 signal that cout104a port and cout104b port produce respectively are input to reading
According to writen_in104 and the readen_in104 port of FIFO device, Read_en104 signal also to input to two inputs simultaneously
Or input 2 port of door Or10.By function control device selo101 port output sel101 signal to data selector MUX101
Selection port, selo102 port output sel102 signal is to the selection end of data selector MUX102, and selo103 port is defeated
Go out the sel103 signal selection port to data selector MUX103.Exported by function control device burst10 port
Hburst10 signal is to the Hburst interface of ahb bus.By function control device burst10 port output Hburst10 signal to
The Hburst interface of ahb bus.Connect by the Hsize of function control device size10 port output Hsize10 signal to ahb bus
Mouthful.Hburst interface by function control device burst10 port output Hburst10 signal to ahb bus.By function control
Device busreq10 port output Hbusreq10 signal is to the Hbusreq interface of ahb bus.
From the point of view of the actually used situation of the present invention, function control device includes nine kinds of duties: holding state, opens
Beginning state, writes the address of data, control information transmission state, and the data message individually write sends state.The data letter write continuously
Breath transmission state, hold mode, read the address of data, control information transmission state, read the wait state of data, read data and send
State.Specifically, being converted to of each state, 1) in the standby state, enter beginning state when Hsel10 is high, otherwise
Rest on this holding state always.2) state is started.When Hgrant10 signal be low (moderator in ahb bus not give should
Bridge use bus right) when rest on this state.Judge again when Hgrant10 signal is high when will to from
Control signal Cwrite of machine operation, when Cwrite10 signal is for high (main frame sends and writes data command), NextState is for writing
Data latency state.When Cwrite10 signal is low (main frame sends reading data command), NextState is address, controls, counts
It is believed that breath sends state.3) write the address of data, control information sends state.This state enter NextState precondition be
When Hready10 is for high (being already prepared to receive data from machine), if now Read_full102=1(address FIFO device is
Empty), then enter the data message individually write and send state.If now Read_full102=1(address FIFO device non-NULL), then
Enter the data message write continuously and send state.Hready10 is low (being not ready for receiving data from machine), stops the most always
In this state.4) data message individually write sends state, and NextState is holding state.5) data message write continuously sends
State.If Hready10=1, and Read_full102=1, then next control bit according to the FIFO device of press-in control before is to read
Or write order determines NextState, if the next bit controlling FIFO device be height (write order), then jump to individually to write
Data message sends state.If the next bit controlling FIFO device is low (read command), then jump to read the address of data, control
Information sends state.If Hready10=1, and Read_full102=0, then rest on this state.If Hready10=0, no matter
What value Read_full102 is, enters hold mode.6) hold mode.If Hready10=0, no matter what two other signal is
State, all remains in this state.If Hready10=1, judge still further below, if Read_full102=0, then enter and write continuously
Data message send state.If Read_full102=1, the most still further below one layer of judgement, if the next bit controlling FIFO device is
High (write order), then the data message jumping to individually write sends state.If the next bit controlling FIFO device is low (reading life
Make), then jump to read the address of data, control information transmission state.7) read the address of data, the information that controls sends state, under
One state is for reading data wait state.8) wait state of data is read.If main frame to be read by Read_full104=0(from machine
Data store to read data FIFO), then jump to read data send state.If Read_full104=1(does not also have from machine
Have and data to be read for main frame stored to reading data FIFO), the most still rest on this state.9) read data and send state,
NextState is holding state.
From the point of view of further combining actual treatment, holding state, for initializing to Bridge, enter holding state
Four FIFO device emptied initialization (being resetted by each FIFO device), to empty the selection signal of data selector
(sel1=0, sel2=0, sel3=0), removes enable (Write_en101=0, Write_en102=of the read and write of FIFO device
0, Write_en103=0, Write_en104=0, Read_en101=0, Read_en102=0, Read_en103=0 and Read_
En104=0).2) under beginning state, OPADD FIFO device write enable signal (Write_en102=1), control FIFO dress
Put write enable signal (Write_en101=1) and write the write enable signal (Write_en103=1) of data FIFO for depositing
Storage address, control information and data message.Send Hbusreq10 signal (bus right to use application) to the arbitration in ahb bus
Device.Remaining signal still keeps the value of laststate.3) under writing the address of data, control information transmission state, address is sent
The reading of FIFO device enables signal (Read_en102=1), controls reading enable signal (Read_en101=1) of FIFO device.Its
Selection signal sel1=sel1+1, sel2=sel2+1 of middle MUX.Remaining signal still keeps the value of laststate.4) individually
Send reading enable signal (Read_en103=1) writing data FIFO under the data message transmission state write, empty address
The reading of FIFO device enables signal (Read_en102=0) and controls reading enable signal (Read_en101=0) of FIFO device.Its
Remaining signal still keeps the value of laststate.5) under the data message transmission state write continuously, data FIFO is write in transmission
Read to enable signal (Read_en103=1), and maintain the reading of address FIFO device enable signal (Read_en102=1) and control
The reading of FIFO device enables signal (Read_en101=1).Wherein the selection signal sel1=sel1+1 of MUX, sel2=sel2+1,
sel3=sel3+3.And this state in ahb bus from equipment sending data group traffic information (Hburst, Hsize
With Htrans signal).Remaining signal still keeps the value of laststate.6) in the hold state, all signals of this state keep
The value of laststate.7) reading the address of data, controlling under information transmission state, the reading sending address FIFO device enables signal
(Read_en102=1), control FIFO device reading enable signal (Read_en101=1) and reading data FIFO write enable
Signal (Write_en104=1).Remaining signal still keeps the value of laststate.8) under the wait state reading data, this shape
The all signals of state keep the value of laststate.9) under reading data transmission state, the reading enable letter reading data FIFO is sent
Number (Read_en104=1).Remaining signal still keeps the value of laststate.
The same pipeline process according to AHB address signal and data-signal, needs to increase at Corssbar to AHB
Add corresponding asynchronous FIFO device to the main frame ensureing Corssbar can access smoothly AHB from machine.This Bridge exists
Work from equipment as one in Crossbar bus, work as main equipment in ahb bus.
Signal intensity sequential chart such as Fig. 1 (equal bit wide write operation), Fig. 2 that AHB is accessed by Crossbar main frame from machine are
Different bit wide write operations, Fig. 3 are read operation.Circuit diagram as shown in Figure 4 and Figure 5, wherein Fig. 4 be double bus use same bit-width time
Special circumstances.Fig. 5 is ordinary circumstance, as it is shown in figure 5, this Bridge includes 3 devices the most altogether, is asynchronous FIFO respectively
Device device, address producing device and control device.And the data selector of 3 N positions and 1 two input or door.
Asynchronous FIFO device device is roughly the same with the FIFO device of AHB to Crossbar Bridge.Altogether by 4 FIFO
Device forms, and controls FIFO device, address FIFO device, writes data FIFO and read data FIFO.Control FIFO dress
Put and deposit main frame in Crossbar bus and send over control information Cwrite under TCLK rising edge clock triggers；Address FIFO
Device deposits, under TCLK rising edge clock triggers, address information Caddr that main frame sends over；Write data FIFO to exist
The rising edge of TCLK deposits, under triggering, the data message Cwdata that main frame sends over；Read data FIFO be used for deposit from
AHB is from the data of machine.The sequential of asynchronous FIFO device is equally by the clock of AHB and the TCLK clock after clock-generating device
Control respectively.The full state of sky in 4 FIFO device matching requirements devices can be read by control device, under facilitating and carrying out
The control of single stepping.It is emphasized that the bit wide of this data FIFO is by the less decision of bit wide.
This system the effect of address converting device be also for producing and data when two bus bits do not mate
The address matched.The figure place of three data selectors in native system also to match with the multiple of double bus.Last by counting
Address, data and the control information matched be exported to from machine according to selector group.
The bit wide writing data FIFO and reading data FIFO in native system follows the change of corresponding read bus bit wide,
The bit wide writing data FIFO device takes that position that bus bit wide is less, and it is total that the bit wide of reading data FIFO takes Crossbar
Line bit wide.And do corresponding data in bit wide higher than the interface of corresponding data FIFO device bit wide to split, low data is write
Entering the FIFO device of low level, the FIFO device that high position data write is high-order, high-order corresponding address is plus the multiple of two buses.
The most only take matched low level at the interface that bit wide is low to abandon as significance bit, a high position.Following two example can solve
Release the course of work of address producing device:
Example: Crossbar is 128 BITBUS network, and AHB is 32 BITBUS network, then the bit wide writing data FIFO takes 32, reads
The bit wide of data FIFO takes 128.Altogether write data FIFO, address FIFO device and control FIFO device for four groups.
Crossbar bit wide (definite value)/AHB bit wide (Hsize)=4
Then address producing device acts on the main frame of Crossbar and writes AHB data from machine.When writing data, is produced from address
Generating apparatus automatically can add 4 carries out the filling of corresponding high byte.Entered by the MUX of three 2 when data output is to ahb bus
Row switching output.
The FIFO device reading data then will read data FIFO, by high 16 from the data write that AHB reads to come
Automatically zero filling, corresponding address information does not changes.
Example: if Crossbar is 16 BITBUS network, AHB is 32 BITBUS network, writes the bit wide of data FIFO the most accordingly
Taking 32, reading data FIFO is 16.
Writing data FIFO the data uploaded from Crossbar bus automatically to be stored to low level, high-order filling is complete
Zero.
Read data FIFO then to need to carry out data fractionation, store low 16.The most here only have low 16
Effectively, high-order invalid, automatically abandon.
Owing to address bit is to be issued from machine by main frame, so address remains the ground sended over by main frame when reading data
Location, will not change.
The writing of the corresponding FIFO device of device major control that control of native system enables and reads to enable, and completes and main equipment
Communication task, as shown in Figure 6: first, whole system receive by the address of main frame through decoding after selected signal
Csel, begin preparing for receiving to the right to use of ahb bus moderator application bus after obtaining the right to use by arbitration
The signal of Crossbar bus.Bridge can TCLK rising edge receive sended over by main frame address, control information and
Data message.Write information into the FIFO device of correspondence, the most also control information is sent to control device.Control device inspection
The order that survey main frame sends is to read or write.
If be detected that be write order, then signal is made to produce Cready=1(according to corresponding combinational logic the most accurate from machine
The signal got ready) give main frame, simultaneously enter address and send state.At HCLK rising edge synch transmission address control information to AHB
Bus.The most then detect this address FIFO device whether non-NULL, if FIFO device non-NULL, then enter burst data and send data shape
State；If address FIFO device sky, enter forms data and send state.
In forms data transmission state, to detect and get out signal Hready from what machine return came, when signal is high, then exist
Next HCLK rising edge sends data；When Hready signal is low, then enter wait state, until detecting that HCLK signal is
High level sends data to ahb bus again.Individual data determines next state according to Csel signal after transmitting, and works as Csel
=1, show to also need to continue to transmit, return to beginning state, prepare transmission next time；Work as Csel=0, show the end of transmission, return
Carry out holding state.
The transmission of burst data is caused by two buses are not mated, and now represents that the figure place of Crossbar bus is higher than
The figure place of ahb bus, so the data fractionation to be carried out when storing the data of Corssbar, address producing device to produce simultaneously
The address information matched.After entering this state, to detect and get out signal Hready, when signal is from what machine return came
Height, then send data at next HCLK rising edge；When Hready signal is low, then enter wait state, until detecting
HCLK signal is that high level sends data to ahb bus again.The address of next data is also sent while sending data
Information.Namely the rising edge at next HCLK clock sends the address information of next data, next data control simultaneously
Information processed and the data message of this secondary transmission.Hburst signal to be passed through, Hsize signal and Htrans signal are informed
Information from this group traffic of machine.The full state of sky according to address FIFO device and the height of Hwrite signal after this end of transmission
The low state judging that the next one is to be entered.When address FIFO device is empty and be write order (Hwrite=1), then enter single word
Joint number is according to the state of transmission；When address FIFO device non-NULL and be write order (Hwrite=1), then enter burst data and send state.
And when Hwrite=0 being detected, enter and read data mode.
If be detected that be read command, then making signal produce Cready=0(according to corresponding combinational logic does not has standard from machine
The signal got ready) give main frame, at this moment enter address and send state, same meeting is synchronized transmission address and control under HCLK clock
Information is to ahb bus.Subsequently into wait state, at this moment controller can detect the write pointer reading data FIFO, works as detection
Variation to write pointer is laggard studies in data mode, and the data now writing FIFO device are sent extremely by Crdata port
In Crossbar bus, and transmission gets out signal (Cready=1) simultaneously.If the data being now transmitted through from AHB are higher than
Crossbar bus, the most high-order invalid, so time need not detection and read the full state of sky of data FIFO, direct basis
Csel signal determines next state, works as Csel=1, shows to also need to continue to transmit, returns to start condition adjudgement read-write, prepare
Transmission next time；Work as Csel=0, show the end of transmission, return to holding state.
By above-mentioned character express it can be seen that after using the present invention, by ahb bus, fill with each function FIFO
Put and match, constitute effective connection-bridge structure, it is achieved main equipment initiating from equipment in ahb bus in Crossbar bus
Read/write operation, make the data can be without communicating of makeing mistakes while meeting the respective timing sequence specification of both sides bus.
Claims (10)
1.Crossbar bus and the data Bridge equipment of ahb bus, include apparatus body, it is characterised in that: described
It is provided with Crossbar bus in apparatus body, Crossbar bus connects and has the function of mutual data communication to control dress
Put, read data FIFO, write data FIFO, address FIFO device, control FIFO device, address producing device, at least 3
The data selector MUX101 of individual N position, data selector MUX102 and data selector MUX103, two input or doors；If AHB is total
Line data bit width be the bit wide of L, Crossbar be M, L less than or equal to M, and define P=M/L.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The address input end mouth of the address producing device stated is din101, output port is dout101 ~ dout10P, total by Crossbar
Address wire Caddr of line is input to the din101 port of address producing device；Address signal is produced by address producing device
What daddr101 ~ daddr10P was input to address FIFO device writes FPDP daddr_in101 ~ daddr_in10P；Wherein
Relation between location signal daddr101 ~ daddr10P is, daddr101=Cdaddr, daddr102=Caddr+1, daddr103
=Caddr+2, until daddr10P=Caddr+P.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The control FIFO device stated, includes and writes input end of clock mouth wclk101, reads input end of clock mouth rclk101, controls input
Mouth writen_in101 and readen_in101, controlling information input terminal mouth is write_in10, controls information output mouth
Write_out101 ~ write_out10P, empty full State-output port read_out101, write_out101, by Crossbar
Bus clock TCLK input to control FIFO device write clock port wclk101, by the bus clock HCLK of AHB input to control
FIFO device processed reads clock port rclk101；The read_ produced by function control device cout101a and cout101b port
En101 and write_en101 signal is input to control input port writen_in101 and readen_in101；By Crossbar
Cwrite signal in bus is input to information input terminal write_in10 port, to be the most also input to or the input of door Or10
1 port；Produced Read_full101, Write_full101 by read_out101 port and write_out101 port to input to
The control coin101a of function control device and coin101b port；Produced by write_out101 ~ write_out10P port
P control signal write101 ~ write10P is input to the FPDP of the data selector MUX101 of P position.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The address FIFO device stated, includes: write input end of clock mouth wclk102, reads input end of clock mouth rclk102, controls input
Port writen_in102 and readen_in102, address information input port is addr_in10, controls information output a port
Ddr_out101 ~ addr_out10P, empty full State-output port read_out102, empty full State-output port write_
out102；Clock port wclk102 is write, total by AHB by what Crossbar bus clock TCLK inputed to control FIFO device
Line clock HCLK inputs to control FIFO device and reads clock port rclk102；By function control device cout102a and
Cout102b port produce read_en102 and write_en102 signal be input to control input port writen_in102 and
readen_in102；It is input to information input terminal addr_in10 port by the Caddr signal in Crossbar bus；By read_
Out102 port and write_out102 port produce Read_full102, Write_full102 and input to function control device
Control coin102a and coin102b port；P address signal is produced by addr_out101 ~ addr_out10P port
Addr101 ~ addr10P, is input to the FPDP of the data selector MUX102 of P position.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
That states writes data FIFO, includes and writes input end of clock mouth wclk103, reads input end of clock mouth rclk103, controls input
Port writen_in103 and readen_in103, data message input port is wdata_in10, controls information output mouth
Wdata_out101 ~ wdata_out10P, empty full State-output port read_out103, write_out103, by Crossbar
Bus clock TCLK input to control FIFO device write clock port wclk103, by the bus clock CCLK of AHB input to control
FIFO device processed reads clock port rclk103；The read_ produced by function control device cout103a and cout103b port
En103 and write_en103 signal is input to control input writen_in103 and readen_in103 port；By Crossbar
Cwdata signal in bus is input to information input terminal wdata_in10 port；By read_out103 port and write_
Out103 port produce Read_full103, Write_full103 input to function control device control coin103a and
Coin103b port；P data-signal addr101 ~ addr10P is produced by wdata_out101 ~ wdata_out10P port
It is input to the FPDP of the data selector MUX103 of P position.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The reading data FIFO stated, including writing input end of clock mouth wclk104, reads input end of clock mouth rclk104, controls input
Mouth writen_in104 and readen_in104, data message input port is rdata_in10, controls information output mouth
Rdata_out10, empty full State-output port read_out104, write_out104；The annexation of port: by
Crossbar bus clock TCLK input to control FIFO device write clock port wclk104, by the bus clock HCLK of AHB
Input to control FIFO device and read clock port rclk104；Produced by function control device cout104a and cout104b port
Read_en104 and write_en104 signal be input to control input writen_in104 and readen_in104 port；By
Hrdata signal in ahb bus is input to information input terminal rdata_in10 port；By read_out104 port and write_
Out104 port produce Read_full104, Write_full104 input to function control device control coin104a and
Coin104b port；Produced reading data signal Crdata10 by rdata_out10 port and be transported to the reading of Crossbar bus
According in line Hrdata.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The function control device stated, including, clock signal input terminal mouth: clk10；Control signal input port includes coin101a end
Mouth, coin101b port, coin102a port, coin102b port, coin103a port, coin103b port, coin104a
Port, coin104b port, Hsel10 port, Hready port, Hgrant port；Control signal output port includes
Cout101a port, cout101b port, cout102a port, cout102b port, cout103a port, cout103b end
Mouth, cout104a port, cout104b port, selo101 port, selo102 port, selo103 port；Total by Crossbar
Line clock TCLK inputs to function control device clock port clk10；Merit is inputed to by Crossbar bus selected signal Csel
Device control signal input port Csel10 can be controlled；Function control device control is inputed to by ahb bus selected signal Hgrant
Signal input port Hgrant10 processed；The input of function control device control signal is inputed to by ahb bus selected signal Hready
Port Hready10；Read_ is produced by the read_out101 port and write_out101 port controlling FIFO device
Full101, Write_full101 input to coin101a port and the coin101b port of function control device；By address
The read_out102 port of FIFO device and write_out102 port produce Read_full102, Write_full102 signal
Input to coin102a port and the coin102b port of function control device；By the read_out103 writing data FIFO
Port and write_out103 port produce Read_full103 signal, Write_full103 signal inputs to function and controls dress
The control coin103a port put and coin103b port；By the read_out104 port and the write_ that read data FIFO
Out104 port generation Read_full104 signal, Write_full104 signal input to the control of function control device
Coin104a port and coin104b port；Produced respectively by function control device cout101a port and cout101b port
Read_en101 signal and write_en101 signal are input to control writen_in101 port and the readen_ of FIFO device
In101 port；The read_en102 signal produced respectively by function control device cout102a port and cout102b port and
Write_en102 signal is input to writen_in10 the port 2 and readen_in102 port of address FIFO device；By function
Read_en103 signal and write_en103 signal that control device cout103a port and cout103b port produce respectively are defeated
Enter to writen_in103 port and the readen_in103 port writing data FIFO；By function control device cout104a
Read_en104 signal and write_en104 signal that port and cout104b port produce respectively are input to read data FIFO dress
Writen_in104 and the readen_in104 port put, Read_en104 signal also to input to two inputs or door Or10 simultaneously
Input 2 port；Selection end by function control device selo101 port output sel101 signal to data selector MUX101
Mouthful, the selection end of selo102 port output sel102 signal to data selector MUX102, selo103 port output sel103
Signal is to the selection port of data selector MUX103；By function control device burst10 port output Hburst10 signal to
The Hburst interface of ahb bus；By function control device burst10 port output Hburst10 signal to ahb bus
Hburst interface；Hsize interface by function control device size10 port output Hsize10 signal to ahb bus；By function
Control the device burst10 port output Hburst10 signal Hburst interface to ahb bus；By function control device
Busreq10 port output Hbusreq10 signal is to the Hbusreq interface of ahb bus.
Crossbar bus the most according to claim 7 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The function control device stated includes nine kinds of duties, holding state, starts state, writes the address of data, the transmission of control information
State, the data message individually write sends state；The data message write continuously sends state, hold mode, read data address,
Control information sends state, reads the wait state of data, reads data and sends state；Being converted to of each state described, 1) treating
Under machine state, enter beginning state when Hsel10 is high, rest on this holding state the most always；2) state is started；When
Hgrant10 signal rests on this state when of being low；Judge again to operate from machine when Hgrant10 signal is high when
Control signal Cwrite, when Cwrite10 signal is high, NextState is for writing data latency state；When Cwrite10 signal
For time low, NextState is address, control, data message transmission state；3) write the address of data, control information sends state；
It is when Hready10 is high that this state enters NextState precondition, if now Read_full102=0, then enters individually
The data message write sends state；If now Read_full102=1, then enter the data message write continuously and send state；
Hready10 is low, rests on this state the most always；4) data message individually write sends state, and NextState is standby shape
State；5) data message write continuously sends state；If Hready10=1, and Read_full102=1, then according to being pressed into control before
Next control bit of FIFO device processed be read or write order is to determine NextState, if control FIFO device next bit be
Height, then the data message jumping to individually write sends state；If the next bit controlling FIFO device is low, then jump to read data
Address, control information send state；If Hready10=1, and Read_full102=0, then rest on this state；If
Hready10=0, no matter what value Read_full102 is, enters hold mode；6) hold mode；If Hready10=0, the most separately
What state outer two signals are, all remain in this state；If Hready10=1, judge still further below, if Read_full102=
0, then enter the data message write continuously and send state；If Read_full102=1, the most still further below one layer of judgement, if controlling FIFO
The next bit of device is high, then the data message jumping to individually write sends state；If the next bit controlling FIFO device is low,
Then jump to read the address of data, control information sends state；7) read the address of data, the information that controls sends state, next shape
State is for reading data wait state；8) wait state of data is read；If Read_full104=0, then jump to read data and send shape
State；If Read_full104=1, the most still rest on this state；9) reading data and send state, NextState is holding state.
Crossbar bus the most according to claim 8 and the data Bridge equipment of ahb bus, it is characterised in that: 1)
Holding state, for initializing to Bridge, enters holding state and four FIFO device is emptied initialization, empty
The selection signal of data selector, removes the enable of the read and write of FIFO device；2) under beginning state, OPADD FIFO fills
Put write enable signal, control FIFO device write enable signal and write the write enable signal of data FIFO for store address,
Control information and data message；Send Hbusreq10 signal to the moderator in ahb bus；Remaining signal still keeps upper one
The value of state；3) under writing the address of data, control information transmission state, the reading sending address FIFO device enables signal, control
The reading of FIFO device processed enables signal；Wherein selection signal sel1=sel1+1, sel2=sel2+1 of MUX；Remaining signal is still
Keep the value of laststate；4) under the data message transmission state individually write, the reading enable letter of data FIFO is write in transmission
Number, the reading reading to enable signal and control FIFO device emptying address FIFO device enables signal；On remaining signal still keeps
The value of one state；5) under the data message transmission state write continuously, the reading enable signal of data FIFO is write in transmission, and ties up
The reading reading to enable signal and control FIFO device holding address FIFO device enables signal；The wherein selection signal sel1=of MUX
sel1+1、sel2=sel2+1、sel3=sel3+3；And this state passing in groups from equipment sending data in ahb bus
Transmission information；Remaining signal still keeps the value of laststate；6) in the hold state, all signals of this state keep laststate
Value；7) reading the address of data, controlling under information transmission state, the reading sending address FIFO device enables signal, control
The write enable signal reading to enable signal with read data FIFO of FIFO device；Remaining signal still keeps laststate
Value；8) under the wait state reading data, all signals of this state keep the value of laststate；9) data transmission state is being read
Under, send the reading enable signal reading data FIFO；Remaining signal still keeps the value of laststate.
Crossbar bus the most according to claim 1 and the data Bridge equipment of ahb bus, it is characterised in that: institute
The data selector MUX101 stated produces the control line Cwrite that Cwrite10 signal is transported in Crossbar bus, and data are selected
Select device MUX102 generation Caddr10 signal and be transported to address wire Caddr in Crossbar bus, data selector MUX103
Producing the write data line Cwdata that Cwdata10 signal is transported in Crossbar bus, described two inputs or door produce
What Hready10 signal inputed to ahb bus gets out signal Hready.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310465421.7A CN103744818B (en) | 2013-10-08 | 2013-10-08 | Crossbar bus and the data Bridge equipment of ahb bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310465421.7A CN103744818B (en) | 2013-10-08 | 2013-10-08 | Crossbar bus and the data Bridge equipment of ahb bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103744818A CN103744818A (en) | 2014-04-23 |
| CN103744818B true CN103744818B (en) | 2016-09-07 |
Family
ID=50501836
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310465421.7A Expired - Fee Related CN103744818B (en) | 2013-10-08 | 2013-10-08 | Crossbar bus and the data Bridge equipment of ahb bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103744818B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115913816B (en) * | 2022-12-16 | 2024-05-24 | 无锡芯光互连技术研究院有限公司 | Communication conversion device and method for communication between master equipment and slave equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169470A (en) * | 2010-02-27 | 2011-08-31 | 比亚迪股份有限公司 | Conversion bridge from advanced high performance bus (AHB) to basic virtual component interface (BVCI) |
| CN103198043A (en) * | 2013-01-24 | 2013-07-10 | 杭州中科微电子有限公司 | Improved AHB-to-APB bus bridge and control method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7581076B2 (en) * | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
| KR101841173B1 (en) * | 2010-12-17 | 2018-03-23 | 삼성전자주식회사 | Device and Method for Memory Interleaving based on a reorder buffer |
-
2013
- 2013-10-08 CN CN201310465421.7A patent/CN103744818B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169470A (en) * | 2010-02-27 | 2011-08-31 | 比亚迪股份有限公司 | Conversion bridge from advanced high performance bus (AHB) to basic virtual component interface (BVCI) |
| CN103198043A (en) * | 2013-01-24 | 2013-07-10 | 杭州中科微电子有限公司 | Improved AHB-to-APB bus bridge and control method thereof |
Non-Patent Citations (2)
| Title |
|---|
| AHB-PCI桥的设计及其验证方法;王晨旭等;《微处理机》;20040229(第1期);第8-13页 * |
| 基于FPGA的OPB_AHB总线桥接器的设计;段小康等;《微计算机应用》;20091231;第25卷(第5-2期);第138-162页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103744818A (en) | 2014-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8352774B2 (en) | Inter-clock domain data transfer FIFO circuit | |
| CN105117360B (en) | Interface signal replay shooting method based on FPGA | |
| CN103415777B (en) | For carry out function and structure test and debugging based on functional structure test controller | |
| CN101770437B (en) | Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory | |
| CN103198043A (en) | Improved AHB-to-APB bus bridge and control method thereof | |
| CN110309526A (en) | For the configurable periphery interconnection from endpoint circuit | |
| CN106294239A (en) | A kind of peripheral bus APB bus bridge | |
| CN102169470B (en) | Conversion bridge from advanced high performance bus (AHB) to basic virtual component interface (BVCI) | |
| CN104915303A (en) | High-speed digital I/O system based on PXIe bus | |
| CN106469127B (en) | A kind of data access device and method | |
| CN105912492A (en) | Extension method of AXI interconnected bus | |
| CN103730149A (en) | Read write control circuit of dual-ported memory | |
| KR20120040535A (en) | Bus system and operating method thereof | |
| CN104615386B (en) | The outer caching device of one seed nucleus | |
| CN103748837A (en) | Method for data throughput improvement in open core protocol based interconnection networks using dynamically selectable redundant shared link physical paths | |
| CN107908587A (en) | Real-time data acquisition transmitting device based on USB3.0 | |
| CN104657297B (en) | Computing device extends system and extended method | |
| CN102023947A (en) | Direct interface method of institute of electrical and electronic engineers (IEEE) 1394 bus and high-speed intelligent unified bus | |
| CN103744818B (en) | Crossbar bus and the data Bridge equipment of ahb bus | |
| CN101213558A (en) | Integrated circuit and method of securing access to an on-chip memory | |
| CN103761208B (en) | Communication conversion bridge equipment between AHB bus and Crossbar bus | |
| US20070283077A1 (en) | Memory and Memory Communication System | |
| CN106603442B (en) | A kind of cross clock domain high-speed data communication interface circuit of network-on-chip | |
| CN218068843U (en) | Bridging circuit structure for converting AXI master port into APB slave port and SOC system | |
| CN103744817B (en) | For Avalon bus to the communication Bridge equipment of Crossbar bus and communication conversion method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SUZHOU ACCESO COMMUNICATION TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SUZHOU ACCESO ELECTRONIC TECHNOLOGIES CO., LTD. Effective date: 20140707 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140707 Address after: 215021, Suzhou Jiangsu Industrial Park, Lou Lu, new Su Yuan District, convenient center, public building supporting the use of two floor Applicant after: Suzhou think Communication Technology Co., Ltd. Address before: 215021 two stage of international science and Technology Park, Suzhou Industrial Park, Jiangsu, A309 Applicant before: SUZHOU AISISUO ELECTRONIC SCIENCE & TECHNOLOGY CO., LTD. |
|
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Dong Lan Inventor after: Zhang He Inventor after: Zhang Ke Inventor before: Wu Di Inventor before: Chen Xin Inventor before: Zhang Ke |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: WU DI CHEN XIN ZHANG KE TO: DONG LAN ZHANG HE ZHANG KE |
|
| C53 | Correction of patent for invention or patent application | ||
| CB02 | Change of applicant information |
Address after: 215021, Suzhou Jiangsu Industrial Park, Lou Lu, new Su Yuan District, convenient center, public building supporting the use of two floor Applicant after: Suzhou wisdom spectrum Electronic Technology Co., Ltd. Address before: 215021, Suzhou Jiangsu Industrial Park, Lou Lu, new Su Yuan District, convenient center, public building supporting the use of two floor Applicant before: Suzhou think Communication Technology Co., Ltd. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: SUZHOU ACCESO COMMUNICATION TECHNOLOGY CO., LTD. TO: SUZHOU ZHIHUIPU ELECTRONICS TECHNOLOGY CO., LTD. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160907 Termination date: 20181008 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |