CN103744804A - Anti-interference method and system while performing communication interface software simulation - Google Patents
Anti-interference method and system while performing communication interface software simulation Download PDFInfo
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- CN103744804A CN103744804A CN201310747010.7A CN201310747010A CN103744804A CN 103744804 A CN103744804 A CN 103744804A CN 201310747010 A CN201310747010 A CN 201310747010A CN 103744804 A CN103744804 A CN 103744804A
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Abstract
The invention provides an anti-interference method and system while performing communication interface software simulation. The method comprises the following steps: the level of an external signal is read and is compared with a triggered level during the period which is less than 1 bit time, after the triggered interruption of a simulate communication interface is triggered by the external signal; if the level of the external signal is different from the trigged level, the external signal is not processed, otherwise, the external signal is further processed. According to the method, the error rate of the received data can be greatly reduced when the software simulation communication interface is performed, the occupation of the wrong data to system resources can be prevented, and the problem that the system resources are greatly occupied when software simulate interface signals are interfered can be solved.
Description
Technical field
The present invention relates to communication technical field, relate in particular to one jamming-proof method and system when software simulation communication interface.
Background technology
Existing interface signal of a great variety, as serial ports, PS2, infrared, parallel port etc.Existing hardware system is also integrated with various interface more and more, but may be because hardware system does not have this interface under a lot of occasion, is likely also the deficiency of the interface quantity of hardware system, usually needs docking port to carry out software simulation.The interface signal of software simulation is generally low speed signal, but low speed signal is a relative concept, do not have clear and definite definition, as long as system simulation interface signal can not take too much system resource, this interface signal is low speed signal for system comparatively speaking.With the ability of present system, the interface signal that can simulate includes but not limited to following signal: serial ports, PS2, infrared, I2C, parallel port, SPI etc.
Here take rs 232 serial interface signal as example, serial ports is very general in Industry Control, and tends to connect opertaing device by very long line, and length can be tens meters.Owing to may there being the interference of environment, while receiving data, may receive wrong data.If serial ports is to adopt the method for hardware to realize, such as one with the IC of serial ports, that jamming-proof design has just realized in IC inside, does not need program to do too many work.If but serial ports is software simulation, that program will think it is a correct signal by mistake, and receives this data.Conventionally all can in the data of serial ports, increase fixing agreement during program design, such as frame head, a centre are data, ending adds one and verification etc. again.These are that judgement is done to obtain on upper strata, and wrong data are weeded out.Bottom, when receiving data, generally adopts the mode of interrupting, and interruption can be edging trigger, can be also level triggers.Adopt the method for existing software simulation, once there be interference, bottom will constantly read data and upload, but these data are invalid in fact, waste undoubtedly system resource, thereby has influence on the processing of system to other events.
Summary of the invention
The technical problem to be solved in the present invention, is to provide one jamming-proof method and system when software simulation communication interface, solves the existing problem that has greatly taken system resource when software simulation interface signal is interfered.
The present invention is achieved in that
One jamming-proof method when software simulation communication interface, comprise the steps: after the triggering of analogue communication interface is interrupted being triggered by external signal, being less than in the time of 1bit time, read the level of external signal, level during with triggering compares, if the level of external signal from trigger time level different, do not process external signal, otherwise external signal be further processed.
Further, the level of described each external signal is read and the number of times that compares of level when triggering is secondary or more than secondary.
Further, between every twice adjacent level that reads external signal the step that compares of level when triggering, interlude equates.
Further, the described level that reads external signal of adjacent twice, the step interlude that the level during with triggering compares is integer/mono-of 1bit time.
Further, the triggering of described analogue communication interface is interrupted for edge triggered interruption or level triggers.
Further, the trigger condition of the described level that reads external signal the step that compares of level when triggering is timer down trigger or the mode that adopts inquiry timer.
Further, described communication interface be serial ports, PS2, infrared, I2C, parallel port or SPI one of them.
And the present invention also provide based on the above method a kind of when software simulation communication interface jamming-proof system, comprise as lower module:
External signal triggers and read module: after interrupting being triggered by external signal for the triggering when analogue communication interface, being less than in the time of 1bit time, read the level of external signal;
Relatively judge module of external signal: for the level when triggering compares by the level of external signal, if the level of the level of external signal during with triggering is different, does not process external signal, otherwise external signal is further processed.
Further, the level of described each external signal is read and the number of times that compares of level when triggering is secondary or more than secondary.
Further, between every twice adjacent level that reads external signal the step that compares of level when triggering, interlude equates.
Further, the described level that reads external signal of adjacent twice, the step interlude that the level during with triggering compares is integer/mono-of 1bit time.
Further, the triggering of described analogue communication interface is interrupted for edge triggered interruption or level triggers.
Further, the trigger condition of the described level that reads external signal the step that compares of level when triggering is timer down trigger or the mode that adopts inquiry timer.
Further, described communication interface be serial ports, PS2, infrared, I2C, parallel port or SPI one of them.
Tool of the present invention has the following advantages: the present invention receives the error rate of data in the time of can greatly reducing software simulation communication interface, improves the product stability that uses software simulation communication interface, reduces the dependence of product to environment.Meanwhile, because these expansion interfaces are low speed, data volume itself is smaller, anti-tampering by the present invention after, can make the system (host computer often) can more rational Resources allocation.
Accompanying drawing explanation
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the schematic diagram of the Wave data of processing of the present invention.
Embodiment
Refer to shown in Fig. 1, below will with software simulation serial port, the present invention is described in detail.
As shown in Figure 1, middle waveform is serial ports waveform, and according to serial ports coding rule, low level is digital signaling zero, and high level is digital signal 1, and what 0 in Fig. 1 and 1 represented is the corresponding digital signal of wave level.Waveform a in Fig. 1 is a bit of impulse disturbances.
According to the method for existing software simulation communication interface: what the reception of external signal was used is that negative edge triggers and interrupts, after the waveform edge of the external signal in communication interface changes with regard to reading out data, will read data 0x59 and 0xFF(serial port protocol is: low level is front, high-order rear, 0 starts, and 1 is position of rest, middle 8 bit data), 0xFF is that waveform a disturbs and the data that read, and 0xFF is unwanted data.If 0xFF is further processed to data, can occupying system resources, even cause system to make mistakes.
Below use of the present invention a kind of when software simulation communication interface jamming-proof method the wave analysis of Fig. 1 is elaborated.Existing software simulation communication interface, in order to reduce the taking of system resource, is all with interrupting triggering the collection to external signal.The type of interrupting comprises edge triggered interruption and level triggered interrupts, can select according to the actual needs.First the wave form varies of external signal can trigger the interruption of simulation communication interface, take negative edge triggering as example, low level waveform b in Fig. 1 can trigger interruption, and the level while triggering is low level, and by external signal, (waveform b) triggers in the triggering of analogue communication interface interruption.
, after the triggering of analogue communication interface is interrupted being triggered by external signal, being less than in the time of 1bit time, read the level of external signal, the level during with triggering compares.The time that bit is shared 1bit time (1 bit time) i.e., because the time of a normal waveform more than the 1bit time, the variation of level also may occur, if be more than or equal to the 1bit time in the ensuing relatively time of judgement, can produce wrong judgement, can cause the loss of data.The condition that arranges that level during triggering can the triggering by communication interface interrupts judge and learn (as be set to rising edge and trigger, the saltus step meeting of only having low level to arrive high level produces to be interrupted, and level during triggering (interruption) is high level); Or the level that reads at once external signal after being triggered by interruption can be learnt the level while triggering.The triggering that the level that reads external signal in this method can be worked as analogue communication interface is less than arbitrarily the 1bit time after interrupting being triggered by external signal.Because the waveform general persistence disturbing is shorter, can use a relatively long time, as the 0.5bit time, the level that normal waveform b (read in time point Fig. 1 shown in c) after the 0.5bit time reads is low level, level during with triggering is identical, can be further processed external signal, think that this waveform b is a start signal, thereby read data 0x59; And interference waveform a after the 0.5bit time (read in time point Fig. 1 shown in d) what read is high level, the level when triggering is different, does not process, and can not read 0xFF.Use this method to avoid reading 0xFF, system need not be processed 0xFF, has saved the resource of system.
In order more exactly waveform to be read, relatively and judgement, the number of times that the level of each external signal is read and the level when triggering compares is secondary or more than secondary.Carry out more than twice judgement, the judgement of twice as the judgement at the time point g place after the judgement at the time point e place after waveform b in Fig. 1 triggers and time point f place and waveform a triggering and time point h place, once have, to determine the level that reads different from the level triggering, think that triggering this waveform interrupting is interference wave, does not process it.
The level that reads external signal of adjacent twice also compares and the time interval of judgement can arbitrarily arrange, for the ease of reading and comparing, preferably, between every twice adjacent level that reads external signal the step that compares of level when triggering, interlude equates.It is the time interval that in Fig. 1, the time interval at e place and c place equals c place and f place.Further, the level that reads external signal of adjacent twice, the step interlude that the level during with triggering compares is integer/mono-of 1bit time.As the time interval at the e place in Fig. 1 and c place can be made as 1/4th of the 1bit time, i.e. the 0.25bit time, such time that is arranged so that distributes more even, and judged result is more accurate.
For the level that reads external signal, the trigger condition of the step that the level during with triggering compares can adopt mode or the timer down trigger mode of inquiry timer.The time point that down trigger mode makes to carry out above-mentioned step is very accurate.
Although the situation that is only serial ports to communication interface above describes, the situation that those skilled in the art can be also PS2, infrared, I2C, parallel port or SPI to communication interface according to above method is carried out anti-tampering processing.
And the present invention also provide based on the above method a kind of when software simulation communication interface jamming-proof system, comprise as lower module:
External signal triggers and read module: after interrupting being triggered by external signal for the triggering when analogue communication interface, being less than in the time of 1bit time, read the level of external signal;
Relatively judge module of external signal: for the level when triggering compares by the level of external signal, if the level of the level of external signal during with triggering is different, does not process external signal, otherwise external signal is further processed.
Further, described communication interface is serial ports, PS2, infrared, I2C, parallel port or SPI.
To sum up, the present invention judges and rejects when interference waveform produces, and can reject most wrong waveforms, avoids wrong waveform to produce wrong data and causes the waste of upper procedure resource.
The foregoing is only embodiments of the invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes instructions of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (14)
1. a jamming-proof method when software simulation communication interface, it is characterized in that: comprise the steps: after the triggering of analogue communication interface is interrupted being triggered by external signal, being less than in the time of 1bit time, read the level of external signal, level during with triggering compares, if the level of external signal from trigger time level different, do not process external signal, otherwise external signal be further processed.
2. one according to claim 1 jamming-proof method when software simulation communication interface, is characterized in that: the level of described each external signal is read and the number of times that compares of level when triggering is secondary or more than secondary.
3. one according to claim 2 jamming-proof method when software simulation communication interface, is characterized in that: between every twice adjacent level that reads external signal the step that compares of level when triggering, interlude equates.
4. one according to claim 3 jamming-proof method when software simulation communication interface, it is characterized in that: the described level that reads external signal of adjacent twice, the step interlude that the level during with triggering compares is integer/mono-of 1bit time.
5. one according to claim 1 jamming-proof method when software simulation communication interface, is characterized in that: the triggering of described analogue communication interface is interrupted for edge triggered interruption or level triggers.
6. one according to claim 1 jamming-proof method when software simulation communication interface, is characterized in that: the trigger condition of the described level that reads external signal the step that compares of level when triggering is timer down trigger or the mode that adopts inquiry timer.
7. according to the arbitrary described one of claim 1 to 6 jamming-proof method when the software simulation communication interface, it is characterized in that: described communication interface be serial ports, PS2, infrared, I2C, parallel port or SPI one of them.
8. a jamming-proof system when software simulation communication interface, is characterized in that: comprise as lower module:
External signal triggers and read module: after interrupting being triggered by external signal for the triggering when analogue communication interface, being less than in the time of 1bit time, read the level of external signal;
Relatively judge module of external signal: for the level when triggering compares by the level of external signal, if the level of the level of external signal during with triggering is different, does not process external signal, otherwise external signal is further processed.
9. one according to claim 8 jamming-proof system when software simulation communication interface, is characterized in that: the level of described each external signal is read and the number of times that compares of level when triggering is secondary or more than secondary.
10. one according to claim 9 jamming-proof system when software simulation communication interface, is characterized in that: between every twice adjacent level that reads external signal the step that compares of level when triggering, interlude equates.
11. one according to claim 10 are jamming-proof system when software simulation communication interface, it is characterized in that: the described level that reads external signal of adjacent twice, the step interlude that the level during with triggering compares is integer/mono-of 1bit time.
12. one according to claim 8 are jamming-proof system when software simulation communication interface, it is characterized in that: the triggering of described analogue communication interface is interrupted for edge triggered interruption or level triggers.
13. one according to claim 8 are jamming-proof system when software simulation communication interface, it is characterized in that: the trigger condition of the described level that reads external signal the step that compares of level when triggering is timer down trigger or the mode that adopts inquiry timer.
14. according to Claim 8-13 arbitrary described one jamming-proof systems when software simulation communication interface, is characterized in that: described communication interface be serial ports, PS2, infrared, I2C, parallel port or SPI one of them.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105183686A (en) * | 2015-07-30 | 2015-12-23 | 深圳市振邦智能科技有限公司 | Method and apparatus for starting simulated serial port communication |
| CN105183686B (en) * | 2015-07-30 | 2018-08-31 | 深圳市振邦智能科技股份有限公司 | A kind of method and apparatus starting simulative serial port communication |
| CN111045476A (en) * | 2019-12-18 | 2020-04-21 | 湖南国科微电子股份有限公司 | Time sequence waveform control method, system, equipment and medium under multi-core CPU system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100223505A1 (en) * | 2009-03-02 | 2010-09-02 | International Business Machines Corporation | Software table walk during test verification of a simulated densely threaded network on a chip |
| CN102546843A (en) * | 2012-01-17 | 2012-07-04 | 厦门雅迅网络股份有限公司 | Method for achieving UART (universal asynchronous receiver/transmitter) communication interfaces through software simulation |
-
2013
- 2013-12-30 CN CN201310747010.7A patent/CN103744804A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100223505A1 (en) * | 2009-03-02 | 2010-09-02 | International Business Machines Corporation | Software table walk during test verification of a simulated densely threaded network on a chip |
| CN102546843A (en) * | 2012-01-17 | 2012-07-04 | 厦门雅迅网络股份有限公司 | Method for achieving UART (universal asynchronous receiver/transmitter) communication interfaces through software simulation |
Non-Patent Citations (1)
| Title |
|---|
| 佘新平等: "基于FPGA的不同波特率串口通信系统设计", 《石油仪器》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105183686A (en) * | 2015-07-30 | 2015-12-23 | 深圳市振邦智能科技有限公司 | Method and apparatus for starting simulated serial port communication |
| CN105183686B (en) * | 2015-07-30 | 2018-08-31 | 深圳市振邦智能科技股份有限公司 | A kind of method and apparatus starting simulative serial port communication |
| CN111045476A (en) * | 2019-12-18 | 2020-04-21 | 湖南国科微电子股份有限公司 | Time sequence waveform control method, system, equipment and medium under multi-core CPU system |
| CN111045476B (en) * | 2019-12-18 | 2021-07-27 | 湖南国科微电子股份有限公司 | Time sequence waveform control method, system, equipment and medium under multi-core CPU system |
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Application publication date: 20140423 |