CN103731317A - Method and device for PCIE address mapping detection - Google Patents
Method and device for PCIE address mapping detection Download PDFInfo
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Abstract
The embodiment of the invention provides a method and device for PCIE address mapping detection. The method comprises the steps that a source device writes a PTMP request message in a current PCIE address of a target device; if it is detected that a PTMP response message written in by the target device exists in the current PCIE address of the target device within the preset time, whether response testing data carried in the PTMP response message is the same as test data carried in the PTMP request message or not is judged; if it is determined that the response testing data carried in the PTMP response message is the same as the test data carried in the PTMP request message, the current PCIE address mapping of the target device and the source device is correct; a series of determination flows are carried out in follow-up operation so as to judge whether other PCIE address mappings of the target device and the source device are correct or not. According to the method and device for PCIE address mapping detection, all the PCIE addresses of the two PCIE bus devices can be detected at the same time by utilizing interaction of the PTMP request message and the response message between the source device and the target device, the detection time is shorter, and the detection accuracy rate is higher.
Description
Technical field
The present invention relates to communication technical field, relate in particular to method and device that the mapping of a kind of PCIE address detects.
Background technology
Quick peripheral component interconnect (Peripheral Component Interconnect Express, PCIE) there is the advantage that message transmission rate is high, at present, the 16X2.0 version that this message transmission rate is the highest can reach 10GB/s, can meet the demand of the interior low-speed device of the present and the future's certain hour and high-speed equipment.
As shown in Figure 1, above-mentioned PCIE architectural framework, generally includes root assembly (Root Complex, RC) 101, switching equipment (Switch) 102 and a plurality of terminal equipment (End Point, EP) 103.Wherein, RC101 mainly completes resource distribution, equipment configuration (for example bus number/device numbering of configuration device/function numbering) and is self and EP distribution PCIE address; The downstream port of RC101 can articulate Switch102 and expand more PCIE port, can certainly directly articulate EP; The downstream port of Switch102 can articulate a plurality of EP103, and Switch102 mainly plays the effect of expansion PCIE architectural framework.
In above-mentioned PCIE architectural framework, RC carries out pci bus while enumerating (Bus Enumeration), from PCIE bus territory, be that self and each EP distribute PCIE address, so that EP is when start, the memory address in local storage territory can be mapped to PCIE address.
In order to guarantee the proper communication between equipment in PCIE architectural framework, conventionally need to detect the PCIE address mapping of EP or RC, if PCIE address mapping error cannot carry out subsequent communications.At present, conventionally adopting following two kinds of modes to realize the mapping of PCIE address detects:
First kind of way: source device is stored and write affairs by PCIE, in the appointment PCIE address of target device, write default test data, by target device, specify the test data writing in PCIE address to print this, then, compare with preset data, whether correct to determine the appointment PCIE address mapping of target device, if adopt the PCIE address of detection resources equipment in this way, reverse operating.
The second way: destination end equipment first writes default test data in local appointment PCIE address, then source device is stored and is read affairs and read this and specify the test data writing in PCIE address by PCIE, then, compare with preset data, whether correct to determine the appointment PCIE address mapping of target device, if adopt the PCIE address of detection resources equipment in this way, reverse operating.
No matter adopt above-mentioned which kind of mode to detect PCIE address, can only realize unidirectional detection, i.e. the PCIE address of the PCIE address of detection resources equipment side, or target device side, this just cause needs simultaneously when detection resources equipment and target device detection time longer.
Summary of the invention
The embodiment of the present invention provides a kind of PCIE address method and device that mapping detects, in order to solve longer problem detection time of existing detection PCIE address mapping.
Based on the problems referred to above, the method that a kind of PCIE address mapping that the embodiment of the present invention provides detects, comprising:
Source device writes point-to-multipoint (Point To Multipoint in the current PC IE address of described target device, PTMP) request message, the current PC IE address of described target device is that described source device is determined according to PCIE base address and the current PC IE address offset of the target device of this locality preservation, carries current PC IE address offset and the test data of source device in described PTMP request message;
If monitor in Preset Time in self current PC IE address and have the PTMP back message using that described target device writes, determine that whether the response test data of carrying in described PTMP back message using is identical with the test data of carrying in described PTMP request message, the current PC IE address of described source device is that described target device has after PTMP request message in monitoring the current PC IE address of self, the current PC IE address offset of the source device carrying in the PCIE base address of the source device of preserving according to this locality and described PTMP request message is determined, in described PTMP back message using, carry the next PCIE address offset of target device and respond test data,
Be defined as when identical, the current PC IE address mapping of determining described target device and described source device is correct, and by the next PICE address offset of the target device carrying in described PTMP back message using and the next PCIF address offset of self, compare with default PCIE address offset respectively, according to comparative result, determine described target device and the next PCIE address of self, using it respectively as the current PC IE address of described target device and self, return to the step that writes described PTMP request message in the current PC IE address of described target device, until determine the next PICE address offset of the target device carrying in described PTMP back message using, detection of end while being described default PCIE address offset with self next PCIE address offset.
The checkout gear of a kind of PCIE address mapping that the embodiment of the present invention provides, comprising:
Writing module, for the current PC IE address to described target device, write PTMP request message, the current PC IE address of described target device is that described device is determined according to PCIE base address and the current PC IE address offset of the target device of this locality preservation, carries current PC IE address offset and the test data of described device in described PTMP request message;
Monitoring modular, for monitor the current PC IE address of described device in Preset Time, whether there is the PTMP back message using that described target device writes, the current PC IE address of described device is that described target device has after PTMP request message in monitoring the current PC IE address of self, the current PC IE address offset of the described device carrying in the PCIE base address of the described device of preserving according to this locality and described PTMP request message is determined, and carries the next PCIE address offset of target device and respond test data in described PTMP back message using;
Determination module, in described monitoring module monitors when having the PTMP back message using that described target device writes in the current PC IE address of described device, determine that whether the response test data of carrying in described PTMP back message using is identical with the test data of carrying in described PTMP request message, and be defined as when identical, the current PC IE address mapping of determining described target device and described device is correct, by the next PCIF address offset of the next PICE address offset of the target device carrying in described PTMP back message using and described device, compare with default PCIE address offset respectively, according to comparative result, determine the next PCIE address of described target device and described device, using it respectively as the current PC IE address of described target device and described device, return to the step that writes described PTMP request message in the current PC IE address of described target device, until determine the next PICE address offset of the target device carrying in described PTMP back message using, detection of end while being described default PCIE address offset with the next PCIE address offset of described device.
The beneficial effect of the embodiment of the present invention comprises:
Method and device that a kind of PCIE address mapping that the embodiment of the present invention provides detects, utilize PTMP request message and back message using mutual between source device and target device, whether the response test data of being compared in local PCIE address by source device is identical with the test data of writing before target device, whether the PCIE mapping to be detected of determining source device and target device is correct, thereby realize the two-way detection of source device and target device, greatly shortened detection time.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing PCIE architectural framework;
The method flow diagram that the PCIE address mapping that Fig. 2 provides for the embodiment of the present invention detects;
The structural representation of the PTMP request message that Fig. 3 provides for the embodiment of the present invention;
The source device that Fig. 4 A-Fig. 4 D provides for the embodiment of the present invention and the mutual schematic diagram of detection of target device;
The structure drawing of device that the PCIE address mapping that Fig. 5 provides for the embodiment of the present invention detects.
Embodiment
Existing PCIE address mapping detection mode, can only unidirectionally detect, and detection time is longer.Based on this problem, the invention provides method and device that the mapping of a kind of PCIE address detects, utilize PTMP request message and back message using mutual between source device and target device, whether the response test data of being compared in local PCIE address by source device is identical with the test data of writing before target device, whether the PCIE mapping to be detected of determining source device and target device is correct, thereby realize the two-way detection of source device and target device, greatly shortened detection time.
In the present invention, the following detection mode of mentioning is applicable between RC and EP in PCIE architectural framework, also applicable between EP and EP, for the ease of subsequent descriptions testing process, the equipment of carrying out detection operation is referred to as to " source device ", detected equipment is referred to as to " target device ", so, for above-mentioned PCIE architectural framework, EP or RC can be used as source device, also can be used as target device, for example, in the situation that EP is source device, any one in other EP all can be used as target device, and RC also can be used as target device; At RC, as source device in the situation that, any one in each EP can be used as target device.
Further, no matter be source device, or target device, their this locality are all set up the database have one to store device identification separately and the corresponding relation of PCIE base address (being PCIE initial address) separately in advance, so that they search each self-corresponding PCIE base address according to device identification.For example, device identification can be bus number/device numbering/function numbering (Bus/Device/Function number, BDF).
In other words, for source device and target device, the PCIE address of knowing oneself each other, know PCIE address offset corresponding to PCIE base address and each PCIE address of oneself, but only can know according to above-mentioned database the PCIE base address of opposite end each other, follow-uply can carry out write operation in PCIE base address each other, if while wanting each other to carry out write operation in other PCIE addresses separately, need both sides' agreement other PCIE address offsets separately in advance, like this, source device and target device all can be according to the other side's PCIE base address, other PICE address offsets of agreement are determined other PCIE addresses separately, then carry out write operation etc.
Below in conjunction with Figure of description, the method that a kind of PCIE address mapping that the embodiment of the present invention is provided detects and the embodiment of device describe.
The method that a kind of PCIE address mapping that the embodiment of the present invention provides detects, as shown in Figure 2, specifically comprises the following steps:
S201: source device writes PTMP request message in the current PC IE address of target device;
Here, the current PC IE address of above-mentioned target device, be actually that the PCIE base address of the target device that source device preserves according to this locality and current PC IE address offset determine, and in PTMP request message, carry current PC IE address offset and the test data of source device;
That is to say, the current PC IE address of target device can be the PCIE base address of target device, and now, the current PC IE address offset of the target device that source device side is preserved is 0; Also can be other PCIE addresses except PCIE base address of target device, now, source device side, except preserving the PCIE base address of target device, be also preserved this other PCIE address offsets; In addition, for the current PC IE address offset of source device, can according to PCIE address offset corresponding to each PCIE address of self, be specified by source device;
S202: monitor in self current PC IE address whether have the PTMP back message using that target device writes in Preset Time; If so, perform step S203; Otherwise, execution step S204;
Here, the current PC IE address of above-mentioned source device, be actually target device has after PTMP request message in monitoring the current PC IE address of self, the current PC IE address offset of the source device carrying in the PCIE base address of the source device of preserving according to this locality and PTMP request message is determined, and carries the next PCIE address offset of target device and respond test data in the PTMP back message using writing in the current PC IE address of source device;
S203: determine that whether the response test data of carrying in PTMP back message using is identical with the test data of carrying in PTMP request message; If so, perform step S205; Otherwise, execution step S206;
S204: the current PC IE address mapping error of determining target device.
S205: the current PC IE address mapping of determining target device and source device is correct, and by the next PICE address offset of the target device carrying in PTMP back message using and the next PCIF address offset of self, compare with default PCIE address offset respectively, according to comparative result, determine target device and the next PCIE address of self, using it respectively as the current PC IE address of target device and self, return to the step that writes PTMP request message in the current PC IE address of target device, until determine the next PICE address offset of the target device carrying in PTMP back message using, detection of end while being default PCIE address offset with self next PCIE address offset,
S206: the current PC IE address mapping error of determining source device.
In the prior art, because the appointment PICE address of source device or target device side is open, the data cover that this test data writing while just easily causing detecting may be write by other equipment falls, and then causes testing result not accurate enough.
For head it off, in embodiments of the present invention, by controlling the running status of source device and target device, make it not disturbed between both sides' detection period, to improve Detection accuracy,, source device can be set to busy state at self, and determining target device after idle condition, carry out above-mentioned steps S201, like this, in source device and target device reciprocal process, some other equipment in PCIE architectural framework that just can not be subject to are carried out the impact of write operation on this locality, and then have improved Detection accuracy.
Further, source device can, by writing the mode of the data outside setting data in the PCIE base address to local, determine that self is in busy state; In addition, source device is determined the state of target device by reading related data in the PCIE base address of target device, be specially: when the data in reading out the PCIE base address of target device are setting data, determine that target device is in idle condition.
It should be noted that, above-mentioned setting data can be specified in advance, be used for representing that equipment is in idle condition, for example setting data is set as to full 0, the equipment that represents is in idle condition, certainly, for the data in the PCIE base address of target device, different data are representing that target device is in different running statuses, for example, when data are full 0, mean that target device is in idle condition; When data are full F, mean the PCIE base address mistake of target device; When data are non-full 0 and non-full F, mean that target device is in busy state etc.
In above-mentioned steps S201, PTMP request message is that the embodiment of the present invention is for transmitting the protocol massages of the information such as test request, PCIE address offset, test data, as shown in Figure 3, the structural representation of PTMP message, specifically can include source device sign (Src BDF), target device sign (Dst BDF), PCIE address offset and test data etc. for this reason.
It should be noted that, in order to guarantee to detect the accuracy of the PCIE address mapping of target device, above-mentioned test data remains unchanged in both reciprocal processes always.
In above-mentioned steps S201; after source device writes PTMP request message in the current PC IE address to target device; for this side of target device; it can monitor the PTMP message that in this current PC IE address, whether active equipment writes; monitoring have PTMP message in the situation that; conventionally can check whether PTMP message is PTMP request message; confirming as while being; just carry out the follow-up flow process that writes; and execute follow-up write flow process after; empty the data in this current PC IE address, with the accuracy that guarantees to detect.For example, the PCIE base address of source device is 0x01000000, and the current PC IE address offset of source device is 0x00300000, in this case, PTMP back message using is write in the PCIE address of determining according to 0x01000000 and 0x00300000.
It should be noted that, in above-mentioned steps S202, above-mentioned Preset Time can be according to the actual conditions that detect and value, and for example, Preset Time is 5 seconds, can also be other numerical value certainly.
Preferably, in above-mentioned steps S205, above-mentioned default PCIE address offset, for characterizing the next PCIE address offset of source device and last PCIE address offset of target device both sides, that is to say, no matter be source device, or target device, if the next PCIE address offset that it carries in corresponding PTMP message is default PCIE address offset, this just means has not needed the PCIE address of test.Here, default PCIE address offset for example can be set as 0XFFFF_FFFF, certainly, also can adopt other modes to identify, and at this, will not enumerate.
Further, in above-mentioned steps S205, source device specifically can be determined target device and the next PCIE address of self by following several modes:
First kind of way: the next PICE address offset of the target device carrying in comparing PTMP back message using is not default PCIE address offset, and when the next PCIE address offset of self is default PCIE address offset, according to the next PICE address offset of the target device carrying in the PCIE base address of target device and PTMP back message using, determine the next PCIE address of target device; And according to the PCIE base address of self and current PC IE address offset, determine the next PCIE address of self;
The second way: the next PICE address offset of the target device carrying in comparing PTMP back message using is default PCIE address offset, and the next PCIE address offset of self is during for default PCIE address offset, according to the PCIE base address of target device and current PC IE address offset, determine the next PCIE address of target device; And according to the PCIE base address of self and next PCIE address offset, determine the next PCIE address of self;
The third mode: the next PICE address offset of the target device carrying in comparing PTMP back message using is not default PCIE address offset, and when the next PCIE address offset of self is not default PCIE address offset, according to the next PCIE address offset of the target device carrying in the PCIE base address of target device and PTMP back message using, determine the next PCIE address of target device; And according to the PCIE base address of self and next PCIE address offset, determine the next PCIE address of self.
Particularly, in embodiments of the present invention, for source device and target device, do not know the other side and be provided with how many PCIE addresses, so, may there is following several situation in both sides' PCIE address:
The first situation: the PCIE number of addresses of source device and target device is identical, in this case, may have following two kinds of situations:
The first situation: both sides only comprise separately current PCIE address, in this case, the next PCIE address offset of source device and target device is default PCIE address offset, both sides detected complete, detection of end;
Second case, both sides comprise the PCIE address that quantity is identical, in this case, if the next PCIE address offset of source device and target device is not all default PCIE address offset, so, adopt above-mentioned the third mode to determine target device and the next PCIE address of self, until by both sides' the complete end of PCIE address detected.For example, device A (source device) comprises A1, A2 and these 3 PCIE addresses of A3; Equipment B (target device) comprises B1, B2 and these 3 PCIE addresses of B3, and so, the detection of device A and equipment B alternately can be as shown in Figure 4 A.
The second situation: the PCIE number of addresses of source device is more than the PCIE number of addresses of target device, in this case, when the next PCIE address offset of source device and target device is all not default PCIE address offset, adopt above-mentioned the third mode to determine target device and the next PCIE address of self; When the next PCIE address offset of target device is default PCIE address offset, adopt the above-mentioned second way to determine target device and the next PCIE address of self, until detected the PCIE end of address (EOA) of source device.For example, device A (source device) comprises these 5 PCIE addresses of A1, A2, A3, A4 and A5; Equipment B (target device) comprises B1, B2 and these 3 PCIE addresses of B3, and so, the detection of device A and equipment B alternately can be as shown in Figure 4 B.
The third situation: the PCIE number of addresses of source device is less than the PCIE number of addresses of target device, in this case, when the next PCIE address offset of source device and target device is all not default PCIE address offset, adopt above-mentioned the third mode to determine target device and the next PCIE address of self; When the next PCIE address offset of self is default PCIE address offset, adopt above-mentioned first kind of way to determine target device and the next PCIE address of self, until detected the PCIE end of address (EOA) of target device.For example, device A (source device) comprises A1, A2 and these 3 PCIE addresses of A3; Equipment B (target device) comprises these 5 PCIE addresses of B1, B2, B3, B4 and B5, and so, the detection of device A and equipment B alternately can be as shown in Figure 4 C.
Certainly, the embodiment of the present invention is not limited in above-mentioned several mode and determines target device and the next PCIE address of self, can also adopt other to determine that mode realizes, for example, in the situation that the PCIE number of addresses of source device is less than the PCIE number of addresses of target device, suppose that the next PCIE address offset that compares source device is for presetting PCIE address offset, at this moment, source device can be selected one from write before the next PCIE address offset the PTMP message of target device side, then according to the base address of self and the PCIE address offset being chosen in out, determine the next PCIE address of source device, at this, will not enumerate.
Preferably, in embodiments of the present invention, the accuracy rate detecting in order further to improve the mapping of PCIE address, when source device does not have the PTMP back message using that target device writes in monitoring the current PC IE address of self, do not carry out immediately above-mentioned steps S204, can first carry out following flow process: again in the current PC IE address of target device, write PTMP request message, and while not monitoring yet PTMP back message using when the number of times of the PTMP request message again writing reaches the first set point number, then carry out above-mentioned steps S204.
Preferably, in embodiments of the present invention, the accuracy rate detecting in order further to improve the mapping of PCIE address, source device is in the situation that the response test data of carrying in determining PTMP back message using is not identical with the test data of carrying in PTMP request message, can not carry out immediately above-mentioned steps S206, first carry out following flow process: the current PC IE address to target device writes PTMP request message again, then the number of times at the PTMP request message again writing reaches set point number, and determine the response test data of carrying in PTMP back message using, when still identical with test data in PTMP request message, carry out again above-mentioned steps S206.
It should be noted that, at above-mentioned two kinds, preferably carry out in flow process, above-mentioned the first set point number and the second set point number all can be determined according to the actual conditions that detect, the two can be set as identical numerical value, also can be set as different numerical value, for example, the two all can be set as 3.
Preferably, in embodiments of the present invention, the accuracy rate detecting in order further to improve the mapping of PCIE address, after whether the response test data that source device carries in determining PTMP back message using is identical with the test data of carrying in PTMP request message, empty the data in the current PC IE address of source device, or while having the PTMP message newly writing in monitoring this current PC IE address, cover the last PTMP message writing.
Still take device A (source device) and equipment B (target device) is below example, and above-mentioned detection method is carried out to brief description:
As shown in Figure 4 D, the current PC IE address of supposing device A is A1, and corresponding PCIE address offset is X1, and next PCIE address is A2, and corresponding PCIE address offset is X2; The current PC IE address of equipment B is B1, and next PCIE address is B2, and corresponding PCIE address offset is Y2; The current PC IE address of equipment B is B1; Device A is known the PCIE address of the current PC IE address B1 of equipment B; In addition, suppose that device A writes the data outside full 0 to the PCIE base address (Fig. 4 D does not show) of self, make it current in busy state, and the data in the PCIE base address of fetch equipment B are full 0, determine equipment B in idle condition.
So, in this case, device A need be carried out above-mentioned steps S201, B1 to equipment B writes PTMP request message, in this PTMP request message, carry X1 and test data, like this, equipment B has after this PTMP request message monitoring B1, the current PC IE address of determining device A according to the PCIE base address of the device A of obtaining and X1 from local data base, be A1, then, equipment B can write PTMP response message to A1, carries the next PCIE address offset of Y2(in this PTMP response message) and respond test data.
For device A, when monitoring, it in A1, has after the PTMP response message that equipment B writes, first confirm that whether the response test data in PTMP response message is identical with the test data of writing before B1, suppose to confirm as identical, so, device A is according to the PCIE base address of the equipment B of obtaining from local data base and the next PCIE address that Y2 determines equipment B, be B2, and confirm that Y2 is not 0XFFFF_FFFF (default offset address), at this moment, to B2, again write the PTMP request message that carries X2 and above-mentioned test data, equipment B is when monitoring B2 and have PTMP request message, know that this address is for last local PCIE address, in this case, it writes to the A2 (concrete deterministic process is the same) of device A the PTMP response message that carries 0XFFFF_FFFF and respond test data, so, during the related data of device A in monitoring A2, suppose still to confirm as identical, at this moment, A2 is last the PCIE address of self, the next PCIE address offset that is self is 0XFFFF_FFFF, the next PCIE address offset of equipment B is 0XFFFF_FFFF also, show that detection is complete, exit testing process.
Based on same inventive concept, the embodiment of the present invention also provides a kind of PCIE address device that mapping detects, because the principle that this device is dealt with problems is similar to the method that the mapping of aforementioned PCIE address detects, therefore the enforcement of this device can, referring to the enforcement of preceding method, repeat part and repeat no more.
The checkout gear of a kind of PCIE address mapping that the embodiment of the present invention provides, as shown in Figure 5, specifically can comprise:
Here, the current PC IE address of above-mentioned target device is that device is determined according to base address and the current PC IE address offset of the target device of this locality preservation, and in PTMP request message, carries current PC IE address offset and the test data of device;
Whether monitoring modular 502, have for the current PC IE address of monitoring device in Preset Time the PTMP back message using that target device writes;
Here, the current PC IE address of said apparatus is that target device has after PTMP request message in monitoring the current PC IE address of device, the current PC IE address offset of the device carrying in the PCIE base address of the device of preserving according to this locality and PTMP request message is determined, and carries the next PCIE address offset of target device and respond test data in the PTMP back message using writing in the current PC IE address of device;
Preferably, said apparatus, also can comprise:
Above-mentioned determination module 503, for being set to after busy state module 504 devices are set, determines that whether target device is in idle condition;
Above-mentioned writing module 501 specifically for when determination module 503 is determined target device in idle condition, writes PTMP request message in the current PC IE address of target device.
Preferably, the above-mentioned module 504 that arranges, specifically for writing after the data outside setting data in the base address to device, determining device is in busy state;
Above-mentioned determination module 503, while being setting data specifically for the data in reading out the base address of target device, determines that target device is in idle condition.
Preferably, above-mentioned determination module 503, next PICE address offset specifically for the target device that carries in comparing PTMP back message using is not default PCIE address offset, and when the next PCIE address offset of device is default PCIE address offset, according to the next PICE address offset of the target device carrying in the PCIE base address of target device and PTMP back message using, determine the next PCIE address of target device; And according to the PCIE base address of device and the current PC IE address offset next PCIE address of determining device; The next PICE address offset of the target device carrying in comparing PTMP back message using is default PCIE address offset, and the next PCIE address offset of device is during for default PCIE address offset, according to the PCIE base address of target device and current PC IE address offset, determine the next PCIE address of target device; And according to the PCIE base address of device and the next PCIE address offset next PCIE address of determining device; And the next PICE address offset of the target device carrying in comparing PTMP back message using is not default PCIE address offset, and when the next PCIE address offset of device is not default PCIE address offset, according to the next PCIE address offset of the target device carrying in the PCIE base address of target device and PTMP back message using, determine the next PCIE address of target device; And according to the PCIE base address of device and the next PCIE address offset next PCIE address of determining device.
Preferably, above-mentioned writing module 501, also when not monitoring the current PC IE address of device at monitoring modular 502 have the PTMP back message using that target device writes in Preset Time, again in the current PC IE address of target device, write PTMP request message;
Above-mentioned determination module 503, also the number of times for the PTMP request message that again writes at writing module 501 reaches the first set point number, and when monitoring modular 502 does not monitor PTMP back message using yet, determine the current PC IE address mapping error of target device, and detection of end.
Preferably, above-mentioned writing module 501, also for determine the response test data that PTMP back message using carries at determination module 503, when not identical with test data in PTMP request message, the current PC IE address to target device writes PTMP request message again;
Above-mentioned determination module 503, also the number of times for the PTMP request message that again writes at writing module 501 reaches the second set point number, and determine the response test data of carrying in PTMP back message using, when still identical with test data in PTMP request message, the current PC IE address mapping error of determining device, and detection of end.
Preferably, said apparatus, also comprises:
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. the method that the mapping of quick peripheral component interconnect PCIE address detects, is characterized in that, comprising:
Source device writes point-to-multipoint PTMP request message in the current PC IE address of described target device, the current PC IE address of described target device is that described source device is determined according to PCIE base address and the current PC IE address offset of the target device of this locality preservation, carries current PC IE address offset and the test data of source device in described PTMP request message;
If monitor in Preset Time in self current PC IE address and have the PTMP back message using that described target device writes, determine that whether the response test data of carrying in described PTMP back message using is identical with the test data of carrying in described PTMP request message, the current PC IE address of described source device is that described target device has after described PTMP request message in monitoring the current PC IE address of self, the current PC IE address offset of the source device carrying in the PCIE base address of the source device of preserving according to this locality and described PTMP request message is determined, in described PTMP back message using, carry the next PCIE address offset of target device and respond test data,
Be defined as when identical, the current PC IE address mapping of determining described target device and described source device is correct, and by the next PICE address offset of the target device carrying in described PTMP back message using and the next PCIF address offset of self, compare with default PCIE address offset respectively, according to comparative result, determine described target device and the next PCIE address of self, using it respectively as the current PC IE address of described target device and self, return to the step that writes described PTMP request message in the current PC IE address of described target device, until determine the next PICE address offset of the target device carrying in described PTMP back message using, detection of end while being described default PCIE address offset with self next PCIE address offset.
2. the method for claim 1, is characterized in that, described source device also comprised write PTMP request message in the current PC IE address to described target device before:
Self is set to busy state, and determines that whether described target device is in idle condition;
If so, in the current PC IE address of described target device, write described PTMP request message.
3. method as claimed in claim 1 or 2, is characterized in that, described source device is determined described target device and the next PCIE address of self by following manner:
If it is not default PCIE address offset that described source device compares the next PICE address offset of the target device carrying in described PTMP back message using, and the next PCIE address offset of self is described default PCIE address offset, according to the next PICE address offset of the target device carrying in the PCIE base address of described target device and described PTMP back message using, determine the next PCIE address of described target device; And according to the PCIE base address of self and current PC IE address offset, determine the next PCIE address of self;
If it is default PCIE address offset that described source device compares the next PICE address offset of the target device carrying in described PTMP back message using, and the next PCIE address offset of self is not described default PCIE address offset, according to the PCIE base address of described target device and current PC IE address offset, determine the next PCIE address of described target device; And according to the PCIE base address of self and next PCIE address offset, determine the next PCIE address of self;
If it is not default PCIE address offset that described source device compares the next PICE address offset of the target device carrying in described PTMP back message using, and the next PCIE address offset of self is not described default PCIE address offset, according to the next PCIE address offset of the target device carrying in the PCIE base address of described target device and described PTMP back message using, determine the next PCIE address of described target device; And according to the PCIE base address of self and next PCIE address offset, determine the next PCIE address of self.
4. method as claimed in claim 1 or 2, is characterized in that, also comprises:
If source device monitors in self current PC IE address in described Preset Time, there is not the PTMP back message using that described target device writes, again in the current PC IE address of described target device, writes described PTMP request message;
If the number of times of the PTMP request message that source device writes does not again monitor described PTMP back message using yet while reaching the first set point number, determine the current PC IE address mapping error of target device, and detection of end.
5. method as claimed in claim 4, is characterized in that, also comprises:
If the response test data that source device carries in determining described PTMP back message using is not identical with the test data in described PTMP request message, again to the current PC IE address of described target device, write described PTMP request message;
If the number of times of the PTMP request message that source device writes again reaches the second set point number, and determine the response test data of carrying in described PTMP back message using, still not identical with the test data in described PTMP request message, determine the current PC IE address mapping error of source device, and detection of end.
6. the device that the mapping of quick peripheral component interconnect PCIE address detects, is characterized in that, comprising:
Writing module, for the current PC IE address to described target device, write point-to-multipoint PTMP request message, the current PC IE address of described target device is that described device is determined according to PCIE base address and the current PC IE address offset of the target device of this locality preservation, carries current PC IE address offset and the test data of described device in described PTMP request message;
Monitoring modular, for monitor the current PC IE address of described device in Preset Time, whether there is the PTMP back message using that described target device writes, the current PC IE address of described device is that described target device has after PTMP request message in monitoring the current PC IE address of described device, the current PC IE address offset of the described device carrying in the PCIE base address of the described device of preserving according to this locality and described PTMP request message is determined, and carries the next PCIE address offset of target device and respond test data in described PTMP back message using;
Determination module, in described monitoring module monitors when having the PTMP back message using that described target device writes in the current PC IE address of described device, determine that whether the response test data of carrying in described PTMP back message using is identical with the test data of carrying in described PTMP request message, and be defined as when identical, the current PC IE address mapping of determining described target device and described device is correct, by the next PCIF address offset of the next PICE address offset of the target device carrying in described PTMP back message using and described device, compare with default PCIE address offset respectively, according to comparative result, determine the next PCIE address of described target device and described device, using it respectively as the current PC IE address of described target device and described device, return to the step that writes described PTMP request message in the current PC IE address of described target device, until determine the next PICE address offset of the target device carrying in described PTMP back message using, detection of end while being described default PCIE address offset with the next PCIE address offset of described device.
7. device as claimed in claim 6, is characterized in that, described device, also comprises:
Module is set, and for when described device is source device, described device is set to busy state;
Determination module, also, for being set to after busy state at the described described device of module that arranges, determines that whether target device is in idle condition;
Said write module specifically for when described determination module is determined described target device in idle condition, writes described PTMP request message in the current PC IE address of described target device.
8. the device as described in claim 6 or 7, it is characterized in that, described determination module, next PICE address offset specifically for the target device that carries in comparing described PTMP back message using is not default PCIE address offset, and when the next PCIE address offset of described device is described default PCIE address offset, according to the next PICE address offset of the target device carrying in the PCIE base address of described target device and described PTMP back message using, determine the next PCIE address of described target device; And the next PCIE address of determining described device according to the PCIE base address of described device and current PC IE address offset; The next PICE address offset of the target device carrying in comparing described PTMP back message using is default PCIE address offset, and when the next PCIE address offset of described device is not described default PCIE address offset, according to the PCIE base address of described target device and current PC IE address offset, determine the next PCIE address of described target device; And the next PCIE address of determining described device according to the PCIE base address of described device and next PCIE address offset; And the next PICE address offset of the target device carrying in comparing described PTMP back message using is not default PCIE address offset, and when the next PCIE address offset of described device is not described default PCIE address offset, according to the next PCIE address offset of the target device carrying in the PCIE base address of described target device and described PTMP back message using, determine the next PCIE address of described target device; And the next PCIE address of determining described device according to the PCIE base address of described device and next PCIE address offset.
9. the device as described in claim 6 or 7, it is characterized in that, said write module, also when not monitoring the current PC IE address of described device at described monitoring modular have the PTMP back message using that described target device writes in described Preset Time, again in the current PC IE address of described target device, write described PTMP request message;
Described determination module, also the number of times for the PTMP request message that again writes in said write module reaches the first set point number, and when described monitoring modular does not monitor described PTMP back message using yet, determine the current PC IE address mapping error of target device, and detection of end.
10. device as claimed in claim 9, it is characterized in that, said write module, also for determine the response test data that described PTMP back message using carries at described determination module, when not identical with test data in described PTMP request message, the current PC IE address to described target device writes described PTMP request message again;
Described determination module, also the number of times for the PTMP request message that again writes in said write module reaches the second set point number, and determine the response test data of carrying in described PTMP back message using, when still identical with test data in described PTMP request message, determine the current PC IE address mapping error of described device, and detection of end.
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