CN103730150A - Level shifting circuit - Google Patents
Level shifting circuit Download PDFInfo
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- CN103730150A CN103730150A CN201410005964.5A CN201410005964A CN103730150A CN 103730150 A CN103730150 A CN 103730150A CN 201410005964 A CN201410005964 A CN 201410005964A CN 103730150 A CN103730150 A CN 103730150A
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Abstract
The invention relates to a level shifting circuit. The level shifting circuit comprises a current supply unit, and a level shifting unit, wherein the current supply unit is suitable for supplying control current; the level shifting unit comprises a signal input node suitable for inputting a first level signal and a signal output node suitable for outputting a second level signal; the level shifting unit is connected with the current supply unit and is suitable for inputting the control current so as to control the level conversion rate of the output node. The level conversion rate of the level shifting circuit under different high levels can be controlled.
Description
Technical field
The present invention relates to semiconductor circuit, particularly a kind of level shift circuit.
Background technology
In the information age, information storage is one of most important technology contents in infotech.The storeies such as DRAM, EEPROM, flash memory obtain applying more and more widely.
In order to realize reading and the operation such as programming of information, storer need to change to obtain required operating voltage between different level: such as, in 90nm high speed Flash storer, in different operator schemes, column decoder (also claiming to be Y code translator) need to provide different bit-line voltages to Destination Storage Unit, such as, in read operation, column decoder need to load to selected bit line the voltage that reads of 3V, and in programming operation, column decoder need to be to program voltage more than selected bit line loading 5V to choose bit line, now, bit-line voltage is generally 8V.Column decoder is to obtain required operating voltage by level shift circuit.
A kind of level shift circuit as shown in Figure 1, comprising: phase inverter INV, PMOS pipe P1 and P2, NMOS pipe N1 and N2; Wherein,
The input signal Data input NMOS pipe grid of N1 and the input end of phase inverter INV, the output of phase inverter INV is connected with the grid of NMOS pipe N2;
The source ground GND of NMOS pipe N1, drain electrode connects the drain electrode of PMOS pipe P1 and the grid of PMOS pipe P2, and the source electrode of PMOS pipe P1 meets supply voltage VDD;
The source ground GND of NMOS pipe N2, drain electrode connects the drain electrode of PMOS pipe P2 and the grid of PMOS pipe P1, and the source electrode of PMOS pipe P2 connects supply voltage VDD.
Continuation is with reference to figure 1, when input signal Data is high level state, node V11 is low level, node V12 is high level, NMOS pipe N1 conducting, NMOS pipe N2 cut-off, PMOS pipe P2 conducting, PMOS pipe P1 cut-off, when input signal Data transfers low level to from high level, NMOS pipe N1 cut-off, NMOS pipe N2 conducting, now, due to, node V11 still remains low level, node V12 still keeps high level, and NMOS pipe N2 and PMOS pipe P2 at the state of conducting and flow through and run through electric current, make node V12 drop to low level in just; When node 12 is low level, PMOS pipe P1 conducting, and produce and run through electric current, make node V11 rise to high level.In said process, in order to make node V12 drop to low level, need to strengthen the transistor size of NMOS pipe N2; In order to make node V11 rise to high level, need to add the transistor size of big pmos P1.
While transferring high level for input signal Data to from low level, situation is also similarly, in order to make node V11 drop to low level, need to strengthen the transistor size of NMOS pipe N1; In order to make node V12 rise to high level, need to add the transistor size of big pmos P2.
But corresponding to the required different operating voltage of storer, the high level of level shift circuit is different.For the high level voltage of exporting after level shift, under some operator scheme of storer, such as, during programming operation, if switching rate is too fast, may be to other devices of storer, such as column decoder or other storage unit, cause high-tension moment impact, can cause damage by storage component part.The level conversion speed of the level shift circuit of prior art is determined by transistor characteristic, for level shift circuit as shown in Figure 1, what according to transistor size, obtain runs through electric current, can make level shift circuit conversion fast between level, but the further level conversion speed of control level shift circuit.
Summary of the invention
The technical matters that technical solution of the present invention solves is: the how level conversion speed of control level shift circuit.
In order to solve the problems of the technologies described above, technical solution of the present invention provides a kind of level shift circuit, comprises;
Electric current provides unit, is suitable for providing control electric current;
Electrical level shift units, comprises the signal output node that is suitable for inputting the signal input node of the first level signal and is suitable for exporting second electrical level signal; Described electrical level shift units provides unit to be connected with described electric current, is suitable for inputting described control electric current, to control the level conversion speed of described output node.
Optionally, described electrical level shift units also comprises the first power supply node and the second source node that is suitable for being connected second source that are suitable for connecting the first power supply; The level value of described second electrical level signal is changed between the level value of the first power supply and the level value of second source.
Optionally, described the first power supply is suitable for providing the first level and second electrical level;
Described electric current provides unit to be suitable for when described the first power supply provides described the first level, providing described control electric current, stops providing described control electric current when described the first power supply provides second electrical level.
Optionally, described electric current provides unit to provide unit for the first electric current provides unit or the second electric current, or described electric current provides unit to comprise that the first electric current provides unit and the second electric current that unit is provided;
Described the first electric current provides unit to be suitable for providing the first control electric current to described the first power supply node, and described the second electric current provides unit to be suitable for providing the second control electric current to described second source node.
Optionally, described the first electric current provides unit to comprise the PMOS current mirror consisting of input PMOS pipe and mirror image PMOS pipe, and the source electrode of described mirror image PMOS pipe connects described the first power supply, and the drain electrode of described mirror image PMOS pipe connects described the first power supply node;
Described the second electric current provides unit to comprise the NMOS current mirror consisting of input NMOS pipe and mirror image NMOS pipe, and the source electrode of described mirror image NMOS pipe connects described second source, and the drain electrode of described mirror image NMOS pipe connects described second source node.
Optionally, described the first electric current provides unit also to comprise and controls NMOS pipe, and its drain electrode is connected with the grid of described mirror image PMOS pipe, and grid is inputted the first control signal, and source electrode input is suitable for making the level of described mirror image PMOS pipe conducting;
Described the second electric current provides unit also to comprise and controls PMOS pipe, and its drain electrode is connected with the grid of described mirror image NMOS pipe, and grid is inputted the second control signal, and source electrode input is suitable for making the level of described mirror image NMOS pipe conducting.
Optionally, described the first power supply provides the first level and second electrical level;
Described the first control signal is suitable for controlling the cut-off of described control NMOS pipe when described the first power supply provides the first level, controls the conducting of described control NMOS pipe when described the first power supply provides second electrical level;
Described the second control signal is suitable for controlling the cut-off of described control PMOS pipe when described the first power supply provides the first level, controls the conducting of described control PMOS pipe when described the first power supply provides second electrical level.
Optionally, described electric current provides unit to comprise that the first electric current provides unit and the second electric current that unit is provided, and also comprises: current source cell, is connected between described input PMOS pipe and input NMOS pipe.
Optionally, described the first power supply provides the first level and second electrical level; Described electric current provides unit also to comprise: control tube, be connected between described current source cell and described input PMOS pipe, or, be connected between described current source cell and described input NMOS pipe;
Grid input the 3rd control signal of described control tube, described the 3rd control signal is suitable for when described the first power supply provides the first level, controlling described control tube conducting, controls described control tube cut-off when described the first power supply provides second electrical level.
Optionally, described signal output node comprises the first output node and the second output node, and described electrical level shift units also comprises a PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 2nd NMOS pipe and phase inverter;
The drain electrode of a described PMOS pipe, the drain electrode of a NMOS pipe are connected described the first output node with the grid of described the 2nd PMOS pipe;
The drain electrode of described the 2nd PMOS pipe, the drain electrode of the 2nd NMOS pipe are connected described the second output node with the grid of a described PMOS pipe;
Described signal input node connects the grid of a described NMOS pipe by described phase inverter, described signal input node connects the grid of described the 2nd NMOS pipe;
The source electrode of a described PMOS pipe is connected described the first power supply node with the source electrode of described the 2nd PMOS pipe;
The source electrode of a described NMOS pipe is connected described second source node with the source electrode of described the 2nd NMOS pipe.
The beneficial effect of technical solution of the present invention at least comprises:
By control electric current is provided for electrical level shift units, make the output node of electrical level shift units slow down the speed of level conversion, particularly, for the level conversion of high level, can avoid the voltge surge to other devices of storer, prevent that device from damaging.
In possibility, control electric current and comprise that the first control electric current and second controls electric current, and can select one and provide also and can all provide, wherein, first controls electric current can slow down the switching rate of low level to high level, and second controls electric current can slow down high level to low level switching rate;
In possibility, that controls electric current provides relevant with the high level amplitude of level conversion, if high level amplitude lower (the first level), consider that the first level may be when reading voltage or other and can not cause voltge surge maybe to need to improve the voltage of level conversion speed to device, can stop controlling providing of electric current, if high level amplitude higher (second electrical level), consider to prevent the voltge surge that voltage that the quick conversion of second electrical level brings brings storage component part, recover to control providing of electric current, to slow down the switching rate of level; So can save power consumption, realize electric current utilization ratio and maximize.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of level shift circuit of prior art;
Fig. 2 is the structural representation of the level shift circuit of embodiment 1;
Fig. 3 is the structural representation of the level shift circuit of embodiment 2.
Embodiment
For object of the present invention, feature and effect can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from other modes described here, implemented, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, the level conversion efficiency of the level shifter of prior art is actual has greatest associated with transistor size:
With reference to figure 1, when input signal Data transfers low level to from high level, the electric current (running through electric current hereinafter referred to as first) that runs through that NMOS pipe N2 and PMOS pipe P2 flow through makes node V12 drop to low level; And PMOS pipe P1 produces and runs through electric current (running through electric current hereinafter referred to as second) and make node V11 rise to high level.In fact, the level fall off rate of node V12 and the electrical level rising speed of node V11, be to run through electric current and second to run through the size of electric current relevant to first respectively.Prior art is that the transistor size by strengthening NMOS pipe N2 strengthens first and runs through electric current, by adding the transistor size of big pmos P1, strengthens second and runs through electric current.But first, increasing transistor size is limited a kind of means, and transistor size can affect the circuit area of storer, in technical field of semiconductors, transistor size is always controlled within the specific limits; Secondly, the amplitude of level conversion is to change, from the speed of level conversion, for the level magnitude under particular case, the switching rate of this level has fast, also to have needs slowly conversion, the difference of the diversity based on operating voltage in storer and level conversion rate requirement, prior art level shifter can only be compromised transistor size or fixed crystal pipe size are set:
Such as, for 90nm high speed Flash storer, in its read operation, can meet the voltage transitions of 0V to 3V, to export, read voltage, the level conversion speed of establishing level shift circuit as shown in Figure 1 can meet the desired reading rate of read operation;
But the level shift circuit of Fig. 1 need to meet the voltage transitions of 0V to 8V in its programming operation, now, above-mentioned voltage conversioning rate is very fast, because the high pressure of 8V can bring the voltge surge of moment to other storeies such as column decoder and storage unit, can wish that now the speed of level conversion is slow, but the level shift circuit of prior art cannot in these cases, be controlled the level conversion speed of level shift circuit.
Analyze: for the level shifting circuit of prior art, its transistor size is determined, it first runs through electric current and the second size that runs through electric current is also determined, the speed of level conversion mainly first runs through electric current and second and runs through electric current based on what form in transistor; Therefore, can consider when controlling the size of current flowing through in transistor level conversion speed is controlled.
Based on above-mentioned thinking, technical solution of the present invention provides a kind of level shifting circuit, below in conjunction with drawings and Examples, is elaborated.
Embodiment 1
For the problems referred to above, the present embodiment provides a kind of level shifting circuit as shown in Figure 2, comprising:
Electric current provides unit 100, is suitable for providing control electric current;
Electrical level shift units 200, comprises the signal output node (out1, out2) that is suitable for inputting the signal input node of the first level signal data and is suitable for exporting second electrical level signal (vout1, vout2); Described electrical level shift units provides unit to be connected with described electric current, is suitable for inputting described control electric current.
In the present embodiment, the first level signal data is the input signal of electrical level shift units 200, and electrical level shift units 200 changes the second electrical level signal (vout1, vout2) of signal output node (out1, out2) according to described the first level signal data between low level and high level.Described high level can be to be provided by the first power supply of outside or level shift circuit inside, and described low level can be to be provided by the second source of outside or level shift circuit inside; Described second source can provide earth level (being generally 0V).
When described the first level signal data make output node out1 from high level to low transition, output node out2 is when change from low level to high level, electric current provides unit 100 can provide a road to control electric current (second controls electric current I 2) to output node out1, make the level slow decreasing on described output node out1, electric current provides unit 100 also can provide another road to control electric current (first controls electric current I 1) and, to output node out2, makes the level rising on described output node out2; The electric current that runs through providing by the transistor in electrical level shift units 200 is not provided the present embodiment, but by above-mentioned control electric current, the level of output node (out1, out2) is changed, thereby by controlling the size of described control electric current, the speed of control circuit level conversion.
Further, second controls electric current I 2 can consider to be carried on the nmos pass transistor of corresponding output node out1 mono-side, and first controls electric current I 1 can consider to be carried on the PMOS transistor of corresponding output node out2 mono-side.Above-mentioned the first control electric current I 1 and the second control electric current I 2 can select one to be provided, and also can provide simultaneously.
Similarly, when described the first level signal data make output node out2 from high level to low transition, output node out1 is when change from low level to high level, electric current provides unit 100 can provide the second control electric current I 2 to output node out2, make the level slow decreasing on described output node out2, electric current provides unit 100 also can provide the first control electric current I 1 to output node out1, makes the level rising on described output node out1.In these cases, second controls electric current I 2 can consider to be carried on the nmos pass transistor of corresponding output node out2 mono-side, and first controls electric current I 1 can consider to be carried on the PMOS transistor of corresponding output node out1 mono-side.Above-mentioned the first control electric current I 1 and the second control electric current I 2 can select one equally to be provided, and also can provide simultaneously.
The present embodiment does not limit the concrete structure of electrical level shift units 200: electrical level shift units 200 comprises two corresponding output node out1, out2 and signal input node datain; Can be using one in described output node as described signal output node, or using two input nodes all as described signal output node, it is relevant that the selection of above-mentioned output node and the function of level shift circuit realize, thereby the present embodiment is not restricted.
Embodiment 2
The present embodiment, on the basis of embodiment 1, has provided more specifically level shift circuit of another kind, as shown in Figure 3:
Electrical level shift units comprises:
The first power supply node VH and second source node VL;
The first output node out1 and the second output node out2;
The one PMOS pipe P10, the 2nd PMOS pipe P20, a NMOS pipe N10 and the 2nd NMOS pipe N20.
The first power supply node VH is suitable for being connected with the first described power supply, second source node VL is suitable for being connected with described second source, the first power supply provides high value vdd, second source provides low level value, in the present embodiment, the direct ground connection of second source node VL (GND) also obtains earth level.
The drain electrode of the one PMOS pipe P10, the drain electrode of a NMOS pipe N10 are connected with the first output node out1 respectively with the grid of the 2nd PMOS pipe P20;
The drain electrode of the 2nd PMOS pipe P20, the drain electrode of the 2nd NMOS pipe N20 are connected with the second output node out2 respectively with the grid of a PMOS pipe P10;
The grid of the one NMOS pipe N10 is signal input node datain, and signal input node datain is connected with the grid of the 2nd NMOS pipe N20 through phase inverter INV1;
The source electrode of the one PMOS pipe P10 is suitable for being respectively connected with the first power supply node VH with the source electrode of the 2nd PMOS pipe P20;
The source electrode of the one NMOS pipe N10 is suitable for being respectively connected with second source node VL with the source electrode of the 2nd NMOS pipe N20.
The present embodiment is using the grid of a NMOS pipe N10 as described signal input node, using the first output node out1 and the second output node out2, respectively as described signal output node, the level value of second electrical level signal (vout1, vout2) is changed between high value vdd and earth level.
In other embodiments, the signal input node of electrical level shift units 200 also can comprise the grid of a NMOS pipe N10 and the grid of the 2nd NMOS pipe N20, input respectively anti-phase each other signal, as the grid of a NMOS pipe N10 is inputted the first level signal, the grid of the 2nd NMOS pipe N20 is inputted the inversion signal of the first level signal.
Introducing the present embodiment electric current below provides the concrete structure of unit.
Continuation is with reference to figure 3, the electric current of the present embodiment provides unit to comprise that the first electric current provides unit and the second electric current that unit is provided, described the first electric current provides unit first to control electric current I 1 for providing as described in Example 1, and described the second electric current provides unit second to control electric current I 2 for providing as described in Example 1.
As shown in Figure 3, the first electric current provides unit to comprise:
PMOS current mirror, consists of input PMOS pipe P30 and mirror image PMOS pipe P40, and wherein, the source electrode of mirror image PMOS pipe P40 connects described the first power supply, accesses high level vdd, and the drain electrode of mirror image PMOS pipe P40 connects the first power supply node VH.
The present embodiment is managed P40 to the first current mirror of drain electrode to mirror image PMOS by the source electrode forming in input PMOS pipe P30 and is controlled electric current I 1 to produce described first; The first power supply node VH is inputted to described first and control electric current I 1, make a PMOS pipe P10 or the interior little electric current of a road source electrode to drain electrode that form of the 2nd PMOS pipe P20 in level shift process, this little electric current is less than the source-drain current of PMOS pipe in (also can equal) described electrical level shift units, this little electric current can make the voltage rising of corresponding output node, to control the output node low level conversion efficiency to high level, reduce now low level to the conversion efficiency of high level.
Continuation provides unit to comprise with reference to figure 3, the second electric currents:
NMOS current mirror, consists of input NMOS pipe N30 and mirror image NMOS pipe N40, and wherein, the source electrode of mirror image NMOS pipe N40 connects described second source, i.e. ground connection, and the drain electrode of mirror image NMOS pipe N40 connects second source node VL.
The present embodiment is controlled electric current I 2 to the second current mirror of source electrode to mirror image NMOS pipe N40 to produce described second by draining of forming in input NMOS pipe N30; Second source node VL is inputted to this second control electric current I 2, thereby a NMOS pipe N10 or the interior road that forms of the 2nd NMOS pipe P20 in level shift process are drained to the little electric current of source electrode, this little electric current is less than the source-drain current of NMOS pipe in (also can equal) described electrical level shift units, this little electric current can make the voltage slow decreasing of corresponding output node, reduces output node high level to low level conversion efficiency.The described second current value of controlling electric current I 2 can be greater than the current value of the first control electric current I 1 relatively.
Conventionally, adapt with 90nm high speed Flash storer, the first control electric current I 1 can be 30uA, and the second control electric current I 2 can be 60uA.Be directed to dissimilar storer, the described first value of controlling electric current and the second control electric current can be different.
In addition, the first above-mentioned electric current can equate with the first control electric current I 1 (when the transistor size of input PMOS pipe P30 and mirror image PMOS pipe P40 equates), also can input by adjustment the transistor size of PMOS pipe P30 and mirror image PMOS pipe P40, set the first electric current and the first proportionate relationship of controlling between electric current I 1, to obtain the size of the first required control electric current I 1;
In like manner, the second above-mentioned electric current also can equate with the second control electric current I 2 (when the transistor size of input NMOS pipe N30 and mirror image NMOS pipe N40 equates), also can input by adjustment the transistor size of NMOS pipe N30 and mirror image NMOS pipe N40, set the second electric current and the second proportionate relationship of controlling between electric current I 2, to obtain the size of the second required control electric current I 2.
Further, with reference to figure 3: the second electric current in the first electric current in input PMOS pipe P30 and input NMOS pipe N30 can be provided by current source cell A, wherein, the first electric current and the second electric current equate, the source electrode of input PMOS pipe P30 accesses described high level vdd, one end of the described current source cell A of drain electrode access, the source ground of input NMOS pipe N30, the other end of the described current source cell A of drain electrode access.
Electric current provides unit also to comprise control tube C0, control tube C0 is located between any two elements on the link that the first power supply (vdd), input PMOS pipe P30, current source cell A, input NMOS pipe N30 and second source (GND) form, comprise be located between input PMOS pipe P30 and current source cell A, between current source cell A and input NMOS pipe N30.The control tube C0 of the present embodiment is arranged between input PMOS pipe P30 and current source cell A.The generation of the first electric current and the second electric current is controlled in the conducting that above-mentioned link in control tube C0 working control simultaneously, also the first control electric current and second is controlled to electric current and plays input control.
It should be noted that, in other embodiments, described the first electric current and the second electric current also can be provided by the first different current source cells and the second current unit respectively.Now, the first power supply (vdd), input PMOS pipe P30, the first current source cell and second source (GND) form the first link; The second current source cell, input NMOS pipe N30 and second source (GND) form the second link.Can pass through the conducting of first control tube control the first link, the conducting of second control tube control the second link.
Said structure can the switching rate of control level shift circuit when high level amplitude is changed, and is specially and slows down switching rate.
Under the prerequisite of such scheme, based on saving the angle of energy consumption, the high level amplitude that the level shift circuit of the present embodiment can also be based on different, selectively provides the first control electric current and second to control electric current, further controls and forbids or control electric current is provided.This design proposal requires to consider based on the required level of memory inside different rates diversified and that level conversion is inputted.Can be according to the difference of the required level numerical value of storer, available level shift circuit high level kind is classified, amplitude is categorized as to the first level higher than the level of threshold value, amplitude is categorized as to second electrical level less than or equal to the level of threshold value, the high level vdd that is Fig. 3 can be the first level, also can be second electrical level, for example, the example of corresponding 90nm high speed Flash storer, can set described threshold value is 5V, when high level is when reading voltage, now the required amplitude 3V that reads voltage can think to belong to second electrical level, and when high level is program voltage, required program voltage 8V can think to belong to the first level.
When high level vdd is the first level, owing to being fast that the first level may cause the voltge surge of the first level to other devices of storer by low transition, thereby input described control electric current for level conversion unit, to slow down level conversion speed;
And when high level vdd is second electrical level, due to reading rate, requiring is that requirement level conversion possesses switching rate faster, and second electrical level can't cause voltge surge to other devices of storer, thereby can stop generation and input described control electric current, and directly by the transistorized electric current that runs through of level conversion unit, realize level conversion, to obtain level conversion speed faster.
Level shifting circuit shown in Fig. 3 is can be according to the kind of described high level and different level conversion demands and can forbid or a kind of physical circuit of controlling electric current is provided level conversion unit:
The electric current of the present embodiment provides in unit:
The first electric current provides unit also to comprise and controls NMOS pipe N50, its drain electrode is connected with the grid of mirror image PMOS pipe P40, control the grid of NMOS pipe N50 and input the first control signal, source electrode input is suitable for making the level of described mirror image PMOS pipe conducting, in the present embodiment, the source electrode of controlling NMOS pipe N50 is connected with described second source, i.e. ground connection.Described the first control signal is suitable for controlling the cut-off of described control NMOS pipe when described the first power supply provides the first level, controls the conducting of described control NMOS pipe when described the first power supply provides second electrical level.
The second electric current provides unit also to comprise and controls PMOS pipe P50, drain electrode is connected with the grid of described mirror image NMOS pipe N40, control the grid of PMOS pipe P50 and input the second control signal, source electrode input is suitable for making the level of described mirror image NMOS pipe conducting, in the present embodiment, the source electrode of controlling PMOS pipe P50 is connected with described the first power supply, accesses high level vdd.Described the second control signal is suitable for controlling the cut-off of described control PMOS pipe when described the first power supply provides the first level, controls the conducting of described control PMOS pipe when described the first power supply provides second electrical level.
To grid input the 3rd control signal of control tube C0, described the 3rd control signal is suitable for when described the first power supply provides the first level, controlling control tube C0 conducting, controls control tube C0 cut-off when described the first power supply provides second electrical level.
Described the first control signal, the second control signal and the 3rd control signal can the different control signals of separate input, also can be as shown in Figure 3, using control signal EN as the second control signal with the 3rd control signal, using the inversion signal ENb of control signal EN as the first control signal.
In other embodiments, can also be as required, electric current is set provides unit only to comprise that the first electric current provides unit or the second electric current that unit is provided:
When electric current provides unit only to comprise that the first electric current provides unit, second source node VL directly connects second source, and what electrical level shift units can the picked up signal output node paramount level conversion speed of low level slows down.The first electric current provides the structure of unit can be with reference to figure 3, and wherein, the first electric current can be provided by current source cell A; Control tube C0 can be located at the first electric current and provide between unit and current source cell A, and by controlling, NMOS manages N50 and control tube C0 control provides the first control electric current.
When electric current provides unit only to comprise that the second electric current provides unit, the first power supply node VH directly meets the first power supply vdd, and electrical level shift units can picked up signal output node high level slowing down to low transition speed.The second electric current provides the structure of unit can be with reference to figure 3, and wherein, the second electric current can be provided by current source cell A; Control tube C0 can be located at the second electric current and provide between unit and current source cell A, and by controlling, PMOS manages P50 and control tube C0 control provides the second control electric current.
It should be noted that; the high level drive end of the each transistor of the present embodiment or element is in order all to access for simplicity described the first power supply; to obtain high level; low level drive end all accesses second source (ground connection); to obtain low level, but in specific implementation process, be appreciated that; if adopt the level input as its drive end of other high level power supplys or low level power, also drop in protection scope of the present invention.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (10)
1. a level shift circuit, is characterized in that, comprising:
Electric current provides unit, is suitable for providing control electric current;
Electrical level shift units, comprises the signal output node that is suitable for inputting the signal input node of the first level signal and is suitable for exporting second electrical level signal; Described electrical level shift units provides unit to be connected with described electric current, is suitable for inputting described control electric current, to control the level conversion speed of described output node.
2. level shift circuit as claimed in claim 1, is characterized in that, described electrical level shift units also comprises the first power supply node and the second source node that is suitable for being connected second source that are suitable for connecting the first power supply; The level value of described second electrical level signal is changed between the level value of the first power supply and the level value of second source.
3. level shift circuit as claimed in claim 2, is characterized in that, described the first power supply is suitable for providing the first level and second electrical level;
Described electric current provides unit to be suitable for when described the first power supply provides described the first level, providing described control electric current, stops providing described control electric current when described the first power supply provides second electrical level.
4. level shift circuit as claimed in claim 2, is characterized in that, described electric current provides unit to provide unit for the first electric current provides unit or the second electric current, or described electric current provides unit to comprise that the first electric current provides unit and the second electric current that unit is provided;
Described the first electric current provides unit to be suitable for providing the first control electric current to described the first power supply node, and described the second electric current provides unit to be suitable for providing the second control electric current to described second source node.
5. level shift circuit as claimed in claim 4, is characterized in that,
Described the first electric current provides unit to comprise the PMOS current mirror consisting of input PMOS pipe and mirror image PMOS pipe, and the source electrode of described mirror image PMOS pipe connects described the first power supply, and the drain electrode of described mirror image PMOS pipe connects described the first power supply node;
Described the second electric current provides unit to comprise the NMOS current mirror consisting of input NMOS pipe and mirror image NMOS pipe, and the source electrode of described mirror image NMOS pipe connects described second source, and the drain electrode of described mirror image NMOS pipe connects described second source node.
6. level shift circuit as claimed in claim 5, is characterized in that,
Described the first electric current provides unit also to comprise and controls NMOS pipe, and its drain electrode is connected with the grid of described mirror image PMOS pipe, and grid is inputted the first control signal, and source electrode input is suitable for making the level of described mirror image PMOS pipe conducting;
Described the second electric current provides unit also to comprise and controls PMOS pipe, and its drain electrode is connected with the grid of described mirror image NMOS pipe, and grid is inputted the second control signal, and source electrode input is suitable for making the level of described mirror image NMOS pipe conducting.
7. level shift circuit as claimed in claim 6, is characterized in that, described the first power supply provides the first level and second electrical level;
Described the first control signal is suitable for controlling the cut-off of described control NMOS pipe when described the first power supply provides the first level, controls the conducting of described control NMOS pipe when described the first power supply provides second electrical level;
Described the second control signal is suitable for controlling the cut-off of described control PMOS pipe when described the first power supply provides the first level, controls the conducting of described control PMOS pipe when described the first power supply provides second electrical level.
8. level shift circuit as claimed in claim 5, is characterized in that, described electric current provides unit to comprise that the first electric current provides unit and the second electric current that unit is provided, and also comprises: current source cell, is connected between described input PMOS pipe and input NMOS pipe.
9. level shift circuit as claimed in claim 8, is characterized in that, described the first power supply provides the first level and second electrical level; Described electric current provides unit also to comprise: control tube, be connected between described current source cell and described input PMOS pipe, or, be connected between described current source cell and described input NMOS pipe;
Grid input the 3rd control signal of described control tube, described the 3rd control signal is suitable for when described the first power supply provides the first level, controlling described control tube conducting, controls described control tube cut-off when described the first power supply provides second electrical level.
10. level shift circuit as claimed in claim 2, it is characterized in that, described signal output node comprises the first output node and the second output node, and described electrical level shift units also comprises a PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 2nd NMOS pipe and phase inverter;
The drain electrode of a described PMOS pipe, the drain electrode of a NMOS pipe are connected described the first output node with the grid of described the 2nd PMOS pipe;
The drain electrode of described the 2nd PMOS pipe, the drain electrode of the 2nd NMOS pipe are connected described the second output node with the grid of a described PMOS pipe;
Described signal input node connects the grid of a described NMOS pipe by described phase inverter, described signal input node connects the grid of described the 2nd NMOS pipe;
The source electrode of a described PMOS pipe is connected described the first power supply node with the source electrode of described the 2nd PMOS pipe;
The source electrode of a described NMOS pipe is connected described second source node with the source electrode of described the 2nd NMOS pipe.
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| CN201410005964.5A CN103730150B (en) | 2014-01-07 | 2014-01-07 | A kind of level shift circuit |
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| CN201410005964.5A CN103730150B (en) | 2014-01-07 | 2014-01-07 | A kind of level shift circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097037A (en) * | 2015-07-17 | 2015-11-25 | 上海华虹宏力半导体制造有限公司 | Reading method of memory device and memory array |
| CN110308759A (en) * | 2018-03-27 | 2019-10-08 | 复旦大学 | A kind of novel level shifter circuit |
| CN115201550A (en) * | 2022-09-16 | 2022-10-18 | 英彼森半导体(珠海)有限公司 | High-voltage input detection circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969554A (en) * | 1997-06-09 | 1999-10-19 | International Business Machines Corp. | Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting |
| US20050007148A1 (en) * | 2003-07-11 | 2005-01-13 | Matsushita Electric Industrial Co., Ltd. | Level shift circuit |
| CN101102082A (en) * | 2006-07-03 | 2008-01-09 | 立锜科技股份有限公司 | Electrical level shift circuit and its method |
| CN101197125A (en) * | 2006-10-17 | 2008-06-11 | 奇景光电股份有限公司 | Level shift circuit and display using same |
| CN101335518A (en) * | 2007-06-29 | 2008-12-31 | 株式会社瑞萨科技 | Semiconductor device |
| US7679420B1 (en) * | 2008-08-28 | 2010-03-16 | Micrel, Incorporated | Slew rate controlled level shifter with reduced quiescent current |
| TW201145827A (en) * | 2010-06-03 | 2011-12-16 | Orise Technology Co Ltd | Level shifter |
-
2014
- 2014-01-07 CN CN201410005964.5A patent/CN103730150B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969554A (en) * | 1997-06-09 | 1999-10-19 | International Business Machines Corp. | Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting |
| US20050007148A1 (en) * | 2003-07-11 | 2005-01-13 | Matsushita Electric Industrial Co., Ltd. | Level shift circuit |
| CN101102082A (en) * | 2006-07-03 | 2008-01-09 | 立锜科技股份有限公司 | Electrical level shift circuit and its method |
| CN101197125A (en) * | 2006-10-17 | 2008-06-11 | 奇景光电股份有限公司 | Level shift circuit and display using same |
| CN101335518A (en) * | 2007-06-29 | 2008-12-31 | 株式会社瑞萨科技 | Semiconductor device |
| US7679420B1 (en) * | 2008-08-28 | 2010-03-16 | Micrel, Incorporated | Slew rate controlled level shifter with reduced quiescent current |
| TW201145827A (en) * | 2010-06-03 | 2011-12-16 | Orise Technology Co Ltd | Level shifter |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097037A (en) * | 2015-07-17 | 2015-11-25 | 上海华虹宏力半导体制造有限公司 | Reading method of memory device and memory array |
| CN110308759A (en) * | 2018-03-27 | 2019-10-08 | 复旦大学 | A kind of novel level shifter circuit |
| CN115201550A (en) * | 2022-09-16 | 2022-10-18 | 英彼森半导体(珠海)有限公司 | High-voltage input detection circuit |
| CN115201550B (en) * | 2022-09-16 | 2022-11-29 | 英彼森半导体(珠海)有限公司 | High-voltage input detection circuit |
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|---|---|
| CN103730150B (en) | 2016-08-17 |
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