CN103714531A - FPGA-based phase correlation method image registration system and method - Google Patents

Abstract

The invention discloses an FPGA-based phase correlation method image registration system and method. The system comprises a kilomega network transmission module, a two dimensional FFT module, a cross-power spectrum calculation module, a two dimensional inverted FFT module, and an extreme value finding module, wherein the kilomega network transmission module is simultaneously connected with the two dimensional FFT module and the extreme value finding module; the two dimensional FFT module is connected with the cross-power spectrum calculation module; the cross-power spectrum calculation module is connected with the two dimensional inverted FFT module; and the two dimensional inverted FFT module is connected with the extreme value finding module. The system and method of the invention are capable of rapidly and accurately conducting image registration pre-treatment during moving targe detection and are characterized by high registration precision and strong instantaneity. The system and method of the invention can leave sufficient time margin for subsequent algorithms.

Description

Phase correlation method figure registration system and method based on FPGA

Technical field

The invention belongs to image registration techniques field, be specifically related to a kind of phase correlation method figure registration system and method based on FPGA.

Background technology

Image registration (Image registration) is exactly the process that two width or multiple image that under different time, different sensors (imaging device) or different condition, (weather, illumination, camera position and angle etc.) are obtained are mated, superposeed, and it has been widely used in the fields such as remotely-sensed data analysis, computer vision, image processing.

Conventional method for registering images has Harris corner correspondence, SIFT feature point extraction matching algorithm and SURF algorithm now, and they complete respectively the coupling of image by extracting the information such as angle point, unique point.But these method for registering images, because algorithm complex is higher, working time is longer, are difficult to requirement of real time for real-time detection tracker.

Document one (Zheng Zhibin, Ye Zhongfu. based on the relevant image registration algorithm of phase place [J]. data acquisition and processing, 2006,21 (4): 445-449.) proposed some algorithms and the improvement about phase place associated picture registration, obtained good effect, but algorithm operation quantity is large, real-time is poor; (state is clear and bright for document two, Li Tiesheng etc. the Design and implementation of the Image Matching Machine based on TMS320C6415 [J], infrared and laser engineering, 2005,34 (4): 482-485.) proposed to utilize TMS320C6415 to complete the method for 512*512 image registration, the time that the method utilizes FFT related algorithm to realize is 0.02s, although the method used time is shorter, but the time of leaving images match in whole search system for is shorter, in 10ms, in this way still can not meet the requirement of search system real-time.

Summary of the invention

The technical matters that the present invention solves is, provide a kind of can be rapidly in moving object detection and accurately carry out the pretreated system and method for image registration, not only can meet the accuracy requirement of registration, also to meet the requirement of real-time, and can leave time enough surplus for subsequent algorithm simultaneously.

For solving the problems of the technologies described above, the present invention proposes a kind of phase correlation method figure registration system based on FPGA, comprises kilomega network transport module, Two-dimensional FFT module, cross-power spectrum computing module, the contrary FFT module of two dimension and extreme value searching module; Kilomega network transport module is found module with Two-dimensional FFT module and extreme value simultaneously and is connected, and Two-dimensional FFT module is connected with cross-power spectrum computing module, and cross-power spectrum computing module is connected with the contrary FFT module of two dimension, and the contrary FFT module of two dimension is found module with extreme value and is connected; Kilomega network transport module receives after the image data packets that computer end sends and unpacks and operate and send the data to Two-dimensional FFT module; Two-dimensional FFT module receives after data and calculates the capable FFT value of one dimension and the one dimension row FFT value that obtains image, sends to cross-power spectrum computing module after trying to achieve the Two-dimensional FFT value of every width image; Cross-power spectrum computing module calculates the cross-power spectrum value of adjacent two width images and sends the data to the contrary FFT module of two dimension after receiving data; The contrary FFT module of two dimension receives calculates the capable value against FFT value and one dimension row against FFT of the one dimension of cross-power spectrum value after data, and the two dimension of trying to achieve cross-power spectrum value sends the data to extreme value searching mould after FFT value; Extreme value is found module and is received the coordinate of finding extreme point after data in the contrary FFT value of two dimension and obtaining this extreme point, and the coordinate of this extreme point is the phase deviation of adjacent two width images, then phase deviation is sent to kilomega network transport module; Kilomega network transport module is convenient to back-end algorithm coupling by phase deviation to computer end.

For solving the problems of the technologies described above, the present invention also proposes a kind of phase correlation method method for registering images based on FPGA, be specially: computer end by camera collection to view data by kilomega network, send on development board, kilomega network module is changed the figure place of view data with fpga chip, calibration data order, splitting datagram, judgement view data is corrected errors, detect UDP message bag frame head, after storing packet into a SRAM storage chip, adjacent two width images are carried out to ping-pong operation, then from a SRAM storage chip, the data with VGA sequential are sent to Two-dimensional FFT module, Two-dimensional FFT module is carried out one dimension FFT conversion to every row pixel of image and every row pixel respectively, the Two-dimensional FFT value of front and back two width images is exported to cross-power spectrum computing module after trying to achieve the Two-dimensional FFT value of every width image, cross-power spectrum computing module first carries out the real part of the Two-dimensional FFT value of front and back two width images and the portion of need multiplying simultaneously and asks modular arithmetic, and then carry out the cross-power spectrum value that division arithmetic obtains adjacent two width images, after the multiple of expansion cross-power spectrum value, with fixed-point number, represent, then send the data to the contrary FFT module of two dimension, the contrary FFT module of two dimension is carried out one dimension to the each row of data of image and every column data respectively and is converted against FFT, tries to achieve the two dimension of cross-power spectrum value after FFT value, and data are exported to extreme point searching module, extreme point is found module the real part of the contrary FFT value of two dimension is carried out to size relatively, search out extreme point and coordinate thereof, according to coordinate corresponding to extreme point, determine the phase deviation of adjacent two width images, then by kilomega network transport module, by being sent to computer end after the packing of image phase off-set value, for back-end algorithm, mate.

The present invention compared with prior art, its remarkable advantage is, (1) the present invention is in conjunction with the logical organization feature of FPGA, adopt serial processing mode to realize phase correlation method, Two-dimensional FFT and the contrary FFT of two dimension are split as to the value of row and column being asked for respectively to one dimension FFT, reduce the calculated amount of algorithm, made algorithm be easy to realize; (2) in the present invention, original image size is reduced, data in process are represented with fixed-point number, simultaneously precision is higher owing to calling the built-in FFT-IP core of development board and solve FFT, so the overall system error of calculation is little, can realize preferably the compensation to background, and it is less affected by illumination variation etc.; (3) in the present invention, by SRAM storage chip is divided into a plurality of storage areas, reduced the resources occupation rate of algorithm in development board, for subsequent algorithm provides larger spatial margin; (4) because this algorithm adopts pure hardware to realize, so data transmission rate is fast, fast operation, real-time is good, and efficiency is high, for subsequent algorithm provides larger time margin.

Accompanying drawing explanation

Fig. 1 is the phase correlation method figure registration system modular structure schematic diagram that the present invention is based on FPGA.

Fig. 2 is the phase correlation method figure registration system detailed structure schematic diagram that the present invention is based on FPGA.

Fig. 3 is the phase correlation method figure registration system Two-dimensional FFT rear end SRAM control structure figure that the present invention is based on FPGA.

Fig. 4 is the Two-dimensional FFT implementation method the present invention is based in the phase correlation method method for registering images of FPGA.

Fig. 5 the present invention is based on cross-power spectrum value calculation process in the phase correlation method method for registering images of FPGA.

Embodiment

As shown in Figure 1, the phase correlation method figure registration system based on FPGA, comprises kilomega network transport module, Two-dimensional FFT module, cross-power spectrum computing module, the contrary FFT module of two dimension and extreme value searching module; Kilomega network transport module is found module with Two-dimensional FFT module and extreme value simultaneously and is connected, and Two-dimensional FFT module is connected with cross-power spectrum computing module, and cross-power spectrum computing module is connected with the contrary FFT module of two dimension, and the contrary FFT module of two dimension is found module with extreme value and is connected; Kilomega network transport module receives after the image data packets that computer end sends and unpacks and operate and send the data to Two-dimensional FFT module; Two-dimensional FFT module receives after data and calculates the capable FFT value of one dimension and the one dimension row FFT value that obtains image, sends to cross-power spectrum computing module after trying to achieve the Two-dimensional FFT value of every width image; Cross-power spectrum computing module calculates the cross-power spectrum value of adjacent two width images and sends the data to the contrary FFT module of two dimension after receiving data; The contrary FFT module of two dimension receives calculates the capable value against FFT value and one dimension row against FFT of the one dimension of cross-power spectrum value after data, and the two dimension of trying to achieve cross-power spectrum value sends the data to extreme value searching mould after FFT value; Extreme value is found module and is received the coordinate of finding extreme point after data in the contrary FFT value of two dimension and obtaining this extreme point, and the coordinate of this extreme point is the phase deviation of adjacent two width images, then phase deviation is sent to kilomega network transport module; Kilomega network transport module is convenient to back-end algorithm coupling by phase deviation to computer end.

As shown in Figure 2, Two-dimensional FFT module can be comprised of the capable FFT computing module of one dimension and one dimension row FFT computing module; The contrary FFT module of two dimension can form against FFT computing module and the contrary FFT computing module of one dimension row by one dimension is capable.The capable FFT computing module of one dimension, one dimension row FFT computing module, one dimension are capable all can be realized by being invoked at the built-in Fast Fourier Transform (FFT) FFT-IP core of development board against FFT computing module and the contrary FFT computing module of one dimension row, and Fast Fourier Transform (FFT) FFT-IP core is data without compression, pipeline organization.

As shown in Figure 2, between kilomega network transport module and the capable FFT computing module of one dimension, be connected with a SRAM storage chip, between the capable FFT computing module of one dimension and one dimension row FFT computing module, be connected with the 2nd SRAM storage chip, between one dimension row FFT computing module and cross-power spectrum computing module, be connected with Three S's RAM storage chip, between the contrary FFT computing module of FFT computing module and one dimension row, be connected with the 4th SRAM storage chip one dimension is capable, an and SRAM storage chip, the 2nd SRAM storage chip, Three S's RAM storage chip and the 4th SRAM storage chip are the external form of development board.

Further, enough in order to guarantee precision of the present invention, must adopt the data of enough bit wides, therefore to the access rate of Three S's RAM storage chip, to increase, so the present invention also adopts three fifo buffer FIFO that data processing section and storage area sequential are separated, and guarantees the real-time of algorithm.As shown in Figure 3, between Three S's RAM storage chip and one dimension row FFT computing module, be also connected with the first fifo buffer FIFO, between Three S's RAM storage chip and cross-power spectrum computing module, be also connected in parallel to the second fifo buffer FIFO and the 3rd fifo buffer FIFO; Three S's RAM storage chip has four storage area block1, block2, block3 and block4, block1 is for storing the real part of the front piece image Two-dimensional FFT value of adjacent two width images, block2 is for storing the imaginary part of the front piece image Two-dimensional FFT value of adjacent two width images, block3 is for storing the real part of the rear piece image Two-dimensional FFT value of adjacent two width images, and block4 is for storing the imaginary part of the rear piece image Two-dimensional FFT value of adjacent two width images.

Phase correlation method method for registering images based on FPGA, is specially:

Computer end by camera collection to view data by kilomega network, send on development board, kilomega network module is changed the figure place of view data with the built-in fifo buffer of fpga chip, calibration data order, splitting datagram, judgement view data is corrected errors, detect UDP message bag frame head, adjacent two width images are carried out to ping-pong operation after storing packet into a SRAM storage chip, then from a SRAM storage chip, the data with VGA sequential are sent to Two-dimensional FFT module;

As shown in Figure 4, Two-dimensional FFT module is carried out one dimension FFT conversion to every row pixel of image and every row pixel respectively, the Two-dimensional FFT value of front and back two width images is exported to cross-power spectrum computing module after trying to achieve the Two-dimensional FFT value of every width image;

Cross-power spectrum computing module first carries out the real part of the Two-dimensional FFT value of front and back two width images and the portion of need multiplying simultaneously and asks modular arithmetic, and then carry out the cross-power spectrum value that division arithmetic obtains adjacent two width images, after the multiple of expansion cross-power spectrum value, with fixed-point number, represent, then send the data to the contrary FFT module of two dimension;

The contrary FFT module of two dimension is carried out one dimension to the each row of data of image and every column data respectively and is converted against FFT, tries to achieve the two dimension of cross-power spectrum value after FFT value, and data are exported to extreme point searching module;

Extreme point is found module the real part of the contrary FFT value of two dimension is carried out to size relatively, search out extreme point and coordinate thereof, according to coordinate corresponding to extreme point, determine the phase deviation of adjacent two width images, then by kilomega network transport module, by being sent to computer end after the packing of image phase off-set value, for back-end algorithm, mate.

As shown in Figure 3, the one dimension row FFT-IP core in Two-dimensional FFT module is input to the first fifo buffer FIFO by the Two-dimensional FFT value of asking for acquisition, and then the first fifo buffer FIFO enters data into Three S's RAM storage chip; The real part of piece image Two-dimensional FFT value before the storage area block1 of Three S's RAM storage chip stores in adjacent two width images, the imaginary part of piece image Two-dimensional FFT value before storage area block2 stores in adjacent two width images, the real part of piece image Two-dimensional FFT value after storage area block3 stores in adjacent two width images, the imaginary part of piece image Two-dimensional FFT value after storage area block4 stores in adjacent two width images; During Three S's RAM storage chip output data, after its storage area block1 and block2 output data, merge and be input to the second fifo buffer FIFO; After storage area block3 and block4 output data, merge and be input to the 3rd fifo buffer FIFO; Then after the second fifo buffer FIFO and the 3rd fifo buffer FIFO output data, walk abreast and be input to cross-power computing module.

Division arithmetic described in cross-power spectrum computing module is realized by the built-in division IP kernel of development board.

Embodiment

The hardware platform that the present embodiment is realized: the FPGA development board that the xc5vfx30t-2ff665 of XINLINX company of take is master chip, 4 external SRAM storage chips, gigabit network interface, AD chip, algorithm verilog language description, programming and emulation complete on ISE13.1.

Kilomega network transport module:

Computer end by camera collection to video data by kilomega network network interface, send on Virtex-5 development board, the video image size sending because of computer end is 640*480 form, for the ease of kilomega network, send data, computer end is packaged into every two row data the UDP message bag of 1280 bytes, and before each frame data, has added that frame head is as the sign of differentiating image.

Shown in Fig. 1, kilomega network transport module receives the video flowing that computer end passes over, the data-signal receiving because of kilomega network transport module is 4 bit image data, so be converted into 16 bit data by fifo buffer FIFO read-write, carry out large small end conversion simultaneously, again UDP message bag is unpacked and processed and detect CRC check code, correct if CRC check yardage is calculated, the data of 1280 bytes of two row are outputed to a SRAM storage chip and carry out buffer memory.

Before and after supposing, two width images are f ₁(x, y), f ₂(x, y), the data of exporting due to kilomega network transport module are 8, and a SRAM storage chip FPDP is 16, for saving resource, first utilize fifo buffer FIFO read-write to transfer 8 bit data of kilomega network transport module output to 16 bit data, then judge the frame head of every width image.If determine frame head, respectively by image f ₁(x, y), f ₂(x, y) deposits in two storage block block1 of a SRAM storage chip and block2 and carries out ping-pong buffer.Meanwhile, according to the requirement of back-end algorithm, utilize 27M clock by row, to read the data in a SRAM storage chip according to sequencing, there are the data of VGA sequential, for back-end algorithm module.

Two-dimensional FFT module:

The image size of coming due to front end is 640*480 form, and Two-dimensional FFT module carry out FFT while calculating data length be all 2 integral number power, so need intercept image.Because of in the process of actual photographed video, the phase deviation of adjacent two width images is less, and image interception is a little bit smaller also can retain offset information, so the present invention selects truncated picture size, is 256*256.Afterwards the image after the intercepting of every width is carried out to one dimension FFT value and calculate, computing formula is,

$x\left[k\right]={\mathrm{\Σ}}_{n=0}^{N-1}x\left[n\right]W_N^{\mathrm{nk}},$

Wherein, x[n] be input image data, x[k] be the value after view data one dimension FFT conversion, N is that the length of one dimension FFT conversion is 256, W _n=e ^{-j2 π/N}for twiddle factor.

In the present invention, all to adopt the built-in FFT-IP of development board to examine existing for one dimension FFT, and be data without compressing, pipeline organization, enable signal fwd_inv is set to high level 1.

Because the capable FFT-IP core input of one dimension data acquiescence is all signed number, so being unified to a high position, input data add sign bit 0, and when using FFT-IP core, enable signal start is that the upper clock before data is to a pulse signal in input, and last output is the capable FFT value of image one dimension.

Due to two width image f ₁(x, y) and f ₂(x, y) successively arrives, so need to be input in the 2nd SRAM storage chip and carry out buffer memory the capable FFT value of one dimension.Value due to the capable FFT-IP core output of one dimension before buffer memory is 18 bit data, so it is compressed, 9 of data shift rights, the real part re of the capable FFT value of one dimension of the image of then the capable FFT-IP core of one dimension being tried to achieve and imaginary part im are spliced into 16 bit data and store to the 2nd SRAM storage chip by row.

As shown in Figure 4, image f ₁(x, y) and image f ₂the capable FFT value of one dimension of (x, y) stores to by row respectively in two the storage block block1 and block2 in the 2nd SRAM storage chip, then they is carried out to ping-pong operation simultaneously, presses respectively row sense data, is input in one dimension row FFT-IP core.

What one dimension row FFT-IP core was selected is 8 inputs, and without compressive flow line structure, enable signal fwd_inv is set to high level 1, and output is 17.While considering the output of first order row FFT-IP core result, data have been compressed, if the data of one dimension row FFT-IP core output are compressed again, the corresponding accumulation of error meeting, so the output valve of one dimension row FFT-IP core has only been omitted most significant digit (16 of actual observation just enough represent).As shown in Figure 3, before each operation, to judge the enable signal dv of one dimension row FFT-IP core output, when dv is 1, be that data are when effective, by 32 bit data that 27M clock is combined into 16 real part re of one dimension row FFT-IP core output and 16 imaginary part im, write in the first fifo buffer FIFO, according to actual threshold value, with 54M, read the data in the first fifo buffer FIFO simultaneously.If image f ₁the Two-dimensional FFT value of (x, y) (being previous image 1), is stored in the real part re of Two-dimensional FFT value and imaginary part im respectively in the block1 and block2 in Three S's RAM storage chip; If image f ₂the Two-dimensional FFT value of (x, y) (image 2), is stored in the real part re of Two-dimensional FFT value and imaginary part im respectively in the block3 and block4 in Three S's RAM storage chip; When dv is 0, according to the front and back order of the image of storing in Three S's RAM storage chip, first by row, read image f in Three S's RAM storage chip ₁the Two-dimensional FFT value of (x, y), simultaneously by image f ₁the real part of the Two-dimensional FFT value of (x, y) and imaginary part store in the second fifo buffer FIFO by 16, then by row, read image f in Three S's RAM storage chip ₂the Two-dimensional FFT value of (x, y), simultaneously by image f ₂the real part of the Two-dimensional FFT value of (x, y) and imaginary part store in the 3rd fifo buffer FIFO with 16.When counting variable rd_data_count is greater than certain threshold value in the second fifo buffer FIFO and the 3rd fifo buffer FIFO, with 27M clock, data are read by 32, be input to cross-power spectrum computing module.

Cross-power computing module:

What the second fifo buffer FIFO and the 3rd fifo buffer FIFO exported respectively is the Two-dimensional FFT value of 32 of front and back two width images, is respectively F ₁(u, v) and F ₂(u, v), they are all to represent with plural form.

Suppose F ₁(u, v)=a+ib, F ₂(u, v)=c+id,

first obtain F ₁(u, v) and F ₂the conjugation product of (u, v):

$F_1(u,v){\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">F</figure-callout>}}_2^{*}(u,v)=(a+\mathrm{ib})(c-\mathrm{id})=(\mathrm{ac}+\mathrm{bd})+i(\mathrm{bc}-\mathrm{ad})$

As shown in Figure 5, the result of above-mentioned conjugation product can be decomposed into the real part (ac+bd) of minute asking for conjugation product value and the value of imaginary part (bc-ad), be that abbreviation becomes a series of multiplication and additive operation, the parallel multiplication result of asking for ac, bd, bc, ad, then utilize additive operation, try to achieve F ₁(u, v) and F ₂the conjugation product value of (u, v).The conjugation product value obtaining at verilog Hardware description language, calls the turn and can directly carry out multiplying by after the variable-definition multiplying each other in multiplication is signed number, so can be expressed as real part re and the imaginary part im of 32.

Obtain conjugation product value after, conjugation product value is asked to modular arithmetic.While asking mould value, adopt CORDIC vector iterative algorithm, this algorithm replaces multiplying by basic adding with shift operation, complete rectangular coordinate to polar conversion, make the functions such as the rotation of vector and the calculating of direction no longer need square, evolution, anti-triangle, also compare to call and ask mould IP kernel to save a lot of FPGA resources.The present embodiment is tried to achieve conjugation product by 16 iteration $F_1(u,v){\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">F</figure-callout>}}_2^{*}(u,v)$ Mould value, error is in 0.1% left and right.

After trying to achieve mould value, according to following spectral density formula, ask for cross-spectral density value:

${\mathrm{<figure-callout\; id="2"\; label="e\; j"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">e</figure-callout>}}^j=\frac{F_1(u,v){{\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">F</figure-callout>}}_2}^{*}(u,v)}{\left|F_1(u,v){{\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">F</figure-callout>}}_2}^{*}(u,v)\right|},$

F wherein ₁(u, v) is image f ₁the Two-dimensional FFT value of (x, y),

image f ₂value after the conjugater transformation of the Two-dimensional FFT value of (x, y),

with F ₂the conjugation product value of (u, v),

for the mould value of conjugation product value, e ^{j2 π (ux0+vy0)}for cross-spectral density value.

So use conjugation product value

the real part re of 32 and imaginary part im respectively except in conjugation product value

mould value, can try to achieve cross-spectral density value.

Division adopts the built-in division IP kernel instrument of Virtex-5 development board to realize, thereby and the size of 2 the spread spectrum density values that when being divided by, the real part re on molecule and imaginary part im all moved to right, the spectral density value of trying to achieve is like this more accurate.

The contrary FFT module of two dimension:

With Two-dimensional FFT module class seemingly, advanced every trade, against FFT computing, then, by value boil down to 8 bit data of the contrary FFT of row, then stores in the 4th SRAM storage chip according to pingpong theory, from the 4th SRAM storage chip sense data, be listed as again contrary FFT computing, finally try to achieve the contrary FFT value of two dimension.

Extreme value is found module:

According to the inverse transformation formula of Two-dimensional FFT: $\mathrm{\&delta;}(x-x_0,y-y_0)={\mathrm{\&zeta;}}^{-1}\left[\frac{F_1(u,v){{\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">F</figure-callout>}}_2}^{*}(u,v)}{\left|F_1(u,v){{\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000430378160000021.png"\; state="\{\{state\}\}">F</figure-callout>}}_2}^{*}(u,v)\right|}\right],$ (x in (x, y) space ₀, y ₀) locate to form an impulse function δ (x-x ₀, y-y ₀).Therefore,, in the matrix of consequence after the contrary FFT inverse transformation of two dimension, the real part of element in matrix is searched for successively, and by relatively maximizing, the corresponding coordinate of maximal value is the displacement that will calculate so.And then utilize kilomega network module that displacement is exported, for the processing of subsequent algorithm.

It is as shown in table 1 that the present embodiment FPGA resource consumption takies situation.As can be seen from Table 1, it is 63% that the relevant registration arrangement of phase place of the present invention consumes sheet register resources on FPGA, and it is only 39% that internal RAM takies resource.Show that native system takies FPGA resource-constrained, the resource space area of a room that can supply with back-end algorithm is larger; The rare inner cabling of FPGA that is beneficial to of resource consumption simultaneously, stability that can the operation of assurance program, improves the robustness of algorithm.

The present embodiment FPGA each several part data bit width is as shown in table 2.As can be seen from Table 2, this is to invent according to internal data actual size situation, is reasonably provided with the fixed-point number bit wide of modules, is not only conducive to the storage of each SRAM and the calculating of data, can guarantee the precision of algorithm, and be conducive to save storage resources and the logical resource of hardware simultaneously.

Table 1 embodiment hardware platform FPGA resource consumption takies situation

Resource classification	Use	Available	Utilization factor
				Slice	13086	20480	63%
Slice?LUTs	12440	20480	60%
				IOBs	234	360	65%
BlockRAM/FIFO	27	68	39%

Table 2 the present embodiment FPGA each several part data bit width

Data	Bit wide
		Kilomega network module output data	8 unsigned numbers
One dimension FFT inputs data	9 signed numbers
		One dimension FFT exports data	18 signed numbers
Two-dimensional FFT input data	8 signed numbers
		Two-dimensional FFT output data	17 signed numbers
Ask mould module input data	20 signed numbers
		Division module output data	20 signed numbers
One dimension is inputted data against FFT	8 signed numbers
		The contrary FFT output of two dimension data	17 signed numbers
Extreme value module output data	8 signed numbers

Claims (8)

1. the phase correlation method figure registration system based on FPGA, is characterized in that comprising kilomega network transport module, Two-dimensional FFT module, cross-power spectrum computing module, the contrary FFT module of two dimension and extreme value searching module; Kilomega network transport module is found module with Two-dimensional FFT module and extreme value simultaneously and is connected, and Two-dimensional FFT module is connected with cross-power spectrum computing module, and cross-power spectrum computing module is connected with the contrary FFT module of two dimension, and the contrary FFT module of two dimension is found module with extreme value and is connected; Kilomega network transport module receives after the image data packets that computer end sends and unpacks and operate and send the data to Two-dimensional FFT module; Two-dimensional FFT module receives after data and calculates the capable FFT value of one dimension and the one dimension row FFT value that obtains image, sends to cross-power spectrum computing module after trying to achieve the Two-dimensional FFT value of every width image; Cross-power spectrum computing module calculates the cross-power spectrum value of adjacent two width images and sends the data to the contrary FFT module of two dimension after receiving data; The contrary FFT module of two dimension receives calculates the capable value against FFT value and one dimension row against FFT of the one dimension of cross-power spectrum value after data, and the two dimension of trying to achieve cross-power spectrum value sends the data to extreme value searching module after FFT value; Extreme value is found module and is received the coordinate of finding extreme point after data in the contrary FFT value of two dimension and obtaining this extreme point, and the coordinate of this extreme point is the phase deviation of adjacent two width images, then phase deviation is sent to kilomega network transport module; Kilomega network transport module is convenient to back-end algorithm coupling by phase deviation to computer end.

2. the phase correlation method figure registration system based on FPGA as claimed in claim 1, is characterized in that, Two-dimensional FFT module comprises the capable FFT computing module of one dimension and one dimension row FFT computing module; The contrary FFT module of two dimension comprises that one dimension is capable of FFT computing module and the contrary FFT computing module of one dimension row.

3. the phase correlation method figure registration system based on FPGA as claimed in claim 2, it is characterized in that, the capable FFT computing module of one dimension, one dimension row FFT computing module, one dimension are capable all to be realized by being invoked at the built-in Fast Fourier Transform (FFT) FFT-IP core of development board against FFT computing module and the contrary FFT computing module of one dimension row, and Fast Fourier Transform (FFT) FFT-IP core is data without compression, pipeline organization.

4. the phase correlation method figure registration system based on FPGA as claimed in claim 2, it is characterized in that, between the capable FFT computing module of kilomega network transport module and one dimension, be connected with a SRAM storage chip, between the capable FFT computing module of one dimension and one dimension row FFT computing module, be connected with the 2nd SRAM storage chip, between one dimension row FFT computing module and cross-power spectrum computing module, be connected with Three S's RAM storage chip, one dimension is capable is connected with the 4th SRAM storage chip between FFT computing module and the contrary FFT computing module of one dimension row, an and SRAM storage chip, the 2nd SRAM storage chip, Three S's RAM storage chip and the 4th SRAM storage chip are the external form of development board.

5. the phase correlation method figure registration system based on FPGA as claimed in claim 4, it is characterized in that, between Three S's RAM storage chip and one dimension row FFT computing module, be connected with the first fifo buffer FIFO, between Three S's RAM storage chip and cross-power spectrum computing module, be connected in parallel to the second fifo buffer FIFO and the 3rd fifo buffer FIFO; Three S's RAM storage chip has four storage area block1, block2, block3 and block4, block1 is for storing the real part of the front piece image Two-dimensional FFT value of adjacent two width images, block2 is for storing the imaginary part of the front piece image Two-dimensional FFT value of adjacent two width images, block3 is for storing the real part of the rear piece image Two-dimensional FFT value of adjacent two width images, and block4 is for storing the imaginary part of the rear piece image Two-dimensional FFT value of adjacent two width images.

6. the phase correlation method method for registering images based on FPGA, be characterised in that, computer end by camera collection to view data by kilomega network, send on development board, kilomega network transport module is changed the bit wide of view data, then calibration data sequentially, splitting datagram, judgement view data is corrected errors, detect UDP message bag frame head, then after storing packet into a SRAM storage chip, adjacent two width images are carried out to ping-pong operation, then from a SRAM storage chip, the data with VGA sequential are sent to Two-dimensional FFT module;

Two-dimensional FFT module is carried out one dimension FFT conversion to every row pixel of image and every row pixel respectively, the Two-dimensional FFT value of front and back two width images is exported to cross-power spectrum computing module after trying to achieve the Two-dimensional FFT value of every width image;

Cross-power spectrum computing module first carries out the real part of the Two-dimensional FFT value of front and back two width images and imaginary part multiplying simultaneously and asks modular arithmetic, and then carry out the cross-power spectrum value that division arithmetic obtains adjacent two width images, after the multiple of expansion cross-power spectrum value, with fixed-point number, represent, then send the data to the contrary FFT module of two dimension;

The contrary FFT module of two dimension is carried out one dimension to the each row of data of image and every column data respectively and is converted against FFT, tries to achieve the two dimension of cross-power spectrum value after FFT value, and data are exported to extreme point searching module;

Extreme point is found module the real part of the contrary FFT value of two dimension is carried out to size relatively, search out extreme point and coordinate thereof, according to coordinate corresponding to extreme point, determine the phase deviation of adjacent two width images, then by kilomega network transport module, by being sent to computer end after the packing of image phase off-set value, for back-end algorithm, mate.

7. the phase correlation method method for registering images based on FPGA, be characterised in that, one dimension row FFT-IP core in Two-dimensional FFT module is input to the first fifo buffer FIFO by the Two-dimensional FFT value of asking for acquisition, and then the first fifo buffer FIFO enters data into Three S's RAM storage chip; The real part of piece image Two-dimensional FFT value before the storage area block1 of Three S's RAM storage chip stores in adjacent two width images, the imaginary part of piece image Two-dimensional FFT value before storage area block2 stores in adjacent two width images, the real part of piece image Two-dimensional FFT value after storage area block3 stores in adjacent two width images, the imaginary part of piece image Two-dimensional FFT value after storage area block4 stores in adjacent two width images; During Three S's RAM storage chip output data, after its storage area block1 and block2 output data, merge and be input to the second fifo buffer FIFO; After storage area block3 and block4 output data, merge and be input to the 3rd fifo buffer FIFO; Then after the second fifo buffer FIFO and the 3rd fifo buffer FIFO output data, walk abreast and be input to cross-power computing module.

8. the phase correlation method method for registering images based on FPGA, is being characterised in that, division arithmetic described in cross-power spectrum computing module is realized by the built-in division IP kernel of development board.

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