CN103713960A

CN103713960A - Watchdog circuit used for embedded system

Info

Publication number: CN103713960A
Application number: CN201210378479.3A
Authority: CN
Inventors: 胡喜; 卓越
Original assignee: Siemens Power Automation Ltd
Current assignee: Siemens Power Automation Ltd
Priority date: 2012-09-29
Filing date: 2012-09-29
Publication date: 2014-04-09
Anticipated expiration: 2032-09-29
Also published as: CN103713960B

Abstract

The invention provides a watchdog circuit used for embedded system. The circuit comprises a watchdog unit (210), an awakening signal generating unit (220), and an awakening control unit (240). The awakening signal generating unit (220) responds an enable signal (S2) to selectively select awakening clock signals (S1) or normal awakening signals (S4) from a system (SYS) as awakening signals (S5) to send to the watchdog unit (210). The awakening control unit (240) is generated in a system starting time frame (T1) as the enable signal 9S2) with effective value. The awakening signal generating unit (220) takes the awakening clock signals (S1) as the awakening signals (S5) to send to the watchdog unit (210) when the enable signal (S2) is in effect.

Description

Watchdog circuit for embedded system

Technical field

The present invention relates in general to embedded hardware system, relates in particular to the watchdog circuit using in a kind of embedded hardware system.

Background technology

House dog (Watchdog, be called for short WD) is actually a kind of timer, is generally used for monitoring whether normal operation of program in software systems or embedded hardware system.If the program of system is normally moved, system can (or claim the WD overtime time limit (t that resets at the predetermined amount of time of WD institute timing _wD)) in to WD, send and to wake (waking) signal (being commonly called as " feeding dog (feeding) " signal) (for example, negative edge or rising edge) up, WD is resetted and reclocking.On the contrary, if system fails to send in time wake-up signal because of program mal in this WD resets the overtime time limit, WD can send reset signal because of its timer expired, thus forced system restart, with this, prevent system in case of system halt or enter endless loop.

Generally, WD can realize with hardware, also can realize with software.Fig. 1 exemplarily shows the hard-wired situation of WD in embedded hardware system.In Fig. 1, WD is a hardware timing chip (for example MAX6366 or similarly WD chip), its input end WDI receives the wake-up signal S4 from an I/O interface (or expansion I/O interface of system SYS) of system SYS, and its output terminal RST is connected to the reset terminal RESET of system SYS.The upper operation of embedded hardware system SYS has application program, and application program burning for example, in storage unit (flash).In application program, include what is called and wake code up, its periodically (in WD resets the overtime time limit) from the I/O interface of system SYS to WDI, end sends effective wake-up signal S4.When the wake-up signal S4 of WDI end is effective, WD resets and reclocking, the RST end output invalid signals of WD.On the contrary, if the wake-up signal of WDI end is lasting invalid, cause WD overtime, RST end output effective reset signal, for example, maintain a reset cycle (t _rP) low level.The effective reset signal of RST end can make system SYS restart, thereby anti-locking system enters abnormality, such as entering endless loop or race flies.

In Fig. 1, overtime in order to prevent WD, in each the different program segment in the application program that need to move on system SYS, all need to embed for waking the code that wakes up of WD up.System SYS carries out this at every turn and wakes code up, all can send effective wake-up signal S4 by the WDI end from its I/O mouth to WD, thereby guarantee that WD is not overtime.If the program on system SYS occurs abnormal, cannot move in time and wake code up, and cause thus WD overtime, and then system SYS is forced to restart.

When system SYS starts or restarts, that is, before the application program operation on system SYS, system SYS can experience a system guiding and system initialization process, and this process is referred to as system starting process.System starting process need to continue the several seconds conventionally, is generally longer than the WD timeout period of existing WD chip this start-up time.Therefore,, if do not send wake-up signal in system starting process, system will be restarted because WD is overtime always, finally cause system to start unsuccessfully.

For resolution system, the WD between the starting period wakes problem up, and existing a solution is in the bottom functional module of system, also to embed WD to wake code up.For example, will wake code up is embedded in guiding-load module, driver, operating system initialization module etc.Yet, in actual applications, such as the bottom functional module of driver, conventionally by supplier independently, provided, generally application developer does not need not have ability to revise the code of bottom functional module yet, because revise the mistake that bottom functional module probably causes bottom function, and increase the unnecessary workload of application layer developer.

Consider this point, in prior art, also need a kind ofly can realize Hardware Implementation and the device that WD wakes up without the bottom function of revising system SYS.

Summary of the invention

It is a kind of for the solution at embedded hardware system house dog (WD) that one object of the present invention is to provide.Adopt this scheme, system between the starting period WD still can be waken up, and without embed extra code in system bottom function.

According to one aspect of the invention, the present invention proposes a kind of circuit that is used as house dog in embedded hardware system, comprising: watchdog unit, it starts timing after powering on or in response to effective wake-up signal of input, and to after date, export a reset signal in the overtime time limit of watchdog reset; Wake-up signal generation unit, optionally will wake clock signal up or as described wake-up signal, be fed to described watchdog unit from the normal wake-up signal of system in response to an enable signal; Wake control module up, produce the described enable signal for described wake-up signal generation unit, described enable signal is arranged in system and starts the period for effective; Wherein, the described cycle of waking clock and normal wake-up signal up is shorter than the overtime time limit of described watchdog reset; and described wake-up signal generation unit is when described enable signal is effective, wakes clock signal up and be fed to described watchdog unit as described wake-up signal described in making.Preferably, described in wake control module up in response to the reset signal from described watchdog unit, and generate described enable signal.More preferably, to start the period be about 1 minute for described system.Particularly preferably, described in wake control module up and comprise a single timer, in response to described reset signal, system of timing starts the period for it.

In one embodiment of the invention, preferably, described enable signal (S2) is also effective value in the firmware renewal period of embedded hardware system.

In one embodiment of the invention, when described enable signal is high level when effective, described wake-up signal generation unit comprises: Sheffer stroke gate, to described enable signal and described in wake clock up and carry out NAND Logic operation, and generate the first M signal; Or door, described enable signal and described normal wake-up signal are carried out or logical operation, and produced the second M signal; With door, described the first and second M signals are carried out and logical operation, thereby obtained described wake-up signal.Preferably, wherein, described in wake control module up and also comprise configuration circuit, it is set to effective value by described enable signal in described firmware upgrades the period.More preferably, described configuration circuit comprises wire jumper.

Except the WD circuit proposing according to the present invention, also preferably can upgrade the same WD of maintenance of period at firmware not overtime.And, for firmware upgrades the period, without increasing extra wake-up circuit or wake-up signal, and be only by change wire jumper, i.e. the more switching between new model of feasible system start-up mode and firmware.

With reference to the detailed description to various embodiments of the present invention below in conjunction with accompanying drawing, above-mentioned aspect of the present invention and advantage will become more apparent clear.

Accompanying drawing explanation

The following drawings is only intended to the present invention to schematically illustrate and explain, not delimit the scope of the invention.Wherein,

Fig. 1 is the schematic diagram of the existing WD for embedded hardware system;

Fig. 2 is the block diagram of WD circuit according to an embodiment of the invention;

Fig. 3 is the schematic diagram of WD circuit in accordance with another embodiment of the present invention;

Fig. 4 A is the oscillogram of each signal in system starting process of circuit shown in Fig. 2, Fig. 3;

Fig. 4 B is the oscillogram of each signal in firmware renewal process of circuit shown in Fig. 2, Fig. 3.

Fig. 5 is the schematic diagram of the WD circuit of another embodiment according to the present invention;

Fig. 6 wakes the signal waveforms in control module 540 up in circuit shown in Fig. 5.

Embodiment

For technical characterictic of the present invention, object and effect being had more clearly, understand, now contrast accompanying drawing explanation the specific embodiment of the present invention.

In view of the defect of the watchdog circuit shown in Fig. 1, the present inventor has proposed a kind of novel house dog (WD) circuit.This WD circuit can be carried effective wake-up signal to WD chip automatically system SYS startup period (or preferably also upgrading period at firmware), not overtime to maintain WD, and after application program adapter system on system SYS, continuing the wake-up signal S4 that code produces on the I/O of system SYS mouth of waking up in application program, to maintain WD not overtime.

Fig. 2 exemplarily shows the block diagram of WD Rouser 200 according to an embodiment of the invention.As shown in Figure 2, WD Rouser 200 comprises WD unit 210, wake-up signal generation unit 220, wakes clock 230 up and wakes control module 240 up.Shown in the structure of WD unit 210 and principle of work and Fig. 1, WD is similar.The input end of WD unit 210 receives the effective wake-up signal S5 from unit 220.If WD210 is because failing to receive that in time wake-up signal S5 is overtime, a reset signal S8 of its output terminal RST output is to system SYS, and with forced system, SYS is restarted.Wake-up signal generation unit 220 has two input ends, and one is connected to and wakes clock 230 up, for receiving the clock signal of one-period, being called, wakes clock S1 up.The WD that the cycle of waking clock S1 up is shorter than WD 210 overtime time limit that resets.Another is connected in an I/O output of system SYS, the normal wake-up signal S4 sending for receiving system SYS normal operation period.Wake-up signal generation unit 220 is controlled by and wakes control module 240 up.Waking control module 240 up and 220 provide enable signal S2 to unit, is to wake clock S1 up or using normal wake-up signal S4 as S5, to be fed to the input end of WD 210 for controlling wake-up signal generation unit 220.For example, in system, between the starting period or firmware reproducting periods, waking up under the control of control module 240, waking clock S1 up and offer WD 210 as S5, and at system SYS normal operation period, normal wake-up signal S4 is offered to WD 210 as S5.Thus, before application program adapter system SYS, can wake WD 210 up by waking clock up, keep WD not overtime, thereby without embedding and wake code up in the bottom functional module at system SYS, just can realize waking up of WD by hardware.

Fig. 3 exemplarily shows the specific embodiment of of block diagram shown in Fig. 2.In WD circuit 300 shown in Fig. 3, WD 210 is same as shown in Figure 2, repeats no more here.Waking clock 330 up is the clock-signal generator of a standard, the WD that its clock period is shorter than WD 210 overtime time limit that resets.Wake-up signal generation unit 320 specifically comprise with non-(NAND) door 321 or (OR) door 323 and with (AND) door 325.Wake control module 340 up and produce enable signal S2, in order to control wake-up signal generation unit 320.Enable signal S2 and wake clock S1 up and send into Sheffer stroke gate 321, the output S3 that the two obtains after NAND Logic computing sends into and door 325.Meanwhile, from the normal wake-up signal S4 of the I/O interface of SYS with enable signal S2 sends into or door 323, the two through or logical operation after the output S7 that obtains also send into and door 325.S3 and S7 obtain sending into the wake-up signal S5 of WD 210 after AND-operation.Wherein, when enable signal S2 is effective, wakes clock S1 up and be used as S5 and send into WD 210.When enable signal S2 is invalid, normal wake-up signal S4 sends into WD 210 as S5.Fig. 3 only exemplarily shows the situation that adopts logic gate to realize wake-up signal generation unit 320.In practical application, unit 320 can also adopt other logics to realize, and is not limited to the situation shown in Fig. 3.

Fig. 4 A and Fig. 4 B show respectively in system the oscillogram of S1, S2, S3, S7 and S5 between the starting period and in firmware reproducting periods Fig. 3.Fig. 4 A shows in system startup situation the oscillogram of each point in the WD circuit shown in Fig. 3.As shown in Figure 4 A, wake the t1 that clock S1 powers on from system SYS up and constantly start to export a series of clock signals.The t1 that enable signal S2 powers on from system SYS starts to be set to effectively constantly, after system has started (or while being called application program adapter system, t2 constantly) be set to invalid.In other words, enable signal S2 system between the starting period (t1 is to t2) be an effective pulse, pulse width T 1 is greater than system and starts required time.S1 and S2 obtain signal S3 after NOT-AND operation.S3 only at T1(t1 to t2) in comprise and periodically wake clock signal up.Normal wake-up signal S4 has started (t2 constantly) in system be non-existent before.S4 only just wakes the normal wake-up signal of code generating period at t2 up constantly because of system SYS execution.S4 and S2 through or operation after obtain signal S7.From S7, S7 becomes as available normal wake-up signal only started (t2 constantly) in system after.So, S3 and S7 make to obtain being fed to after AND-operation the wake-up signal S5 of WD 210.As seen from the figure, S5 was the signal identical with waking clock S1 up at t2 constantly, and t2 is the signal identical with normal wake-up signal S4 constantly.Like this, the whole process of system operation that powers on from system, all there is wake-up signal to send into WD 210, make the WD can be because of overtime resetting system SYS.

Fig. 4 B shows under firmware update status the oscillogram of each point in the WD Rouser shown in Fig. 3.For embedded hardware system, the application program burning of the upper operation of system SYS is in the storage unit of for example FLASH, each application program of upgrading need to first be downloaded for application program, then downloaded application program is burnt in FLASH, then restarts system SYS.This process is generally longer, needs several minutes.For this reason, different from Fig. 4 A, in Fig. 4 B, in the whole process that firmware upgrades (from t3 to t4, i.e. T2), enable signal S2 continuously effective.Meanwhile, due to any application program of off-duty in T2, thereby normal wake-up signal S4 does not exist in T2.Thus, the wake-up signal S5 obtaining according to structure shown in Fig. 3 is the clock signal identical with S1 all the time in the cycle T 2 from t3 to t4.After firmware renewal finishes, SYS can be restarted, and correspondingly according to the waveform shown in Fig. 4 A, exports wake-up signal S5 to WD 210.

In Fig. 3 and Fig. 4, enable signal S2 can obtain in several ways.For example, enable signal S2 can be realized by a timer.System power on or restart after this timer start timing, and export high level, and for example, after predetermined amount of time (T1) output low level.When firmware upgrades beginning, S2 can be set to effective value and upgrade and finish postposition for invalid at firmware.According to the actual requirements, those skilled in the art can select suitable circuit structure to obtain enable signal S2 in conjunction with common circuit.

Fig. 5 exemplarily shows a kind of concrete WD circuit 500.As shown in Figure 5, WD circuit 500 comprises WD chip U1, starts wake-up signal generation circuit 520, wakes clock 530 and wake-up control circuit 540 up.In Fig. 5, what WD chip U1 adopted is MAX6366 chip, and on other markets, available WD chip all can be used as U1 certainly.The WDI end of WD chip U1 is input end, and RST end is output terminal.The principle of work of WD chip U1 is identical with the WD 210 mentioning before.In addition, wake-up signal produce circuit 530 specifically comprise Sheffer stroke gate U5 or door U6 and with door U4, its structure and principle of work are identical with the wake-up signal generation circuit 330 shown in Fig. 3.Here, for WD chip and wake-up signal generation circuit 530, all repeat no more.

Different from Fig. 3 structure, wake-up control circuit 540 comprises a single timer 543, for example 555 conventional serial timers.In Fig. 5, the effective trigger pip receiving in response to trigger end TR, timer 543 is at a monopulse with preset width of its output end vo output.The broadband T1 of monopulse can determine by resistance R 1, capacitor C 2, T1=1.1*R1*C2.In the embodiment of Fig. 5, T1 is configured to be greater than real system and starts the required time, and for example T1 is arranged to general one minute.

In the example shown in Fig. 5, WD chip U1 is at Vcc during higher than reset threshold or when because of overtime reset, and its output RST maintains the low level of a reset cycle, as shown in first waveform in Fig. 6.And the trigger end TR of single timer 543 is rising edge triggering.For this reason, increased phase inverter U2 and carried out the RST negate to U1, thereby effective RST has been converted into for the same effectively trigger pip of timer 543.Fig. 6 shows the oscillogram of the output TR of output RST, U2 and the output Vo of timer (being control signal S2) of U1.As shown in Figure 6, after system SYS powers on, the RST of U1 is maintaining the low level of a reset cycle.Correspondingly, phase inverter U2 is to RST negate, thus the pulse of a forward of formation.Direct impulse on TR triggers timer 543 and starts timing, thereby timer 543 forms an effective impulse that pulsewidth is T1 at its output end vo, and this pulse can be used as enable signal S2, is used for controlling wake-up signal according to mode shown in Fig. 3 and produces circuit 520.

In the example shown in Fig. 5, circuit 500 has two kinds of mode of operations.Mode of operation is a system start-up mode, and another kind is more new model of firmware, and the differentiation of these two kinds of patterns can realize by configuration circuit.In the example of Fig. 5, configuration circuit is the wire jumper X1 waking up in control module 540.Particularly, under system start-up mode, 3 ends of wire jumper X1 and 2 end short circuits.Like this, the output S6 of timer 543, just as enable signal S2, is used for controlling wake-up signal and produces circuit 520.Thus, in system starting process, clock signal S1 can be fed to the input end of WD chip U1 automatically, not overtime to guarantee WD.The waveform of each signal under this mode of operation as shown in Figure 4 A.At firmware more under new model, 1 end of wire jumper X1 and 2 end short circuits, wherein 1 end is connected to Vcc.At firmware more in new stage T2, clock signal S1 can be fed to the input end WDI of WD chip U1 automatically, not overtime to guarantee WD like this.At firmware, upgrade to finish and before system restarts, then wire jumper is changed to 2-3 short circuit from 1-2 short circuit.The waveform of each signal under this mode of operation as shown in Figure 4 B.

Although realize the switching of two kinds of different modes with wire jumper in Fig. 5, those skilled in the art can also select other modes to realize this switching in actual use.For example, a hardware switch is set, when firmware upgrades beginning, hardware switch makes control signal S2 be set to high level, and when firmware upgrades end, control signal S2 is set to the output terminal that is connected to timer 543.

Be to be understood that, although this instructions is described according to each embodiment, but not each embodiment only comprises an independently technical scheme, this narrating mode of instructions is only for clarity sake, those skilled in the art should make instructions as a whole, technical scheme in each embodiment also can, through appropriately combined, form other embodiments that it will be appreciated by those skilled in the art that.

The foregoing is only the schematic embodiment of the present invention, not in order to limit scope of the present invention.Any those skilled in the art, not departing from equivalent variations, modification and the combination of doing under the prerequisite of design of the present invention and principle, all should belong to the scope of protection of the invention.

Claims

1. in embedded hardware system, be used as a circuit for house dog, comprise:

Watchdog unit (210, U1), it starts timing after powering on or in response to effective wake-up signal (S5) of input, and at the overtime time limit (t of watchdog reset _wD) to after date, output one reset signal (S8);

Wake-up signal generation unit (220,320,520), in response to an enable signal (S2) optionally using wake up clock signal (S1) or from the normal wake-up signal (S4) of system (SYS) as described wake-up signal (S5) be fed to described watchdog unit (210, U1);

Wake control module (240,340,540) up, produce the described enable signal (S2) for described wake-up signal generation unit, described enable signal (S2) is arranged in system and starts the period (T1) for effective;

Wherein, the described cycle of waking clock (S1) and normal wake-up signal (S4) up is shorter than the overtime time limit of described watchdog reset; and described wake-up signal generation unit (220,320,520) is at described enable signal (S2) effectively time, described in making, wakes clock signal (S1) up and be fed to described watchdog unit (210, U1) as described wake-up signal (S5).

2. circuit as claimed in claim 1, wherein, described in wake control module (540) up in response to the reset signal from described watchdog unit (U1), and generate described enable signal (S2).

3. circuit as claimed in claim 1, wherein, the unloading phase of described system, (T1) is about 1 minute.

4. circuit as claimed in claim 2, wherein, described in wake control module (540) up and comprise a single timer, it is corresponding to described reset signal (S8) and system of timing starts the period (T1).

5. as the circuit as described in arbitrary in claim 1-4, wherein, it is effective value that described enable signal (S2) also upgrades the period (T2) at the firmware of embedded hardware system.

6. circuit as claimed in claim 1, wherein, when described enable signal (S2) is high level when effective, described wake-up signal generation unit (320,520) comprising:

Sheffer stroke gate (321, U5), to described enable signal (S2) and described in wake clock (S1) up and carry out NAND Logic operation, and generate the first M signal (S3);

Or door (323, U6), described enable signal (S2) and described normal wake-up signal (S4) are carried out or logical operation, and produced the second M signal (S7);

With door (325, U4), described the first and second M signals (S3, S7) are carried out and logical operation, thereby are obtained described wake-up signal (S5).

7. circuit as claimed in claim 5, wherein, described in wake control module (540) up and also comprise configuration circuit (X1), it is set to described enable signal (S2) effectively in described firmware upgrades the period (T2).

8. circuit as claimed in claim 7, wherein said configuration circuit comprises wire jumper (X1).