CN103713960B - Watchdog circuit for embedded system - Google Patents
Watchdog circuit for embedded system Download PDFInfo
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- CN103713960B CN103713960B CN201210378479.3A CN201210378479A CN103713960B CN 103713960 B CN103713960 B CN 103713960B CN 201210378479 A CN201210378479 A CN 201210378479A CN 103713960 B CN103713960 B CN 103713960B
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Abstract
The present invention proposes a kind of circuit for being used as house dog in embedded hardware system.The circuit includes：Watchdog unit（210）；Wake-up signal generation unit（220）, it is in response to an enable signal（S2）And it will optionally wake up clock signal（S1）Or from system（SYS）Normal wakeup signal（S4）As the wake-up signal（S5）It is fed to the watchdog unit（210）；Wake up control unit（240）, produce and start the period in system（T1）The interior enable signal for virtual value（S2）；Wherein, the wake-up signal generation unit（220）In the enable signal（S2）When effective so that the wake-up clock signal（S1）As the wake-up signal（S5）It is fed to the watchdog unit（210）.
Description
Technical field
This patent disclosure relates generally to the house dog used in embedded hardware system, more particularly to a kind of embedded hardware system
Circuit.
Background technology
House dog（Watchdog, abbreviation WD）Actually a kind of timer, be generally used for monitor a software systems or
Program in embedded hardware system whether normal operation.If the normal program operation of system, system can be counted in WD
When predetermined amount of time（Or WD resets timeouts（tWD））Interior sent to WD wakes up（waking）Signal（It is commonly called as " feeding dog
（feeding）" signal）（For example, trailing edge or rising edge）So that WD resets and reclocking.If on the contrary, resetted in the WD
System fails to send wake-up signal in time because of program mal in timeouts, then WD can send reset letter because of its timer expired
Number, so as to force system reboot, system in case of system halt is prevented or into endless loop with this.
Generally, WD can be realized with hardware, can also be realized with software.Fig. 1 is schematically illustrated
The hard-wired situations of WD in embedded hardware system.In Fig. 1, WD is a hardware timing chip（Such as MAX6366 or
The similar WD chips of person）, an I/O interface of its input WDI receptions from system SYS（Or system SYS expansion I/O
Interface）Wake-up signal S4, its output end RST is connected to system SYS reset terminal RESET.Transported on embedded hardware system SYS
Row has application program, and application program burning is in memory cell（Such as flash）In.Include so-called wake-up generation in application program
Code, it can be periodically（Resetted in WD in timeouts）From system SYS I/O interfaces effective wake-up is sent to WDI ends
Signal S4.When the wake-up signal S4 at WDI ends is effective, WD resets and reclocking, WD RST ends output invalid signals.On the contrary,
That if the wake-up signal at WDI ends continues is invalid, causes WD overtime, RST ends output effective reset signal, such as maintains a reset
Cycle（tRP）Low level.The effective reset signal at RST ends enables to system SYS to restart, so as to which anti-locking system enters exception
State, for example into endless loop or run winged.
In Fig. 1, in order to prevent WD time-out, it is necessary to each different journey in the application program run on system SYS
The embedded wake-up code for being used to wake up WD is both needed in sequence section.System SYS performs the wake-up code every time, all can from its I/O mouth to
WD WDI ends send effective wake-up signal S4, so as to ensure that WD is not overtime.If there is exception in the program on system SYS,
Wake-up code can not be run in time, and thus causes WD overtime, and then system SYS is forced to restart.
When system SYS starts or restarted, i.e. before the application program operation on system SYS, system SYS can undergo one
Individual System guides and system initialization process, this process are referred to as system starting process.System starting process usually requires to hold
Continuous several seconds, this startup time are generally longer than the WD timeout periods of existing WD chips.Therefore, if in system starting process not
Wake-up signal is sent, then system will restart always because of WD time-out, ultimately result in system and start failure.
WD to solve between system startup wakes up problem, and existing a solution is the bottom function mould in system
Also WD is embedded in block and wakes up code.For example, code will be waken up, to be embedded into guiding-load module, driver, operating system initial
In change module etc..However, in actual applications, the bottom functional module of such as driver generally by independent supplier Lai
There is provided, generally application developer need not also have no ability to change the code of bottom functional module, because modification
Bottom functional module likely results in the mistake of bottom function, and increases the unnecessary workload of application layer developer.
Can be real in consideration of it, also needing to a kind of bottom function that can need not change system SYS in the prior art
The Hardware Implementation and device that existing WD wakes up.
The content of the invention
It is an object of the present invention to provide one kind to be used for the house dog in embedded hardware system（WD）Solution party
Case.Using this scheme, WD can be still waken up between system startup, without embedded extra in system bottom function
Code.
According to one aspect of the invention, the present invention proposes a kind of electricity for being used as house dog in embedded hardware system
Road, including：Watchdog unit, it starts timing after the power-up or in response to effective wake-up signal of input, and in house dog
After reset timeouts expire, a reset signal is exported；Wake-up signal generation unit, the selectivity in response to an enable signal
Wake-up clock signal or the normal wakeup signal from system are fed to the house dog list by ground as the wake-up signal
Member；Control unit is waken up, produces the enable signal for the wake-up signal generation unit, the enable signal is arranged to
It is effective in the system startup period；Wherein, the cycle of the wake-up clock and normal wakeup signal is shorter than the watchdog reset
Timeouts, and the wake-up signal generation unit is when the enable signal is effective so that and the wake-up clock signal is made
The watchdog unit is fed to for the wake-up signal.Preferably, the wake-up control unit from described in response to guarding the gate
The reset signal of dog unit, and generate the enable signal.It is further preferable that it is about 1 minute that the system, which starts the period,.Especially
For preferably, the wake-up control unit includes a single timer, its in response to the reset signal and timing one is
System starts the period.
In an embodiment of the invention, it is preferable that the enable signal（S2）Also in the firmware of embedded hardware system
The renewal period is virtual value.
In an embodiment of the invention, when the enable signal is that high level is effective, the wake-up signal produces single
Member includes：NAND gate, NAND Logic operation is performed to the enable signal and the wake-up clock, and generate and believe among first
Number；OR gate, to the enable signal and the normal wakeup signal performs or logical operation, and produces second M signal；With
Door, to first and second M signal execution and logical operation, so as to obtain the wake-up signal.Preferably, wherein, institute
Stating wake-up control unit also includes configuration circuit, and the enable signal is set to virtual value by it within the firmware renewal period.
It is further preferable that the configuration circuit includes wire jumper.
Except according to WD circuits proposed by the present invention, preferably can equally keep WD not surpass in the firmware renewal period
When.Moreover, for firmware updates the period, without increasing extra wake-up circuit or wake-up signal, and merely by more
Change wire jumper, you can realize the switching between system start-up mode and firmware generation patterns.
With reference to the detailed description below in conjunction with accompanying drawing to various embodiments of the present invention, aforementioned aspect of the present invention and advantage will
Become apparent from understanding.
Brief description of the drawings
The following drawings is only intended to, in doing schematic illustration and explanation to the present invention, not delimit the scope of the invention.Wherein,
Fig. 1 is the existing WD being used in embedded hardware system schematic diagram；
Fig. 2 is the block diagram of WD circuits according to an embodiment of the invention；
Fig. 3 is the schematic diagram of WD circuits in accordance with another embodiment of the present invention；
Fig. 4 A are the oscillograms of each signal in system starting process of circuit shown in Fig. 2, Fig. 3；
Fig. 4 B are the oscillograms of each signal in firmware renewal process of circuit shown in Fig. 2, Fig. 3.
Fig. 5 is the schematic diagram according to the WD circuits of another embodiment of the invention；
Fig. 6 is that the signal waveforms in control unit 540 are waken up in circuit shown in Fig. 5.
Embodiment
In order to which technical characteristic, purpose and the effect of the present invention is more clearly understood, now control illustrates this hair
Bright embodiment.
In view of the defects of watchdog circuit shown in Fig. 1, the present inventor proposes a kind of new house dog
（WD）Circuit.This WD circuits can start the period in system SYS（Or preferably also update the period in firmware）Automatically WD cores are given
Piece conveys effective wake-up signal, to maintain WD not overtime, and after the application program adapter system on system SYS, continues
By wake-up code in application program, caused wake-up signal S4 maintains WD not overtime on system SYS I/O mouths.
Fig. 2 schematically illustrates the block diagram of WD Rousers 200 according to an embodiment of the invention.As shown in Fig. 2
WD Rousers 200 include WD units 210, wake-up signal generation unit 220, wake up clock 230 and wake up control unit
240.The structure and operation principle of WD units 210 are similar with WD shown in Fig. 1.The input of WD units 210 receives and comes from unit 220
Effective wake-up signal S5.If WD210 receives wake-up signal S5 and overtime, its output end RST outputs in time because failing
One reset signal S8 gives system SYS, to force system SYS to be restarted.Wake-up signal generation unit 220 has two inputs,
One, which is connected to, wakes up clock 230, for receiving the clock signal of a cycle, referred to as wakes up clock S1.Wake up clock S1
Cycle be shorter than WD 210 WD reset timeouts.In another I/O outputs for being connected to system SYS, it is for receiving
The normal wakeup signal S4 that system SYS is sent during normal operation.Wake-up signal generation unit 220 is controlled by wake-up control unit
240.Wake up control unit 240 and provide enable signal S2 to unit 220, be to call out for controlling wake-up signal generation unit 220
Awake clock S1 or the input that WD 210 is fed to using normal wakeup signal S4 as S5.For example, between system startup or
Firmware reproducting periods, in the case where waking up the control of control unit 240, wake up clock S1 and be supplied to WD 210 as S5, and in system
SYS is supplied to WD 210 using normal wakeup signal S4 as S5 during normal operation.Thus, in application program adapter system SYS
Before, WD 210 can be waken up by wake-up clock, keeps WD not overtime, without in system SYS bottom functional module
It is embedded to wake up code, it is possible to WD wake-up is realized by hardware.
Fig. 3 schematically illustrates the specific embodiment of one of block diagram shown in Fig. 2.In WD circuits 300 shown in Fig. 3,
WD 210 is same as shown in Figure 2, repeats no more here.Wake up the clock-signal generator that clock 330 is a standard, its clock
The WD that cycle is shorter than WD 210 resets timeouts.Wake-up signal generation unit 320 specifically include with it is non-（NAND）Door 321 or
（OR）Door 323 and with（AND）Door 325.Wake up control unit 340 and produce enable signal S2, to control wake-up signal to produce
Unit 320.Enable signal S2 and wake-up clock S1 are sent into NAND gate 321, the two output S3 obtained after NAND Logic computing
It is sent into and door 325.Meanwhile the normal wakeup signal S4 and enable signal S2 of the I/O interfaces from SYS are sent into OR gate 323, the two
Through or logical operation after obtained output S7 be also fed into and door 325.S3 and S7 obtains that WD 210 can be sent into after with operation
Wake-up signal S5.Wherein, when enable signal S2 is effective, wakes up clock S1 and be sent into WD 210 as S5.Enable signal S2 without
During effect, normal wakeup signal S4 is sent into WD 210 as S5.Fig. 3 is exemplarily only shown wakes up letter using gate to realize
The situation of number generation unit 320.In practical application, unit 320 can also be realized using other logics, and be not limited to Fig. 3 institutes
Situation about showing.
Fig. 4 A and Fig. 4 B respectively illustrate S1, S2, S3, S7 and S5 between system startup and in firmware reproducting periods Fig. 3
Oscillogram.Fig. 4 A show the oscillogram of each point in the WD circuits in the case of system starts shown in Fig. 3.As shown in Figure 4 A,
Wake up clock S1 and export a series of clock signals since the t1 moment of electricity on system SYS.Enable signal S2 is electric from system SYS
The t1 moment start to be set to effectively, after system start completion（Or when making application program adapter system, i.e. t2 moment）It is set to
To be invalid.In other words, enable signal S2 is between system startup（T1 to t2）For an effective pulse, pulse width T1 is more than
The time required to system starts.S1 and S2 obtains signal S3 after NOT-AND operation.S3 is only in T1（T1 to t2）It is interior to include periodically
Wake up clock signal.Normal wakeup signal S4 is in system start completion（The t2 moment）It is not present before.S4 is only at the t2 moment
Just generate periodic normal wakeup signal because system SYS is performed and waken up code afterwards.S4 and S2 are passed through or are obtained letter after operating
Number S7.From S7, S7 is only in system start completion（The t2 moment）After be turned into available normal wakeup signal.In this way, S3 and
Both S7 make to obtain being fed to WD 210 wake-up signal S5 after with operation.As seen from the figure, S5 is before the t2 moment
With waking up clock S1 identical signals, it is and normal wakeup signal S4 identical signals after the t2 moment.So, from system
Electricity makes WD not reset system SYS because of time-out to there is during the entire process of system operation wake-up signal to be sent into WD 210.
Fig. 4 B show the oscillogram of each point in WD Rousers under firmware update status shown in Fig. 3.For insertion
For formula hardware system, in such as FLASH memory cell, renewal every time should for the application program burning run on system SYS
Need first to download for application program with program, then application downloaded is burnt in FLASH, then restart system
SYS.This process is general longer, it is necessary to several minutes.Therefore, unlike Fig. 4 A, in figure 4b, the whole mistake of firmware renewal
Journey（From t3 to t4, i.e. T2）In, enable signal S2 continuously effectives.Simultaneously as any application program of off-duty in T2, thus just
Normal wake-up signal S4 is not present in T2.Thus, the wake-up signal S5 obtained according to structure shown in Fig. 3 is in the cycle from t3 to t4
It is all the time in T2 and S1 identical clock signals.After firmware renewal terminates, SYS can restart, and correspondingly according to shown in Fig. 4 A
Waveform export wake-up signal S5 to WD 210.
Enable signal S2 can be obtained in several ways in figs. 3 and 4.For example, enable signal S2 can be by one
Individual timer is realized.The system electrification or timer starts timing after restarting, and high level is exported, and in predetermined amount of time
（Such as T1）After export low level.When firmware updates beginning, S2 can be asserted value and terminate in firmware renewal rearmounted
To be invalid.According to the actual requirements, those skilled in the art can combine the suitable circuit structure of common circuit selection to be made
Can signal S2.
Fig. 5 schematically illustrates a kind of specific WD circuits 500.As shown in figure 5, WD circuits 500 include WD chips U1,
Start wake-up signal generation circuit 520, wake up clock 530 and wake-up control circuit 540.In Figure 5, WD chips U1 is used
It is MAX6366 chips, certain available WD chips of other in the markets can be employed as U1.WD chips U1 WDI ends are input,
RST ends are output end.WD chips U1 operation principle is identical with the WD 210 referred to before.In addition, wake-up signal generation circuit
530 specifically include NAND gate U5, OR gate U6 and are produced with door U4, its structure and operation principle and the wake-up signal shown in Fig. 3
Circuit 330 is identical.Here, repeated no more for WD chips and wake-up signal generation circuit 530.
Unlike Fig. 3 structures, wake-up control circuit 540 includes a single timer 543, such as conventional 555
Serial timer.In Figure 5, the effective trigger signal received in response to triggering end TR, timer 543 are defeated in its output end vo
Go out a pulse with preset width.The broadband T1 of pulse can be determined by resistance R1, electric capacity C2, T1=1.1*
R1*C2.In the 5 embodiment of figure 5, T1 is configured to be more than the time needed for real system startup, such as T1 is arranged to general one
Minute.
In the example as shown in fig. 5, for WD chips U1 when Vcc is higher than reset threshold or when being resetted because of time-out, its is defeated
Go out the low level that RST maintains a reset cycle, as shown in first waveform in Fig. 6.And the triggering end TR of single timer 543
Triggered for rising edge.Therefore, phase inverter U2 is added to be negated to U1 RST, so as to which effective RST is converted into for timing
543 equally valid trigger signal of device.Fig. 6 shows that U1 output RST, U2 output TR and the output Vo of timer (is controlled
Signal S2 processed) oscillogram.As shown in fig. 6, on system SYS after electricity, U1 RST is maintaining the low level of a reset cycle.
Correspondingly, phase inverter U2 negates to RST, so as to form a positive pulse.Direct impulse triggering timer 543 on TR is opened
Beginning timing, so as to which timer 543 forms the effective impulse that a pulsewidth is T1 in its output end vo, this pulse, which can be used as, to be made
Energy signal S2, for controlling wake-up signal generation circuit 520 according to mode shown in Fig. 3.
In the example as shown in fig. 5, circuit 500 has two kinds of mode of operations.A kind of mode of operation is system start-up mode,
Another kind is firmware generation patterns, and the differentiation of both patterns can be realized by configuration circuit.In the example of fig. 5, configure
Circuit is the wire jumper X1 in wake-up control unit 540.Specifically, under system start-up mode, wire jumper X1 3 ends and 2 end short circuits.
So, the output S6 of timer 543 is just used as enable signal S2, for controlling wake-up signal generation circuit 520.Thus, it is being
In start-up course of uniting, clock signal S1 can be automatically fed to WD chips U1 input, to ensure that WD is not overtime.This work
The waveform of each signal under pattern is as shown in Figure 4 A.Under firmware generation patterns, wire jumper X1 1 end and 2 end short circuits, wherein 1 end
It is connected to Vcc.So in firmware more in new stage T2, clock signal S1 can be automatically fed to WD chips U1 input WDI,
To ensure that WD is not overtime.Update and terminate and before system reboot in firmware, then wire jumper is changed to 2-3 short circuits from 1-2 short circuits.This
The waveform of each signal under one mode of operation is as shown in Figure 4 B.
Although the switching of two kinds of different modes is realized with wire jumper in Figure 5, in actual use art technology
Personnel are also an option that other modes realize this switching.For example, a hardware switch is set, the hardware when firmware updates beginning
Switch causes control signal S2 to be set to high level, and is set to control signal S2 at the end of firmware updates and is connected to timer
543 output end.
It should be appreciated that although this specification is described according to each embodiment, not each embodiment only includes one
Individual independent technical scheme, this narrating mode of specification is only that those skilled in the art will should say for clarity
Bright book is as an entirety, and the technical solutions in the various embodiments may also be suitably combined, and forming those skilled in the art can be with
The other embodiment of understanding.
The schematical embodiment of the present invention is the foregoing is only, is not limited to the scope of the present invention.It is any
Those skilled in the art, equivalent variations, modification and the combination made on the premise of the design of the present invention and principle is not departed from,
The scope of protection of the invention all should be belonged to.
Claims (7)
1. a kind of circuit for being used as house dog in embedded hardware system, including：
Watchdog unit (210, U1), it starts timing after the power-up or in response to effective wake-up signal (S5) of input, and
In watchdog reset timeouts (tWD) expire after, export a reset signal (S8)；
Wake-up signal generation unit (220,320,520), clock will be optionally waken up in response to an enable signal (S2)
Signal (S1) or normal wakeup signal (S4) from system (SYS) are fed to described as the effectively wake-up signal (S5)
Watchdog unit (210, U1)；
Control unit (240,340,540) is waken up, produces the enable signal (S2) for the wake-up signal generation unit,
It is effective that the enable signal (S2), which is arranged in system startup period (T1),；
Wherein, when the cycle of the wake-up clock signal (S1) and normal wakeup signal (S4) is shorter than the watchdog reset time-out
Limit, and the wake-up signal generation unit (220,320,520) is when the enable signal (S2) is effective so that the wake-up
Clock signal (S1) is fed to the watchdog unit (210, U1) as the effectively wake-up signal (S5)；
When the enable signal (S2) is that high level is effective, the wake-up signal generation unit (220,320,520) includes：
NAND gate (321, U5), NAND Logic operation is performed to the enable signal (S2) and the wake-up clock signal (S1),
And generate first M signal (S3)；
OR gate (323, U6), to the enable signal (S2) and the normal wakeup signal (S4) performs or logical operation, and raw
Produce second M signal (S7)；
With door (325, U4), first and second M signal (S3, S7) is performed and logical operation, so as to obtain described having
Imitate wake-up signal (S5).
2. circuit as claimed in claim 1, wherein, the wake-up control unit (240,340,540) is in response to from described
The reset signal of watchdog unit (210, U1), and generate the enable signal (S2).
3. circuit as claimed in claim 1, wherein, the system started the period (T1) as 1 minute.
4. circuit as claimed in claim 2, wherein, the wake-up control unit (240,340,540) is determined including a single
When device, its corresponding to the reset signal (S8) and one system of timing starts the period (T1).
5. the circuit as described in any in claim 1-4, wherein, the enable signal (S2) is also in embedded hardware system
Firmware renewal period (T2) is virtual value.
6. circuit as claimed in claim 5, wherein, the wake-up control unit (240,340,540) also includes configuration circuit,
The enable signal (S2) is set to effectively by it in firmware renewal period (T2).
7. circuit as claimed in claim 6, wherein the configuration circuit includes wire jumper (X1).
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| CN201210378479.3A CN103713960B (en) | 2012-09-29 | 2012-09-29 | Watchdog circuit for embedded system |
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| CN201210378479.3A CN103713960B (en) | 2012-09-29 | 2012-09-29 | Watchdog circuit for embedded system |
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| CN103713960B true CN103713960B (en) | 2017-11-14 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106873943B (en) * | 2017-01-12 | 2020-01-17 | 深圳市优必选科技有限公司 | Firmware upgrading method of embedded system |
| CN111400074A (en) * | 2019-01-02 | 2020-07-10 | 珠海格力电器股份有限公司 | Watchdog simulating device and control method thereof |
| CN112433589B (en) * | 2020-10-30 | 2022-11-01 | 天津航空机电有限公司 | Double-margin DSP anti-reset locking circuit |
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|---|---|---|---|---|
| US5513319A (en) * | 1993-07-02 | 1996-04-30 | Dell Usa, L.P. | Watchdog timer for computer system reset |
| CN2519335Y (en) * | 2001-12-24 | 2002-10-30 | 华为技术有限公司 | Controlling logic circuit of gate keeper dog |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN101165656A (en) * | 2006-10-16 | 2008-04-23 | 艾默生网络能源系统有限公司 | External watchdog circuit |
-
2012
- 2012-09-29 CN CN201210378479.3A patent/CN103713960B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5513319A (en) * | 1993-07-02 | 1996-04-30 | Dell Usa, L.P. | Watchdog timer for computer system reset |
| CN2519335Y (en) * | 2001-12-24 | 2002-10-30 | 华为技术有限公司 | Controlling logic circuit of gate keeper dog |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN101165656A (en) * | 2006-10-16 | 2008-04-23 | 艾默生网络能源系统有限公司 | External watchdog circuit |
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