CN103701412A - Circuit for realizing high and low power of linear power amplifier by taking CMOS (complementary metal-oxide-semiconductor) transistors as switches - Google Patents
Circuit for realizing high and low power of linear power amplifier by taking CMOS (complementary metal-oxide-semiconductor) transistors as switches Download PDFInfo
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Abstract
The invention provides a circuit for realizing high and low power of a linear power amplifier by taking CMOS (complementary metal-oxide-semiconductor) transistors as switches. The circuit comprises a high-power module, a medium-low-power module and an output matching network circuit II. The medium-low-power module comprises a matching network circuit II, a power amplifier II, a secondary matching network circuit and a CMOS transistor II. The matching network circuit II, the power amplifier II and the secondary matching network circuit are sequentially connected in series. A drain electrode of the CMOS transistor II is connected at the joint of the power amplifier II and the matching network circuit II. A grid electrode of the CMOS transistor II is connected with the voltage output end of a control circuit II. A source electrode of the CMOS transistor II is grounded. Two CMOS transistors severing as the switches are integrated in a CMOS bare chip used for providing stable bias voltage, the implementation method is simple, and production cost is reduced greatly; due to the CMOS transistor switches, mutual interference between high-power portions and medium-low-power portions is eliminated, matching networks are simplified, and efficiency of the power amplifier during lower-power working is improved.
Description
Technical field
The present invention relates to communication technique field, especially a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier.
Background technology
In the handheld device of 3G communication system, in order to meet code requirement, generally all need to use in a large number linear PA to be power amplifier, below referred to as power amplifier.These systems are except linear requirement, and also efficient requirement, represents with PAE conventionally.Because transmitting power most of the time of handheld device is operated in 0dBm left and right, fewer in the time of maximum power output, in order to make handheld device power saving as far as possible, need the efficiency of transmitting power linear PA when 0dBm left and right higher.In order to meet this requirement, linear PA has three kinds of mode of operations conventionally: high-power mode, middle power mode and low-power mode.Under high-power mode, power output is between 17dBm to 28dBm, and the power output of middle power and low-power mode is below 17dBm.Conventionally when maximum power output, the efficiency of PA can reach 35% to more than 40%, and along with the reduction of power, efficiency also decreases; When being reduced to 17dBm left and right, if be not switched to middle power mode, efficiency will be in 5% left and right, and after being switched to low-power mode, efficiency can be brought up to 20% left and right.In like manner in power output, at 8dBm, be switched to low-power mode, efficiency also can continue to improve under middle power mode, therefore can allow handheld device power saving more.
The basic framework of the modules of handheld device on transmitting chain is shown in Fig. 4; the input signal of PA module (power amplifier module) is provided by transceiver as seen from the figure; and Vref(or VEN) and the control level such as Vmode by baseband chip, provided; between the output of PA module and antenna, conventionally have duplexer or switch, add in addition some matching networks.According to 3G system specifications, handheld device reaches 23dBm or 24dBm in the maximum power of antenna end, the insertion loss of deduction duplexer or switch, linear PA roughly arrives 27dBm at 26dBm in the maximum power of handheld device, and the peak power output of transceiver generally at 0dBm between 3dBm, so linear PA needs roughly 25dB left and right just can reach the output of maximum power at high power; In like manner, handheld device can be-49dBm at the minimum power of antenna end, and middle power mode switches roughly in 17dBm left and right, and the minimum output power of transceiver need to deduct the gain of the middle low-power mode of linear PA on the basis of-49dBm.Therefore in order to guarantee the dynamic range of transceiver, the gain of middle power mode lower linear PA can not be too high, and generally, in 18dB left and right, in order to guarantee the power stage of switching point, the gain of middle power mode can not be lower than 14dB.
Yet in the Linear Power Amplifier using at present, during lower powered realization, generally have three kinds of methods, the first is to reduce bias voltage, such as the nude film by CMOS in Fig. 3 is adjusted to 2.70V by bias voltage from 2.85V.Driving stage and power stage are still in running order, because the reduction of bias voltage causes the reduction of gain and the raising of efficiency, but the efficiency of middle low-power mode still can be lower, gain simultaneously under low-power only, than the little several decibels of high-power gain, is therefore had higher requirement to the dynamic range of transceiver, the second is the mode of the patent US7394313 that explains of Fig. 5 under middle low-power mode, the power stage of Linear Power Amplifier is closed, and using driving stage output as middle low-power mode by switching network, but input and output due to this network connection power output stage, therefore under high-power mode, need to guarantee that under high-power mode, this network does not have impact substantially on whole power stage, guarantee the stability under high-power mode, efficiency, and linearity, and power output stage is closed under low-power mode, need to guarantee linearity and the efficiency under low-power mode by impedance inverting network and other matching network, this kind of mode can cause whole network quite complicated, and greatly improved production cost, the third is in module, to add switch to realize, this method has two kinds of implementations, a kind of is by technique, on a kind of wafer, to realize the function of power stage and switch, but the price of this technique is high, and another is directly to add a switch nude film to realize in module, what in patent 200910039721, adopt is exactly this method, and implementation is shown in Fig. 6, yet extra switch has also brought the rising of cost.CMOS technique, because substrate is not insulator, if directly make switch by conventional method, realizes ON/OFF characteristic by the characteristic of pipe self, and Insertion Loss can be larger so, thereby causes the gain of PA and the efficiency can be lower.
Summary of the invention
The problem to be solved in the present invention is in power amplifier module inside, added CMOS pipe as switch and by matching network, realized the work under the height frequency mode of whole power amplifier.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it comprises high power module, middle low power module and output matching network circuit two;
High power module comprises matching network circuit one, drive circuit, inter-stage matching network circuit, power output circuit and the output matching network circuit one being connected in series successively, also comprise CMOS pipe one and control circuit one, the output of the drain electrode of described CMOS pipe one and matching network circuit one is connected with the input junction of drive circuit, the grid of this CMOS pipe one is connected with the voltage output end of described control circuit one, and the source ground of CMOS pipe one;
Middle low power module comprises matching network circuit two, power amplifier two and the second level matching network circuit being connected in series successively, also comprise CMOS pipe two, in the output junction of this power amplifier two and matching network circuit two, be connected to the drain electrode of CMOS pipe two, the grid of described CMOS pipe two is connected with the voltage output end of control circuit two, the source ground of CMOS pipe two;
The input of matching network circuit one of described high power module and the input of the matching network circuit of middle low power module two are connected in parallel, and connect with the input of power amplifier;
The output of the output of described output matching network circuit one and second level matching network circuit is in parallel and connect with the input of output matching network circuit two.
Further, matching network circuit one and matching network circuit two form by an inductance and an electric capacity, and one end of described inductance is connected with one end of electric capacity, and the other end of this inductance connects with corresponding CMOS pipe, described electric capacity other end ground connection.
Further, also comprise three biasing circuits, the bias voltage output of these three biasing circuits is connected with drive circuit, power output circuit and power amplifier two respectively.
Further, described three biasing circuits are all integrated on CMOS nude film.
Further, described CMOS pipe one and CMOS pipe two are all integrated on CMOS nude film.
Further, described control circuit one and control circuit two are all embedded in CMOS nude film.
Advantage and good effect that the present invention has are:
1, CMOS pipe is realized by matching network as switch, rather than traditional employing CMOS pipe self-characteristic realizes on off state, can avoid the problem that Insertion Loss is large like this.
2, two CMOS pipes that use are integrated in the CMOS nude film of stablizing bias voltage for providing as switch, implementation method is simple, greatly reduces production cost.
3, due to the existence of CMOS pipe switch, eliminated the problem such as interfere with each other between high power portion and partial low-power, therefore simplified matching network, and the efficiency of power amplifier in the time of low-power operation is improved.
4, Integral lifting the service behaviour of power amplifier, and the taking up room of saving power amplifier.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is matching network and CMOS pipe connection diagram;
Fig. 3 is the basic framework schematic diagram of Linear Power Amplifier;
Fig. 4 is the Organization Chart of the modules of transmitting chain in handheld device;
Fig. 5 is the circuit diagram of realizing of low-power mode in patent US 7394313;
Fig. 6 is the circuit diagram of realizing high-low power pattern of mentioning in patent 200910039721.
Embodiment
Below in conjunction with accompanying drawing and concrete execution mode, the present invention is further illustrated.
As illustrated in fig. 1 and 2, a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it comprises high power module, middle low power module, biasing circuit and output matching network circuit two;
High power module comprises the matching network circuit one being connected in series successively, drive circuit, inter-stage matching network circuit, power output circuit and output matching network circuit one, also comprise CMOS pipe one and control circuit one, matching network circuit one is comprised of inductance and electric capacity, one end of inductance is connected with one end of electric capacity, and the other end of described inductance and the input of drive circuit are connected, the other end of described electric capacity is ground connection, the drain electrode of CMOS pipe one is connected with the input junction of drive circuit with the inductance in matching network circuit one, the grid of this CMOS pipe one is connected with the voltage output end of described control circuit one, and the source ground of CMOS pipe one,
Middle low power module comprises matching network circuit two, power amplifier two and the second level matching network circuit being connected in series successively, also comprise CMOS pipe two, described matching network circuit two is comprised of inductance and electric capacity, this connected mode is identical with matching network circuit one, and in the inductance junction of this power amplifier two and matching network circuit two, be connected to the drain electrode of CMOS pipe two, the grid of described CMOS pipe two is connected with the voltage output end of control circuit two, the source ground of CMOS pipe two;
The input of matching network circuit one of described high power module and the input of the matching network circuit of middle low power module two are connected in parallel, and connect with the input of power amplifier;
The output of the output of described output matching network circuit one and second level matching network circuit is in parallel and connect with the input of output matching network circuit two;
The bias voltage output of described three biasing circuits is connected with drive circuit, power output circuit and power amplifier two respectively, and biasing circuit is all integrated on CMOS nude film, shown in be also embedded with CMOS pipe one and CMOS pipe two and control circuit one and control circuit two on CMOS nude film.
Above-mentioned drive circuit provides certain gain and power amplification for power output circuit; And the main power output of power output circuit; Output matching network circuit converts best power output point to 50ohm; Simultaneously, the current way of bias voltage of power amplifier is through Vref pin, to provide voltage by the GPIO mouth of baseband chip, with this, guarantee the normal work of drive circuit, power output circuit and power amplifier two, therefore need to provide stable bias voltage at the inner nude film that increases a CMOS technique of power amplifier module; Arranging of matching network one and matching network two is all to play the effect that can adjust in time input impedance.
Enforcement principle of the present invention:
By adjusting the voltage of control circuit, make CMOS pipe can be height when controlling voltage on off state, and CMOS pipe work, in variable resistor district, is equivalent to switch opens, and this pipe is equivalent to the small resistor of about several ohm; And when to control voltage be low, CMOS pipe by, be equivalent to switch close, this pipe is equivalent to the little electric capacity of a 0.1pF～1pF.Described resistance or the size of capacitance all depend on the Insertion Loss of switch or the size of isolation.When optimizing the matching network of CMOS pipe leading portion, can realize at CMOS pipe during in closed condition the mould value of input impedance | Zin| is smaller, simultaneously at CMOS pipe under open mode, the mould value of input impedance | Zin| is larger.
Under high-power mode, according to the state of CMOS pipe one, can meet | Z
in2| >>|Z
in1|, now from the energy of the input of power amplifier, can enter into drive circuit, then through inter-stage matching network circuit to power output circuit, thereby realize high-power output; And under middle low-power mode, according to the state of CMOS pipe 2, can meet | Z
in1| <<|Z
in2|, now the energy at the input of power amplifier can enter into power amplifier two, the output of power mode in realization; Under middle power mode, reduce the bias voltage of power amplifier two, can realize the output of low-power mode.
Implementation process of the present invention:
When power amplifier is under high-power mode, by controlling each self-corresponding biasing circuit, make drive circuit and the power output circuit state in opening, and power amplifier two is closed condition, and the voltage of adjusting control circuit two, makes CMOS pipe two be operated in variable resistor district, CMOS pipe one is operated in by district it by adjusting control circuit one, now the energy of the input of power amplifier will pass through high power module, and from two outputs of output matching network circuit.
When power amplifier is under middle low-power mode, by adjustment, control each self-corresponding biasing circuit, make driving stage and the power output stage state in closing, and the state of PA2 in opening, the CMOS pipe one that simultaneously connects driving stage makes it be operated in variable resistor district by adjusting control circuit one, and the CMOS pipe two-way that connects power amplifier two is crossed adjustment control circuit two it is operated in by district, the energy of the input of power amplifier low module in will passing through now, and from two outputs of output matching network circuit.
Above embodiments of the invention are had been described in detail, but described content is only preferred embodiment of the present invention, can not be considered to for limiting practical range of the present invention.All equalization variations of doing according to the scope of the invention and improvement etc., within all should still belonging to this patent covering scope.
Claims (6)
1. with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it is characterized in that: it comprises high power module, middle low power module and output matching network circuit two;
High power module comprises matching network circuit one, drive circuit, inter-stage matching network circuit, power output circuit and the output matching network circuit one being connected in series successively, also comprise CMOS pipe one and control circuit one, the output of the drain electrode of described CMOS pipe one and matching network circuit one is connected with the input junction of drive circuit, the grid of this CMOS pipe one is connected with the voltage output end of described control circuit one, and the source ground of CMOS pipe one;
Middle low power module comprises matching network circuit two, power amplifier two and the second level matching network circuit being connected in series successively, also comprise CMOS pipe two, in the output junction of this power amplifier two and matching network circuit two, be connected to the drain electrode of CMOS pipe two, the grid of described CMOS pipe two is connected with the voltage output end of control circuit two, the source ground of CMOS pipe two;
The input of matching network circuit one of described high power module and the input of the matching network circuit of middle low power module two are connected in parallel, and connect with the input of power amplifier;
The output of the output of described output matching network circuit one and second level matching network circuit is in parallel and connect with the input of output matching network circuit two.
2. according to claim 1ly a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it is characterized in that: matching network circuit one and matching network circuit two form by an inductance and an electric capacity, one end of described inductance is connected with one end of electric capacity, the other end of this inductance connects with corresponding CMOS pipe, described electric capacity other end ground connection.
3. according to claim 1ly a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it is characterized in that: also comprise three biasing circuits, the bias voltage output of described three biasing circuits is connected with drive circuit, power output circuit and power amplifier two respectively.
4. according to claim 3ly a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it is characterized in that: described three biasing circuits all embed in CMOS nude film.
5. according to claim 4ly a kind ofly with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it is characterized in that: described CMOS pipe one and CMOS pipe two are all integrated on CMOS nude film.
6. according to a kind of described in claim 3,4 or 5, with CMOS pipe, do the circuit that switch is realized the high-low power of linear power amplifier, it is characterized in that: described control circuit one and control circuit two are all embedded in CMOS nude film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310756100.2A CN103701412B (en) | 2013-12-31 | 2013-12-31 | Circuit for realizing high and low power of linear power amplifier by taking CMOS (complementary metal-oxide-semiconductor) transistors as switches |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310756100.2A CN103701412B (en) | 2013-12-31 | 2013-12-31 | Circuit for realizing high and low power of linear power amplifier by taking CMOS (complementary metal-oxide-semiconductor) transistors as switches |
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| CN103701412A true CN103701412A (en) | 2014-04-02 |
| CN103701412B CN103701412B (en) | 2017-01-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110768648A (en) * | 2018-07-26 | 2020-02-07 | 苏州能讯微波集成电路有限公司 | TDD (time division Duplex) switching circuit and depletion type semiconductor amplifying circuit |
| CN113258914A (en) * | 2021-06-17 | 2021-08-13 | 展讯通信（上海）有限公司 | Signal processing circuit and wireless communication device |
| CN113541675A (en) * | 2020-04-17 | 2021-10-22 | 爱思开海力士有限公司 | Semiconductor device for controlling voltage at input node of circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080111630A1 (en) * | 2006-10-05 | 2008-05-15 | Nec Electronics Corporation | Small size power amplifier with amplifiers switched |
| CN101562425A (en) * | 2009-05-26 | 2009-10-21 | 惠州市正源微电子有限公司 | High-low power combining circuit for radio-frequency power amplifier |
| CN101656509A (en) * | 2009-09-04 | 2010-02-24 | 惠州市正源微电子有限公司 | High and low power combination circuit of radio frequency power amplifier |
| CN101656515A (en) * | 2009-09-04 | 2010-02-24 | 惠州市正源微电子有限公司 | High and low power combination circuit of radio frequency power amplifier |
| CN201438689U (en) * | 2009-04-30 | 2010-04-14 | 惠州市正源微电子有限公司 | High and low power combining circuit for RF power amplifier |
| CN203775144U (en) * | 2013-12-31 | 2014-08-13 | 天津朗波微电子有限公司 | Circuit of realizing high/low power of linear power amplifier by using CMOS (Complementary Metal Oxide Semiconductor) tubes as switches |
-
2013
- 2013-12-31 CN CN201310756100.2A patent/CN103701412B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080111630A1 (en) * | 2006-10-05 | 2008-05-15 | Nec Electronics Corporation | Small size power amplifier with amplifiers switched |
| CN201438689U (en) * | 2009-04-30 | 2010-04-14 | 惠州市正源微电子有限公司 | High and low power combining circuit for RF power amplifier |
| CN101562425A (en) * | 2009-05-26 | 2009-10-21 | 惠州市正源微电子有限公司 | High-low power combining circuit for radio-frequency power amplifier |
| CN101656509A (en) * | 2009-09-04 | 2010-02-24 | 惠州市正源微电子有限公司 | High and low power combination circuit of radio frequency power amplifier |
| CN101656515A (en) * | 2009-09-04 | 2010-02-24 | 惠州市正源微电子有限公司 | High and low power combination circuit of radio frequency power amplifier |
| CN203775144U (en) * | 2013-12-31 | 2014-08-13 | 天津朗波微电子有限公司 | Circuit of realizing high/low power of linear power amplifier by using CMOS (Complementary Metal Oxide Semiconductor) tubes as switches |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110768648A (en) * | 2018-07-26 | 2020-02-07 | 苏州能讯微波集成电路有限公司 | TDD (time division Duplex) switching circuit and depletion type semiconductor amplifying circuit |
| CN110768648B (en) * | 2018-07-26 | 2024-05-14 | 苏州能讯微波集成电路有限公司 | TDD switching circuit and depletion type semiconductor amplifying circuit |
| CN113541675A (en) * | 2020-04-17 | 2021-10-22 | 爱思开海力士有限公司 | Semiconductor device for controlling voltage at input node of circuit |
| CN113541675B (en) * | 2020-04-17 | 2024-02-13 | 爱思开海力士有限公司 | Semiconductor device for controlling voltage at input node of circuit |
| CN113258914A (en) * | 2021-06-17 | 2021-08-13 | 展讯通信（上海）有限公司 | Signal processing circuit and wireless communication device |
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