CN103700647B - Package substrate and the integrated circuit comprising the package substrate - Google Patents
Package substrate and the integrated circuit comprising the package substrate Download PDFInfo
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- CN103700647B CN103700647B CN201310751619.1A CN201310751619A CN103700647B CN 103700647 B CN103700647 B CN 103700647B CN 201310751619 A CN201310751619 A CN 201310751619A CN 103700647 B CN103700647 B CN 103700647B
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- package substrate
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- line layer
- conduction column
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Abstract
The present invention is the integrated circuit on package substrate and comprising the package substrate.One embodiment of the invention provides a package substrate, and the package substrate includes：First line layer, the second line layer, the dielectric layer between the first line layer and the second line layer, it is embedded into conduction column in the dielectric layer, and is arranged at the virtual conduction column of the conduction column side.The upper end of the conduction column connects second line layer, and lower end connects the first line layer to conduct the first line layer and the second line layer.The virtual conduction column does not conduct the first line layer and the second line layer.The package substrate of the present invention and the integrated circuit comprising the package substrate can realize the miniaturization of integrated circuit with alap package substrate angularity.
Description
Technical field
The present invention relates to integrated circuit fields, package substrate especially with regard to integrated circuit fields and the encapsulation base is included
The integrated circuit of plate.
Background technology
With the development of electronic technology, requirement more and more higher of the consumer to electronic product.It is desirable to the production of same electronics
Integrated function is increasingly come more on product, but volume is increasingly frivolous.And to meet this high degree of integration and miniaturization will
Ask, the improvement of IC products relying primarily on or as core component.
One of improved approach is exactly to use layer multilayer packaging substrate, and interlayer interconnection technique is used under limited space to expand
The configuration area utilized is available on big package substrate, coordinates the use demand of the integrated circuit of elevated track density, reduces envelope
The thickness of substrate is filled, so as to reach the purpose that encapsulating products are multi-functional, minimize.
Layer multilayer packaging substrate mainly has two kinds at present, and a kind of is the package substrate for having support plate, or has the encapsulation of core layer
Substrate, it is by a core board with internal layer circuit and is formed at the circuit layer reinforced structures of the core board both sides and forms, core board
The smooth of whole package substrate can be ensured；Package substrate that is another then being no support plate, or the package substrate of seedless central layer, its
Support plate is removed after increasing layer so as to further shorten conductor length and reduce integral thickness.Because no support plate supports, coreless
The package substrate of layer is easy to that warpage occurs, therefore the factor of the planarization of any package substrate that may influence seedless central layer is all
Consider carefully.
The content of the invention
An object of the present invention is to provide package substrate and the integrated circuit comprising the package substrate, with as low as possible
Package substrate angularity realize the miniaturization of integrated circuit.
One embodiment of the invention provides a package substrate, and the package substrate includes：First line layer, the second line layer,
Dielectric layer between the first line layer and the second line layer, it is embedded into conduction column in the dielectric layer, and is arranged at this and leads
The virtual conduction column of through post side.The upper end of the conduction column connects second line layer, and lower end connects the first line layer with electricity
Turn on the first line layer and the second line layer.The virtual conduction column does not conduct the first line layer and the second line layer.
According to one embodiment of the invention, the package substrate is coreless laminar substrate.In the dielectric layer, with the conduction column
It is interior without other conduction columns or heat sink strip area for the center of circle, circumference of the radius more than or equal to 700um.The virtual conduction column and the conduction column
The distance between be not more than 700um.The virtual conduction column can electrically connect with the ground path of the package substrate, and can be long
The variously-shaped metal coupling such as bar shaped or polygon.
Another embodiment of the present invention additionally provides the integrated circuit comprising the package substrate.
Compared to prior art, package substrate of the invention and the integrated circuit comprising the package substrate pass through in conduction column
Sparse region sets virtual conduction column to provide support, reduces out-of-flatness caused by package substrate brushing, and then improve package substrate
With the quality of integrated circuit.
Brief description of the drawings
Fig. 1 is the cross-sectional view of an existing package substrate in the fabrication process
Fig. 2 is the cross-sectional view of package substrate according to an embodiment of the invention
Fig. 3 is that cross-section structure of the package substrate according to an embodiment of the invention after the embedment of first time conduction column is completed shows
It is intended to
Embodiment
Spirit for a better understanding of the present invention, it is made furtherly below in conjunction with the part preferred embodiment of the present invention
It is bright.
Integrated circuit is mainly to be made up of chip with the package substrate for carrying the chip.And package substrate particularly coreless
Layer package substrate can be two-sided while carry out increasing layer operation and makes line construction in manufacturing process, and every time will after increasing layer
Brushing is carried out to expose metal structure therein.
Fig. 1 is the cross-sectional view of an existing package substrate 10 in the fabrication process.For the sake of simplicity, only given in Fig. 1
The package substrate monomer of a corresponding encapsulation unit is gone out, every package substrate 10 includes some as is known to the person skilled in the art
Package substrate monomer.
As shown in figure 1, two kinds of metal structures are primarily present in current package substrate 10：A kind of is the metal for radiating
Projection, heat sink strip can be claimed（bar）12；Another kind is used to support and the metal coupling of circuit turn-on, can claim conduction column (pillar)
14.Bar12 is typically that multiple concentrate forms a heat sink strip area 120, is mainly used in the packaging body as power amplifier, can
It is arranged on chip（It is not shown）Lower section and be connected with chip to play a part of as chip cooling.Relative in package substrate 10
Effective electrical circuit（Not comprising simple ground path）, bar12 is electrically independent.Pillar14 is then scattered, and can lead
Logical levels circuit（It is not shown）, it is typically cylinder.
Because the design of package substrate 10 need to consider many factors, heat sink strip area 120 and Pillar14 be difficult accomplish uniformly,
High-density array.But then, the strength difference between the base material 16 of package substrate 10 and metal structure is larger, such as base material 16
It is prepreg (prepreg-pp), is a kind of preimpregnation material being made up of resin and reinforcing material, and metal structure is then copper
Block.When package substrate 12 carries out two-sided while brushing, after brushing identical number, the small material of intensity is by the big material of intensity
The reaction force of material and relative pressure of brushing is bigger than normal, it is easier to fallen by brushing.Therefore package substrate 10 in the fabrication process, is often present
The out-of-flatness phenomenon caused by brushing, thus influence the quality of follow-up layer reinforced structure.
Package substrate according to embodiments of the present invention then solves this well with the integrated circuit comprising the package substrate
One problem, it sets virtual conduction column to improve the distribution density of metal structure and being distributed relatively sparse conduction column side
Even property, greatly reduce because base material is different from the intensity of metal structure and metal structure skewness caused by brushing out-of-flatness
Property.
Fig. 2 is the cross-sectional view of package substrate 20 according to an embodiment of the invention.
As shown in Fig. 2 the package substrate 20 includes some line layers and is respectively arranged on the dielectric layer of two circuit interlayers.Specifically
, the package substrate 20 includes first line layer 200, the second line layer 202, tertiary circuit layer 204, the 4th line layer 206, the
Five line layers 208, the first dielectric layer 210 being arranged between the line layer 202 of first line layer 200 and second, it is arranged on the second line
The second dielectric layer 212 between road floor 202 and tertiary circuit floor 204, it is arranged between the line layer 206 of tertiary circuit floor 204 and the 4th
The 3rd dielectric layer 214, and the 4th dielectric layer 216 being arranged between the 4th line layer 206 and the 5th line layer 208.Each dielectric
Some conduction columns 220 are provided with layer, are respectively turned on two adjacent line layers.For example, the conduction column 220 in the first dielectric layer 210
Upper end connects the second line layer 202, and lower end connects first line layer 200 so as to conduct the first line layer 200 and second
Line layer 202；The upper end of conduction column 220 connection tertiary circuit layer 202 in second dielectric layer 212, lower end connects the second circuit
Layer 202 is so as to conduct second line layer 200 and tertiary circuit layer 204, by that analogy.
Sparse region is distributed for conduction column 220, is not had between such as conduction column 220 of centre two of the second dielectric layer 212
Any conduction column 220, package substrate 20 of the invention provide the arrangement of virtual conduction column 222.Specifically, in the second dielectric
Two similar conduction columns 220 are added between the conduction column 220 of centre two of layer 212 but do not conduct the metal knot of line layer
Structure, i.e., virtual conduction column 222.These virtual conduction columns 222 can be distributed rarefaction in metal structure and provide certain support, so as to
The tolerance during the brushing in the region is improved, and then improves the overall leveling of package substrate 20.
Similar, there is also conduction column in the 3rd dielectric layer 214 to be distributed rarefaction, as between middle two conduction columns 220
Region, therefore the 3rd dielectric layer 214 the region also comprising virtual conduction column 222 with improve the distribution density of metal structure and
Uniformity.
The specific setting of virtual conduction column 222 can be adjusted flexibly according to the IC design demand of reality.For example, same
It is the center of circle with a conduction column 220 in one dielectric layer, if surrounding reaches certain scope without other conduction columns or heat sink strip area just
An at least conduction column 220 can be set in circumference of the side of conduction column 220 less than 700um, it is preferable that with a conduction column 220
For the center of circle, radius then will be by the conduction column 220 without other conduction columns or heat sink strip area in the range of being more than or equal to 700um
Side sets an at least conduction column 220 in the circumference less than 700um.Bilevel virtual conduction column 222, which can connect, also not to be connected
Connect, or even the ground path of package substrate can be connected according to demand, but can not conduct in addition to ground wire other are effective
Circuit.For the first dielectric layer 210 and the 4th dielectric layer of the not high dielectric layer of flatness requirement, such as above-mentioned package substrate 20
216, it is contemplated that follow-up no longer increasing layer, the influence of two layers of the irregularities to encapsulation is little, even if it is dilute conduction column to be thereon present
Area is dredged, virtual conduction column 222 can not also be set thereon.
The shape of virtual conduction column 222（Cross sectional shape i.e. in the horizontal direction）It is generally circular, in addition can also basis
Design need be arranged to strip, or polygon.
Fig. 3 is section of the package substrate 20 according to an embodiment of the invention after completing first time conduction column 220 and being embedded to
Structural representation.As shown in figure 3, virtual conduction column 222 can be formed simultaneously with conduction column 220 with identical material, same process, because
Technological process without complicating package substrate 20.Certainly, in other embodiments, virtual conduction column 222 also completely can be with
Using other high hardness materials, handled and completed with single technological process.
Another embodiment of the present invention discloses the integrated circuit being encapsulated into by above-mentioned package substrate, i.e. a chip is set
In above-mentioned package substrate, chip and the package substrate are electrically connected with by several plain conductors, and chip package is formed one by adhesive body
Integrated circuit structure, the structure of the package substrate of the integrated circuit are being described above, not repeated herein.
The technology contents and technical characterstic of the present invention have revealed that as above, but those skilled in the art still may base
Make a variety of replacements and modification without departing substantially from spirit of the present invention in teachings of the present invention and announcement.Therefore, protection model of the invention
Content disclosed in embodiment should be not limited to by enclosing, and should include various replacements and modification without departing substantially from the present invention, and be this patent
Application claims are covered.
Claims (8)
1. a kind of integrated circuit, comprising：
Chip；And
Package substrate, the wherein package substrate are coreless laminar substrates, and the package substrate includes：
Multiple line layers, the multiple line layer include：First line layer, the second line layer, tertiary circuit layer, the 4th circuit
Layer, and the 5th line layer；
Multiple dielectric layers, the multiple dielectric layer include：First between the first line layer and second line layer is situated between
Electric layer, the second dielectric layer between second line layer and the tertiary circuit layer, positioned at the tertiary circuit layer and the 4th
The 3rd dielectric layer between line layer, and the 4th dielectric layer between the 4th line layer and the 5th line layer；
Some conduction columns, it is embedded into and is respectively turned on two adjacent line layers in the multiple dielectric layer, some conduction columns；And
Some virtual conduction columns, each virtual conduction column is embedded into the single dielectric layer in the multiple dielectric layer, and sets
In some conduction column distribution sparse region, without conducting two line layers adjacent in the multiple line layer, wherein should
Virtual conduction column is the metal coupling of circular, strip or polygon.
2. integrated circuit as claimed in claim 1, wherein in the dielectric layer, using the conduction column as the center of circle, radius is more than etc.
In in 700um circumference without other conduction columns or heat sink strip area.
3. the distance between integrated circuit as claimed in claim 1, the wherein virtual conduction column and the conduction column are not more than
700um。
4. integrated circuit as claimed in claim 1, the wherein virtual conduction column can be electrically connected with the ground path of the integrated circuit
Connect.
5. a kind of package substrate, it is coreless laminar substrate, and it is included：
Multiple line layers, the multiple line layer include：First line layer, the second line layer, tertiary circuit layer, the 4th circuit
Layer, and the 5th line layer；
Multiple dielectric layers, the multiple dielectric layer include：First between the first line layer and second line layer is situated between
Electric layer, the second dielectric layer between second line layer and the tertiary circuit layer, positioned at the tertiary circuit layer and the 4th
The 3rd dielectric layer between line layer, and the 4th dielectric layer between the 4th line layer and the 5th line layer；
Some conduction columns, it is embedded into and is respectively turned on two adjacent line layers in the multiple dielectric layer, some conduction columns；And
Some virtual conduction columns, each virtual conduction column is embedded into the single dielectric layer in the multiple dielectric layer, and sets
In some conduction column distribution sparse region, without conducting two line layers adjacent in the multiple line layer, wherein should
Virtual conduction column is the metal coupling of circular, strip or polygon.
6. package substrate as claimed in claim 5, wherein in the dielectric layer, using the conduction column as the center of circle, radius is more than etc.
In in 700um circumference without other conduction columns or heat sink strip area.
7. the distance between package substrate as claimed in claim 5, the wherein virtual conduction column and the conduction column are not more than
700um。
8. package substrate as claimed in claim 5, the wherein virtual conduction column can be electrically connected with the ground path of the package substrate
Connect.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310751619.1A CN103700647B (en) | 2013-12-31 | 2013-12-31 | Package substrate and the integrated circuit comprising the package substrate |
| TW103146637A TWI546909B (en) | 2013-12-31 | 2014-12-31 | A package substrate, and a semiconductor integrated circuit including the package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310751619.1A CN103700647B (en) | 2013-12-31 | 2013-12-31 | Package substrate and the integrated circuit comprising the package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103700647A CN103700647A (en) | 2014-04-02 |
| CN103700647B true CN103700647B (en) | 2018-03-16 |
Family
ID=50362129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310751619.1A Active CN103700647B (en) | 2013-12-31 | 2013-12-31 | Package substrate and the integrated circuit comprising the package substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103700647B (en) |
| TW (1) | TWI546909B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203800035U (en) * | 2013-12-31 | 2014-08-27 | 日月光半导体(上海)有限公司 | Packaging substrate and integrated circuit having same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4222979B2 (en) * | 2004-07-28 | 2009-02-12 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
| JP2007234663A (en) * | 2006-02-27 | 2007-09-13 | Kyocera Corp | Wiring board, and electronic device employing it |
| KR100791697B1 (en) * | 2006-08-29 | 2008-01-03 | 동부일렉트로닉스 주식회사 | Metal line structure and method for forming metal line of semiconductor device |
| JP4642908B2 (en) * | 2008-03-11 | 2011-03-02 | パナソニック株式会社 | Semiconductor integrated circuit device |
| JP2013222929A (en) * | 2012-04-19 | 2013-10-28 | Renesas Electronics Corp | Multilayer wiring board |
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2013
- 2013-12-31 CN CN201310751619.1A patent/CN103700647B/en active Active
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- 2014-12-31 TW TW103146637A patent/TWI546909B/en active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203800035U (en) * | 2013-12-31 | 2014-08-27 | 日月光半导体(上海)有限公司 | Packaging substrate and integrated circuit having same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103700647A (en) | 2014-04-02 |
| TW201526173A (en) | 2015-07-01 |
| TWI546909B (en) | 2016-08-21 |
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