CN103700647A - Package substrate and integrated circuit comprising same - Google Patents
Package substrate and integrated circuit comprising same Download PDFInfo
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- CN103700647A CN103700647A CN201310751619.1A CN201310751619A CN103700647A CN 103700647 A CN103700647 A CN 103700647A CN 201310751619 A CN201310751619 A CN 201310751619A CN 103700647 A CN103700647 A CN 103700647A
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- conduction column
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Abstract
The invention relates to a package substrate and an integrated circuit comprising the same. One embodiment of the invention provides the package substrate which comprises a first circuit layer, a second circuit layer, a dielectric layer located between the first circuit layer and the second circuit layer, a breakover column which is embedded in the dielectric layer and a virtual breakover column arranged at the side of the breakover column, wherein the upper end of the breakover column is connected with the second circuit layer; the lower end of the breakover column is connected with the first circuit layer to electrically connect the first circuit layer and the second circuit layer; the virtual breakover column does not electrically connect the first circuit layer and the second circuit layer. The package substrate and the integrated circuit comprising the same can realize the miniaturization of the integrated circuit by keeping the package substrate warping degree as low as possible.
Description
Technical field
The present invention relates to integrated circuit fields, particularly about the base plate for packaging of integrated circuit fields and the integrated circuit that comprises this base plate for packaging.
Background technology
Along with the development of electronic technology, consumer is more and more higher to the requirement of electronic product.People wish that function integrated on same electronic product more and more comes manyly, but volume is day by day frivolous.And to meet this high degree of integration and microminiaturized requirement, main that rely on or as the improvement of the integrated circuit (IC) products of core component.
One of improved approach is exactly to use layer multilayer packaging substrate, under limited space, use interlayer interconnection technique can supply the configuration area of utilization to expand on base plate for packaging, coordinate the user demand of the integrated circuit of elevated track density, the thickness that reduces base plate for packaging, thereby reach, encapsulating products is multi-functional, the object of miniaturization.
Layer multilayer packaging substrate mainly contains two kinds at present, a kind of is the base plate for packaging that has support plate, or claim to have the base plate for packaging of core layer, and its circuit layer reinforced structure that has the core board of internal layer circuit by one and be formed at these core board both sides forms, and core board can guarantee the smooth of whole base plate for packaging; Another kind of be the base plate for packaging without support plate, or claim the base plate for packaging of coreless layer, thus it removes support plate and further shortens conductor length and reduce integral thickness after increasing layer.Owing to not having support plate to support, the base plate for packaging of coreless layer is easy to occur warpage, and therefore the factor of the planarization of any base plate for packaging that may affect coreless layer all will be considered carefully.
Summary of the invention
One of object of the present invention is the integrated circuit that base plate for packaging is provided and comprises this base plate for packaging, realizes the miniaturization of integrated circuit with alap base plate for packaging angularity.
One embodiment of the invention provide a base plate for packaging, this base plate for packaging comprises: the first line layer, the second line layer, the dielectric layer between this first line layer and the second line layer, be embedded into the conduction column in this dielectric layer, and be arranged at the virtual conduction column of this conduction column side.The upper end of this conduction column connects this second line layer, and lower end connects this first line layer to conduct this first line layer and the second line layer.This virtual conduction column does not conduct this first line layer and the second line layer.
According to one embodiment of the invention, this base plate for packaging is coreless laminar substrate.In this dielectric layer, take this conduction column as the center of circle, radius is more than or equal in the circumference of 700um without other conduction column or heat sink strip district.Distance between this virtual conduction column and this conduction column is not more than 700um.This virtual conduction column can with this base plate for packaging ground path be electrically connected to, and can be the metal coupling of the various shapes such as strip or polygon.
Another embodiment of the present invention also provides the integrated circuit that comprises this base plate for packaging.
Compared to prior art, base plate for packaging of the present invention and the integrated circuit that comprises this base plate for packaging provide support by virtual conduction column being set in conduction column sparse region, reduce the out-of-flatness that base plate for packaging brushing causes, and then improve the quality of base plate for packaging and integrated circuit.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of an existing base plate for packaging in manufacture process
Fig. 2 is the cross-sectional view of base plate for packaging according to an embodiment of the invention
Fig. 3 is the cross-sectional view of base plate for packaging after completing conduction column for the first time and imbedding according to an embodiment of the invention
Embodiment
Spirit for a better understanding of the present invention, is described further it below in conjunction with part preferred embodiment of the present invention.
Integrated circuit is mainly comprised of the base plate for packaging of chip and this chip of carrying.And base plate for packaging particularly coreless layer package substrate in manufacturing process, can two-sidedly increase layer operation simultaneously and make line construction, and all to carry out brushing to expose metal structure wherein after increasing layer at every turn.
Fig. 1 is the cross-sectional view of an existing base plate for packaging 10 in manufacture process.For the purpose of simple, only provided the base plate for packaging monomer of a corresponding encapsulation unit in Fig. 1, every base plate for packaging 10 comprises some base plate for packaging monomers as is known to the person skilled in the art.
As shown in Figure 1, mainly in current base plate for packaging 10 there are two kinds of metal structures: a kind of is metal coupling for dispelling the heat, can claim heat sink strip (bar) 12; Another kind of for supporting and the metal coupling of circuit turn-on, can claim conduction column (pillar) 14.Normally a plurality of concentrated composition of Bar12 one heat sink strip district 120, is mainly being used as in the packaging body of power amplifier, and can be arranged on the below of chip (not shown) and be connected with chip to play is the effect of chip cooling.With respect to the effectively electrically circuit (not comprising simple ground path) of 10 li of base plate for packaging, bar12 is electrically independently.Pillar14 is scattered, can conducting levels circuit (not shown), and normally cylindrical.
Because the design of base plate for packaging 10 need be considered many factors, heat sink strip district 120 and Pillar14 are difficult to accomplish evenly, high density is arranged.But then, base material 16 and the strength difference between metal structure of base plate for packaging 10 are larger, if base material 16 is prepreg (prepreg-pp), are a kind of preimpregnation materials consisting of resin and reinforcing material, and metal structure is copper billet.At base plate for packaging 12, carry out two-sided while during brushing, after the identical number of times of brushing, the material that intensity is little be subject to the material that intensity is large reaction force and relatively brush press bigger than normally, more easily by brushing, fallen.Therefore in manufacture process, often there is the out-of-flatness phenomenon causing because of brushing, thereby affect the quality of follow-up layer reinforced structure in base plate for packaging 10.
According to the base plate for packaging of the embodiment of the present invention and the integrated circuit that comprises this base plate for packaging, well solved this problem, it arranges virtual conduction column to improve distribution density and the uniformity of metal structure at the relatively sparse conduction column side that distributes, and has greatly reduced because of intensity different and metal structure skewness cause the brushing out-of-flatness of base material from metal structure.
Fig. 2 is the cross-sectional view of base plate for packaging 20 according to an embodiment of the invention.
As shown in Figure 2, this base plate for packaging 20 comprises some line layers and is located at respectively the dielectric layer between two line layers.Concrete, this base plate for packaging 20 comprises the first line layer 200, the second line layer 202, tertiary circuit layer 204, the 4th line layer 206, the 5th line layer 208, be arranged on 202 of the first line layer 200 and the second line layers the first dielectric layer 210, be arranged on 204, the second line layer 202 and tertiary circuit layer the second dielectric layer 212, be arranged on the 3rd dielectric layer 214 of 206 of tertiary circuit layer 204 and the 4th line layers, and be arranged on the 4th dielectric layer 216 of 208 of the 4th line layer 206 and the 5th line layers.In each dielectric layer, be provided with some conduction columns 220, respectively two adjacent line layers of conducting.For example, conduction column 220 upper ends in the first dielectric layer 210 connect the second line layer 202, thereby lower end connects the first line layer 200, can conduct this first line layer 200 and the second line layer 202; Conduction column 220 upper ends in this second dielectric layer 212 connect tertiary circuit layer 202, can conduct this second line layer 200 and tertiary circuit layer 204, by that analogy thereby lower end connects the second line layer 202.
For conduction column 220 distribution sparse region, as between two of the centres conduction column 220 of the second dielectric layer 212 without any conduction column 220, base plate for packaging 20 of the present invention provides the layout of virtual conduction column 222.Concrete, between the conduction column 220 of two of the centres of the second dielectric layer 212, increased by two similar conduction columns 220 but do not conducted the metal structure of line layer, be i.e. virtual conduction column 222.These virtual conduction columns 222 can provide certain support in the metal structure rarefaction that distributes, thereby improve the tolerance in the brushing process in this region, and then improve the overall leveling of base plate for packaging 20.
Similarly, in the 3rd dielectric layer 214, also there is conduction column distribution rarefaction, as the region between middle two conduction columns 220, therefore the 3rd dielectric layer 214 also comprises virtual conduction column 222 to improve distribution density and the uniformity of metal structure in this region.
The concrete setting of virtual conduction column 222 can be adjusted flexibly according to actual integrated circuit (IC) design demand.For example, in same dielectric layer, the conduction column 220 of take is the center of circle, as around reach certain scope and will in these conduction column 220 sides are less than the circumference of 700um, at least one conduction column 220 be set without other conduction column or heat sink strip district, preferably, the conduction column 220 of take is the center of circle, and radius is more than or equal in the scope of 700um without other conduction column or heat sink strip district will arrange at least one conduction column 220 in these conduction column 220 sides are less than the circumference of 700um.Bilevel virtual conduction column 222 can connect also and can not connect, the ground path of connection encapsulation substrate even according to demand, but can not conduct other the effective circuits except earth connection.For the less demanding dielectric layer of evenness, as the first dielectric layer 210 of above-mentioned base plate for packaging 20 and the 4th dielectric layer 216, consider the follow-up layer that no longer increases, this two-layer out-of-flatness is little on the impact of encapsulation, even if there is conduction column rarefaction on it, also virtual conduction column 222 can be set thereon.
It is circular that the shape of virtual conduction column 222 (cross sectional shape) is in the horizontal direction generally, in addition also can be according to design need to be arranged to strip, or polygon.
Fig. 3 is the cross-sectional view of base plate for packaging 20 after completing conduction column 220 for the first time and imbedding according to an embodiment of the invention.As shown in Figure 3, virtual conduction column 222 can form with same material, same process with conduction column 220 simultaneously, thereby technological process that can complicated base plate for packaging 20.Certainly, in other embodiments, virtual conduction column 222 also can be used other high hardness material completely, with independent technological process, finishes dealing with.
Another embodiment of the present invention discloses the integrated circuit being encapsulated into by above-mentioned base plate for packaging, a chip is arranged at above-mentioned base plate for packaging, several plain conductors are electrically connected chip and this base plate for packaging, adhesive body forms an integrated circuit structure by chip package, the structure of the base plate for packaging of this integrated circuit, describing above, does not repeat at this.
Technology contents of the present invention and technical characterstic disclose as above, yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by present patent application claims.
Claims (12)
1. an integrated circuit, comprises:
Chip; And
Base plate for packaging, this base plate for packaging comprises:
The first line layer;
The second line layer;
Dielectric layer between this first line layer and the second line layer;
Conduction column, is embedded in this dielectric layer; The upper end of this conduction column connects this second line layer, and lower end connects this first line layer to conduct this first line layer and the second line layer; And
Virtual conduction column, is arranged at this conduction column side and does not conduct this first line layer and the second line layer.
2. integrated circuit as claimed in claim 1, wherein, in this dielectric layer, take this conduction column as the center of circle, and radius is more than or equal in the circumference of 700um without other conduction column or heat sink strip district.
3. integrated circuit as claimed in claim 1, wherein the distance between this virtual conduction column and this conduction column is not more than 700um.
4. integrated circuit as claimed in claim 1, wherein this virtual conduction column can be electrically connected to the ground path of this integrated circuit.
5. integrated circuit as claimed in claim 1, the metal coupling that wherein this virtual conduction column is the various shapes such as strip or polygon.
6. integrated circuit as claimed in claim 1, wherein this base plate for packaging is coreless laminar substrate.
7. a base plate for packaging, comprises:
The first line layer;
The second line layer;
Dielectric layer between this first line layer and the second line layer;
Conduction column, is embedded in this dielectric layer; The upper end of this conduction column connects this second line layer, and lower end connects this first line layer to conduct this first line layer and the second line layer; And
Virtual conduction column, is arranged at this conduction column side and does not conduct this first line layer and the second line layer.
8. base plate for packaging as claimed in claim 7, wherein, in this dielectric layer, take this conduction column as the center of circle, and radius is more than or equal in the circumference of 700um without other conduction column or heat sink strip district.
9. base plate for packaging as claimed in claim 7, wherein the distance between this virtual conduction column and this conduction column is not more than 700um.
10. base plate for packaging as claimed in claim 7, wherein this virtual conduction column can be electrically connected to the ground path of this base plate for packaging.
11. base plate for packaging as claimed in claim 7, the metal coupling that wherein this virtual conduction column is the various shapes such as strip or polygon.
12. base plate for packaging as claimed in claim 7, it is coreless laminar substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310751619.1A CN103700647B (en) | 2013-12-31 | 2013-12-31 | Package substrate and the integrated circuit comprising the package substrate |
| TW103146637A TWI546909B (en) | 2013-12-31 | 2014-12-31 | A package substrate, and a semiconductor integrated circuit including the package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310751619.1A CN103700647B (en) | 2013-12-31 | 2013-12-31 | Package substrate and the integrated circuit comprising the package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103700647A true CN103700647A (en) | 2014-04-02 |
| CN103700647B CN103700647B (en) | 2018-03-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310751619.1A Active CN103700647B (en) | 2013-12-31 | 2013-12-31 | Package substrate and the integrated circuit comprising the package substrate |
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| Country | Link |
|---|---|
| CN (1) | CN103700647B (en) |
| TW (1) | TWI546909B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728382A (en) * | 2004-07-28 | 2006-02-01 | 恩益禧电子股份有限公司 | Semiconductor device |
| JP2007234663A (en) * | 2006-02-27 | 2007-09-13 | Kyocera Corp | Wiring board, and electronic device employing it |
| KR100791697B1 (en) * | 2006-08-29 | 2008-01-03 | 동부일렉트로닉스 주식회사 | Metal line structure and method for forming metal line of semiconductor device |
| US20090230562A1 (en) * | 2008-03-11 | 2009-09-17 | Hideaki Kondou | Semiconductor integrated circuit device |
| JP2013222929A (en) * | 2012-04-19 | 2013-10-28 | Renesas Electronics Corp | Multilayer wiring board |
| CN203800035U (en) * | 2013-12-31 | 2014-08-27 | 日月光半导体(上海)有限公司 | Packaging substrate and integrated circuit having same |
-
2013
- 2013-12-31 CN CN201310751619.1A patent/CN103700647B/en active Active
-
2014
- 2014-12-31 TW TW103146637A patent/TWI546909B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728382A (en) * | 2004-07-28 | 2006-02-01 | 恩益禧电子股份有限公司 | Semiconductor device |
| JP2007234663A (en) * | 2006-02-27 | 2007-09-13 | Kyocera Corp | Wiring board, and electronic device employing it |
| KR100791697B1 (en) * | 2006-08-29 | 2008-01-03 | 동부일렉트로닉스 주식회사 | Metal line structure and method for forming metal line of semiconductor device |
| US20090230562A1 (en) * | 2008-03-11 | 2009-09-17 | Hideaki Kondou | Semiconductor integrated circuit device |
| JP2013222929A (en) * | 2012-04-19 | 2013-10-28 | Renesas Electronics Corp | Multilayer wiring board |
| CN203800035U (en) * | 2013-12-31 | 2014-08-27 | 日月光半导体(上海)有限公司 | Packaging substrate and integrated circuit having same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103700647B (en) | 2018-03-16 |
| TWI546909B (en) | 2016-08-21 |
| TW201526173A (en) | 2015-07-01 |
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