CN103699462A - Single chip microprocessor system with reliability design - Google Patents
Single chip microprocessor system with reliability design Download PDFInfo
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- CN103699462A CN103699462A CN201410006579.2A CN201410006579A CN103699462A CN 103699462 A CN103699462 A CN 103699462A CN 201410006579 A CN201410006579 A CN 201410006579A CN 103699462 A CN103699462 A CN 103699462A
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Abstract
The invention relates to a single chip microprocessor system with reliability design. The single chip microprocessor system comprises a first central processor, a second central processor, a random access storage device and a read-only memory, wherein when the first central processor is malfunctioned, the first central processor is isolated, and the task processed by the first central processor is changed to be processed by the second central processor. The single chip microprocessor with the reliability design is provided with the two central processors, when one central processor is malfunctioned, the other central processor can be used, so that the reliability is greatly improved; moreover, a charging control chip also can be used for processing partial tasks when the charging is not needed, so that the performance of the single chip microprocessor can be improved, and the cost is reduced.
Description
Technical field
The present invention relates to a kind of Single Chip Microcomputer (SCM) system, more specifically, relate to a kind of Single Chip Microcomputer (SCM) system with reliability design.
Background technology
Single-chip microcomputer is a kind of integrated circuit (IC) chip, to adopt very large scale integration technology the central processing unit with data-handling capacity, the functions (may also comprise the circuit such as display driver circuit, pulse-width modulation circuit, analog multiplexer, A/D converter) such as random access memory, ROM (read-only memory), multiple I/O mouth and interrupt system, timer/counter are integrated into the little and perfect microcomputer system forming on a silicon chip, in industrial control field widespread use.From the eighties in last century, by 4,8 single-chip microcomputers at that time, develop into the high-speed microprocessor of present 300M.At present, single-chip microcomputer has been widely used in the fields such as household electrical appliance, industrial automation, Aero-Space and automotive electronics.
Yet, in some cases, such as in rugged surroundings, the reliability of Single Chip Microcomputer (SCM) system is had to higher requirement, especially when processing important event, can not be interrupted work, need to there is reliability design, such as reliability designs such as hardware redundancies.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of Single Chip Microcomputer (SCM) system with reliability design.
The Single Chip Microcomputer (SCM) system with reliability design provided by the invention, concrete technical scheme is as follows:
A kind of Single Chip Microcomputer (SCM) system with reliability design, comprise the first central processing unit, the second central processing unit, random access memory and ROM (read-only memory), wherein, when the first central processing unit breaks down, isolation the first central processing unit the task that the first central processing unit is processed switch to by the second central processing unit to be processed.
Preferably, while normally working, described the first central processing unit and described the second central processing unit are worked simultaneously and process respectively different tasks; Described Single Chip Microcomputer (SCM) system also comprises detection commutation circuit, whether described detection commutation circuit breaks down for detection of described the first central processing unit, if described detection commutation circuit is determined when the first central processing unit breaks down, described detection commutation circuit is isolated described the first central processing unit and the task of the first central processing unit processing is switched to by the second central processing unit and processed, and by the second central processing unit, processes all tasks.
Preferably, described Single Chip Microcomputer (SCM) system is by external power supply or rechargeable battery powered, and described Single Chip Microcomputer (SCM) system also comprises electrical measurement unit and charge controlling chip, when described external power supply is powered to Single Chip Microcomputer (SCM) system, described rechargeable battery is charged to described rechargeable battery by described external power supply under the control of charge controlling chip, and when described external power supply disconnects, described rechargeable battery is powered to Single Chip Microcomputer (SCM) system, described electrical measurement unit is for measuring the electric weight of described rechargeable battery, after processing at the first central processing unit of task switches to and is processed by the second central processing unit, described detection commutation circuit and described electrical measurement unit communications are also obtained the electric weight of described rechargeable battery, if the electric weight of described rechargeable battery is greater than first threshold, described detection commutation circuit isolate being connected of described charge controlling chip and rechargeable battery and task that the second central processing unit is processed in part task switch to by described charge controlling chip and process, be that described the second central processing unit and described charge controlling chip are worked simultaneously and process respectively different tasks, after this, when described electrical measurement unit inspection is less than Second Threshold to the electric weight of described rechargeable battery, send look-at-me to described detection commutation circuit, the task that described detection commutation circuit is processed described charge controlling chip switches to by the second central processing unit to be processed, by the second central processing unit, process all tasks, and described detection commutation circuit is recovered being connected of described charge controlling chip and rechargeable battery, wherein Second Threshold is less than first threshold.
Preferably, described the first central processing unit sends continuous impulse to described detection commutation circuit when work, and while not receiving yet next pulse after being greater than Preset Time, described detection commutation circuit determines that the first central processing unit breaks down.
Preferably, when described the first central processing unit and described the second central processing unit are worked simultaneously and process respectively different tasks, or when described the second central processing unit and described charge controlling chip are worked simultaneously and process respectively different tasks, described random access memory is that described the first central processing unit and described the second central processing unit or described the second central processing unit and described charge controlling chip are shared, and at described first central processing unit of the moment, in described the second central processing unit or described charge controlling chip, only has a described random access memory of access.
Preferably, described random access memory comprises arbitration circuit.
Preferably, described random access memory is dual-port random access memory.
Preferably, two of described dual-port random access memory ports connect respectively the first central processing unit and described the second central processing unit.
Preferably, part task in the task that described detection commutation circuit is processed the second central processing unit switches to while being processed by described charge controlling chip, and described detection commutation circuit is connected described dual-port random access memory port with the first central processing unit switches to described charge controlling chip and is connected.
The beneficial effect with the Single Chip Microcomputer (SCM) system of reliability design provided by the invention is: configured two central processing units, one is broken down and can take over processing by another, reliability strengthens, and, when without charging, charge controlling chip also can be taken over the processing of part task, has not only improved the performance of Single Chip Microcomputer (SCM) system but also reduced cost.
Accompanying drawing explanation
Fig. 1 is the schematic diagram with the Single Chip Microcomputer (SCM) system of reliability design provided by the present invention;
Reference numeral 101-the first central processing unit wherein; 102-the second central processing unit; 103-random access memory; 104-ROM (read-only memory); 105-detects commutation circuit; 201-electrical measurement unit; 202-charge controlling chip.
Embodiment
Now by reference to the accompanying drawings the present invention is described further.
As Fig. 1 shows the schematic diagram with the Single Chip Microcomputer (SCM) system of reliability design provided by the present invention.A kind of Single Chip Microcomputer (SCM) system with reliability design, comprise the first central processing unit 101, the second central processing unit 102, random access memory 103 and ROM (read-only memory) 104, wherein, when the first central processing unit 101 breaks down, isolation the first central processing unit 101 task that the first central processing unit 101 is processed switch to by the second central processing unit 102 to be processed.
Preferably, while normally working, described the first central processing unit 101 and described the second central processing unit 102 are worked simultaneously and process respectively different tasks; Described Single Chip Microcomputer (SCM) system also comprises detection commutation circuit 105, whether described detection commutation circuit 105 breaks down for detection of described the first central processing unit 101, if described detection commutation circuit 105 is determined when the first central processing unit 101 breaks down, described detection commutation circuit 105 described the first central processing units 101 of isolation and the task that the first central processing unit 101 is processed switch to by the second central processing unit 102 to be processed, and by the second central processing unit 102, processes all tasks.
Preferably, described Single Chip Microcomputer (SCM) system is by external power supply or rechargeable battery powered, and described Single Chip Microcomputer (SCM) system also comprises electrical measurement unit 201 and charge controlling chip 202; When described external power supply is powered to Single Chip Microcomputer (SCM) system, described rechargeable battery is charged to described rechargeable battery by described external power supply under the control of charge controlling chip 202, and when described external power supply disconnects, described rechargeable battery is powered to Single Chip Microcomputer (SCM) system; described electrical measurement unit 201 is for measuring the electric weight of described rechargeable battery, after processing at the first central processing unit 101 of task switches to and is processed by the second central processing unit 102, described detection commutation circuit 105 and 201 communications of described electrical measurement unit are also obtained the electric weight of described rechargeable battery, if the electric weight of described rechargeable battery is greater than first threshold, the part task in being connected and the second central processing unit 102 being processed of the task of the described charge controlling chip 202 of described detection commutation circuit 105 isolation and rechargeable battery switches to by described charge controlling chip 202 processing, be that described the second central processing unit 102 and described charge controlling chip 202 are worked simultaneously and process respectively different tasks, after this, the electric weight that described rechargeable battery detected when described electrical measurement unit 201 is less than Second Threshold, send look-at-me to described detection commutation circuit 105, the task that described detection commutation circuit 105 is processed described charge controlling chip 202 switches to by the second central processing unit 102 and processes, by the second central processing unit 102, process all tasks, and the described charge controlling chip 202 of described detection commutation circuit 105 recovery is connected with rechargeable battery, wherein Second Threshold is less than first threshold.
The present invention, by two central processing units of configuration, if one of them breaks down, can take over processing by another, has greatly strengthened reliability, and central processing unit can be worked simultaneously but process different tasks, both can be the task of processing different peripheral, such as a central processing unit is responsible for processing vedio data, and another central processing unit is responsible for processing audio data, also can be to process task of different nature, such as a central processing unit is responsible for the tasks such as storage of deal with data, and another central processing unit is responsible for real time signal processing, in the present invention, when a central processing unit breaks down as the first central processing unit 101, can process all tasks by the second central processing unit 102 burdens, in addition, when the electric weight of rechargeable battery is greater than first threshold without charging, charge controlling chip is also used as central processing unit, share the processing of part task, like this, not only improve the performance of Single Chip Microcomputer (SCM) system but also reduced cost, and if electrical measurement unit 201 detects the electric weight of described rechargeable battery, to be less than Second Threshold be that electric weight is lower time (this situation is the situation that there is no external power supply), send look-at-me to described detection commutation circuit 105, and described charge controlling chip 202 is switched to, rechargeable battery is charged, the use of look-at-me makes to inquire about in real time or discontinuously the electric weight of battery without detecting commutation circuit 105, thereby can relatively reduce the power consumption of system.First threshold can be for example rechargeable battery Full Charge Capacity 60%, Second Threshold can be for example rechargeable battery Full Charge Capacity 30%, by setting respectively such two threshold values of first threshold and Second Threshold, in the time of can avoiding single threshold value, the electric weight of rechargeable battery just approaches this single threshold value and charge controlling chip 202 is switched repeatedly and causes system to be absorbed in endless loop or cause hardware damage.
Preferably, described the first central processing unit 101 sends continuous impulse to described detection commutation circuit 105 when work, and while not receiving yet next pulse after being greater than Preset Time, described detection commutation circuit 105 determines that the first central processing unit 101 breaks down.
Preferably, when described the first central processing unit 101 and described the second central processing unit 102 are worked simultaneously and process respectively different tasks, or when described the second central processing unit 102 and described charge controlling chip 202 are worked simultaneously and process respectively different tasks, described random access memory 103 is that described the first central processing unit 101 and described the second central processing unit 102 or described the second central processing unit 102 and described charge controlling chip 202 are shared, and at a moment first central processing unit 101, in described the second central processing unit 102 or described charge controlling chip 202, only has a described random access memory 103 of access.
Preferably, described random access memory 103 comprises arbitration circuit.Arbitration circuit can be so that only have a described random access memory 103 of access in a moment first central processing unit 101, described the second central processing unit 102 or described charge controlling chip 202, thereby prevent conflict and produce wrong data.
Preferably, described random access memory 103 is dual-port random access memory.Dual-port random access memory is a kind of special data-storing chip, there is two covers completely independently data line, address wire, read-write control line, allow two CPU (central processing unit) to carry out access to the same unit of dual-port random access memory, there is completely independently interrupt logic of two covers, realize the control signal of shaking hands between two CPU (central processing unit), guarantee that two CPU (central processing unit) carry out the correctness of read-write operation to same unit simultaneously.
Preferably, two of described dual-port random access memory ports connect respectively the first central processing unit 101 and described the second central processing unit 102.
Preferably, part task in the task that described detection commutation circuit 105 is processed the second central processing unit 102 switches to while being processed by described charge controlling chip 202, and described detection commutation circuit 105 is connected described dual-port random access memory 103 port with the first central processing unit 101 switches to described charge controlling chip 202 and is connected.
In the Single Chip Microcomputer (SCM) system with reliability design provided by the invention, two central processing units have been configured, one is broken down and can take over processing by another, reliability strengthens, and, when without charging, charge controlling chip also can be taken over the processing of part task, has not only improved the performance of Single Chip Microcomputer (SCM) system but also reduced cost.
Certainly, the above is only preferred embodiment of the present invention, and the present invention is not limited to above-described embodiment and implementation method.The practitioner of correlative technology field can carry out different variations and enforcement in the scope of technological thought license of the present invention, the equivalence of doing according to structure, feature and principle described in patent claim of the present invention therefore all changes or modifies, and is included in patent claim of the present invention.
Claims (9)
1. a Single Chip Microcomputer (SCM) system with reliability design, comprise the first central processing unit, the second central processing unit, random access memory and ROM (read-only memory), it is characterized in that: when the first central processing unit breaks down, isolation the first central processing unit the task that the first central processing unit is processed switch to by the second central processing unit to be processed.
2. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 1, is characterized in that: while normally working, described the first central processing unit and described the second central processing unit are worked simultaneously and process respectively different tasks; Described Single Chip Microcomputer (SCM) system also comprises detection commutation circuit, whether described detection commutation circuit breaks down for detection of described the first central processing unit, if described detection commutation circuit is determined when the first central processing unit breaks down, described detection commutation circuit is isolated described the first central processing unit and the task of the first central processing unit processing is switched to by the second central processing unit and processed, and by the second central processing unit, processes all tasks.
3. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 2, is characterized in that: described Single Chip Microcomputer (SCM) system is by external power supply or rechargeable battery powered, and described Single Chip Microcomputer (SCM) system also comprises electrical measurement unit and charge controlling chip, when described external power supply is powered to Single Chip Microcomputer (SCM) system, described rechargeable battery is charged to described rechargeable battery by described external power supply under the control of charge controlling chip, and when described external power supply disconnects, described rechargeable battery is powered to Single Chip Microcomputer (SCM) system, described electrical measurement unit is for measuring the electric weight of described rechargeable battery, after processing at the first central processing unit of task switches to and is processed by the second central processing unit, described detection commutation circuit and described electrical measurement unit communications are also obtained the electric weight of described rechargeable battery, if the electric weight of described rechargeable battery is greater than first threshold, described detection commutation circuit isolate being connected of described charge controlling chip and rechargeable battery and task that the second central processing unit is processed in part task switch to by described charge controlling chip and process, be that described the second central processing unit and described charge controlling chip are worked simultaneously and process respectively different tasks, after this, when described electrical measurement unit inspection is less than Second Threshold to the electric weight of described rechargeable battery, send look-at-me to described detection commutation circuit, the task that described detection commutation circuit is processed described charge controlling chip switches to by the second central processing unit to be processed, by the second central processing unit, process all tasks, and described detection commutation circuit is recovered being connected of described charge controlling chip and rechargeable battery, wherein Second Threshold is less than first threshold.
4. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 3, it is characterized in that: described the first central processing unit sends continuous impulse to described detection commutation circuit when work, while not receiving yet next pulse after being greater than Preset Time, described detection commutation circuit determines that the first central processing unit breaks down.
5. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 3, it is characterized in that: when described the first central processing unit and described the second central processing unit are worked simultaneously and process respectively different tasks, or when described the second central processing unit and described charge controlling chip are worked simultaneously and process respectively different tasks, described random access memory is that described the first central processing unit and described the second central processing unit or described the second central processing unit and described charge controlling chip are shared, and at described first central processing unit of the moment, in described the second central processing unit or described charge controlling chip, only has a described random access memory of access.
6. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 1, is characterized in that: described random access memory comprises arbitration circuit.
7. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 3, is characterized in that: described random access memory is dual-port random access memory.
8. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 7, is characterized in that: two ports of described dual-port random access memory connect respectively the first central processing unit and described the second central processing unit.
9. the Single Chip Microcomputer (SCM) system with reliability design as claimed in claim 8, it is characterized in that: the part task in the task that described detection commutation circuit is processed the second central processing unit switches to while being processed by described charge controlling chip, and described detection commutation circuit is connected described dual-port random access memory port with the first central processing unit switches to described charge controlling chip and is connected.
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| CN113342613A (en) * | 2021-06-25 | 2021-09-03 | 深圳市商汤科技有限公司 | Data processing apparatus, data processing method, computer device, and storage medium |
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