CN103684455B - Single channel ADC fault diagnosis and restoration methods in many adc datas acquisition system - Google Patents
Single channel ADC fault diagnosis and restoration methods in many adc datas acquisition system Download PDFInfo
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Abstract
The invention discloses single channel ADC fault diagnosis and restoration methods in a kind of many adc datas acquisition system, the method is: FPGA is diagnosed to be fault ADC in passage, respectively data updating rate f to each passage ADC automaticallyDATAIt is monitored, if the f that fpga logic recordsDATAValue is inconsistent with the value set, and thinks fault, otherwise the most normal；It will be resetted after being diagnosed to be fault ADC by FPGA, and reconfigure the parameters of this ADC, and parameter configuration is entirely by reference to the ADC of normal channel；FPGA sends the analog digital conversion moment at an appropriate time point to fault ADC after resetting, reconfiguring and adjusts order again, can be achieved with fault ADC and exports Tong Bu with the data of other normal channels ADC.The present invention has quick diagnosis, reliability high.
Description
Technical field
The invention belongs to data acquisition technology field, particularly relate to a kind of multi-channel parallel, synchronous data collection
Method.
Background technology
At present, in field of inertia measurement, accelerometer is used to measure movable body three-dimensional acceleration letter
Number, navigation information is to be obtained time integral by acceleration.Acceleration is integrated available speed to the time,
Speed can get positional information through an integration again.Before to time integral, it is necessary to assure on three directions
Acceleration information be synchronization, i.e. time synchronized.If it is asynchronous, then to be extrapolated by integration
Navigation information is the most unreliable.In the occasion that the similar this data to multi-channel synchronous have time synchronized to require,
Data collecting system to be accomplished can each channel data of synchronous acquisition.
The multi-channel synchronous data acquisition system of current main-stream is based on FPGA (FPGA, Field
Programmable Gate Array, field programmable gate array), it have parallel processing, rich interface with
And the advantage of flexible in programming, applicable multi-channel A/D C of collection simultaneously (ADC, Analog-to-Digital Converter,
Analog-digital converter) data.FPGA is connected with each passage ADC, for each passage ADC by the interface of self
Independent controlling of sampling sequential and common sampling clock are provided.
For described multi-channel synchronous data acquisition system, when the ADC of one of them passage occurs such as single
During the non-destructive faults such as particle locking, exceptional reset, fault ADC and other normal ADC are the most same
Step, causes system operation irregularity.Fault ADC is carried out reset restart, ADC after now restarting and its
He normal ADC is nonsynchronous, thus each passage adc data causing FPGA to collect is not same
Moment.Therefore, it is achieved fault ADC and the re-synchronization of other normal channels ADC, it is that multichannel is same
Step data acquisition system recovers normal premise.But, a kind of effective method can be accomplished
On the premise of not affecting normal channel adc data gathered, it is achieved ADC after fault recovery and other
The re-synchronization of ADC.
Summary of the invention
Instant invention overcomes the deficiencies in the prior art, it is provided that single channel ADC in a kind of many adc datas acquisition system
Fault diagnosis and restoration methods.The method can be diagnosed to be faulty channel ADC automatically, then to fault ADC
Carry out resetting and the analog digital conversion moment adjust again, thus realize after fault ADC is recovered with other normal channels
ADC's is the most subsynchronous.
For reaching above-mentioned purpose, the present invention adopts the following technical scheme that in a kind of many adc datas acquisition system
Single channel ADC fault diagnosis and restoration methods, the method realizes in many ADC Channels Synchronous Data Acquisition System,
Described many ADC Channels Synchronous Data Acquisition System is made up of FPGA and multichannel ADC；Described FPGA conduct
Master controller is connected with each passage ADC, control each passage ADC synchronize conversion, and parallel, synchronize adopt
Collect the data of each passage ADC；It is characterized in that: the method is particularly as follows: described FPGA is diagnosed to be logical automatically
Fault ADC in road, described FPGA data updating rate f to each passage ADC respectivelyDATAIt is monitored,
If the f that fpga logic recordsDATAValue is inconsistent with the value set, and thinks fault, otherwise the most normal；Described
It will be resetted after being diagnosed to be fault ADC by FPGA, and reconfigure the parameters of this ADC,
Parameter configuration is entirely by reference to the ADC of normal channel；Described FPGA an appropriate time point to through reset,
Fault ADC after reconfiguring sends the analog digital conversion moment and adjusts order again, can be achieved with fault ADC with
The data output of other normal channels ADC synchronizes.
The invention has the beneficial effects as follows, the present invention only needs individually to reset fault ADC, reconfigure with
And the operation such as analog digital conversion moment adjustment again, it is not related to the interference to normal channel ADC analog digital conversion, can be real
Do not affect now on the premise of normal channel adc data is gathered, it is achieved ADC after fault recovery and its
The re-synchronization of he ADC.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, required in below embodiment being described
Accompanying drawing to be used is made one and is simply introduced.
The structure of the multi-channel synchronous data acquisition system based on FPGA that Fig. 1 provides for the embodiment of the present invention
Figure；
The sequential chart of the method for the three road ADC synchronized samplings that Fig. 2 provides for the embodiment of the present invention；XDRDY
Convert marking signal for ADC device #1, YDRDY be ADC device #2 convert mark
Will signal, ZDRDY respectively ADC device #3 converts marking signal, Low level effective；Sync
Pulse is the ADC analog digital conversion moment to adjust order；TadsIt is issued to ADC first for adjusting order from conversion
Time required for the individual effectively edge appearance converting marking signal；fDATAData for ADC update frequency
Rate；
Fault ADC that Fig. 3 provides for the embodiment of the present invention recover after the schematic diagram of re-synchronization method；
Zsync is the analog digital conversion moment of ADC device #3 (fault ADC) to adjust order.
Detailed description of the invention
Multi-channel synchronous data acquisition system is made up of on-site programmable gate array FPGA and multi-channel A/D C, respectively
Individual passage ADC is same model；Described FPGA is connected with each passage ADC as master controller, control
Make each passage ADC synchronize conversion and gather.
Described ADC has switch instant and controls pin, when this pin receives and effectively triggers pulse, and ADC
Current analog digital conversion state can be terminated, start the conversion of a new round；After each EOC of described ADC,
Will produce and convert marking signal；Described ADC is normally operated under continuous translative mode, converts
Marking signal is with f set in advanceDATAFrequency occurs.
Described FPGA data updating rate f to each passage ADC respectivelyDATAIt is monitored, if FPGA patrols
Collect the f recordedDATAValue is inconsistent with the value set, and thinks fault, otherwise the most normal；Described monitoring method is:
By fpga logic, adjacent two are converted the interval that marking signal occurs and carry out clock pulse count, real
Time calculate fDATAValue.
It will be resetted after being diagnosed to be fault ADC by described FPGA, and reconfigure each of this ADC
Item parameter, parameter configuration is entirely by reference to the ADC of normal channel.
Described FPGA sends analog digital conversion at appropriate time point ADC after fault recovery and adjusts life
Order, can be achieved with the ADC after fault recovery Tong Bu with the output of the data of other normal channels ADC, described
A proper time point be to be calculated by the anti-method pushed away, described Backstipping design is described as follows:
FPGA with normal channel ADC convert marking signal effectively along as time zero, time delay m
After time, the ADC after fault recovery sends conversion adjustment order,
M value meets functional relationship: N* (1/fDATA)=Tads+m (a)
Wherein, Tads(known quantity): be issued to ADC first from conversion adjustment order and convert mark letter
Number effectively along the time required for occurring；1/fDATA(known quantity): convert marking signal for ADC
Effectively along the interval occurred, i.e. the data update cycle of ADC；N is positive integer；
According to functional relation (a), m value after choosing N value, just can be calculated in turn.Then, calculate
Also this appropriate time point it has been known that after going out m value.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of the present invention, based on
The embodiment that the present invention provides, in the every other embodiment not making creative work and obtain, broadly falls into this
The scope of invention protection.
Embodiments provide a kind of multi-channel synchronous data parallel based on FPGA, synchronous acquisition side
Method, as shown in Figure 1.ADC device #1, #2, #3 specification is: ADS1281, FPGA4 and three
Road ADC is joined directly together, and each tunnels analogy input signal sends into the device of each self-corresponding ADC, by FPGA
Logic controls the synchronous acquisition of each ADC, and FPGA provides unified sampling clock FCLK=for each ADC
4.096MHZ。
The self-diagnosis technology of a kind of ADC fault that the embodiment of the present invention provides, as shown in Figure 2.The present embodiment
Middle supposition ADC device #3 breaks down, and ADC device #1 and #2 is normal.On FPGA Zhong Dui tri-tunnel
The XDRDY of ADC, adjacent two trailing edges interval of YDRDY, ZDRDY signal carries out pulse parallel
Counting.The f of ZDRDYDATAValue is substantially greater than standard value, it is believed that ADC device #3 breaks down.
A kind of fault ADC self-restoring technology that the embodiment of the present invention provides, as it is shown on figure 3, time delay m adds
TadsTotal time length can adjacent equal to ADC two convert the integers of interval times that marking signal occurs
Times, i.e. m value meets functional relation N* (1/fDATA)=Tads+m.In the present embodiment, the data of each ADC are more
New rate fDATAFor 16K, fclkFor the periodicity of sampling clock (frequency is 4.096MHZ), then 1/fDATA=
256fclk, f can be found from the technical documentation of ADS1281 simultaneouslyDATAFor T corresponding during 16Kads=1672
fclk, when therefore taking N=7, counter can release m=120fclk.Fpga logic is with XDRDY or YDRDY
Trailing edge be time zero, after 120 sampling clock cycle of time delay when fault ADC sends analog digital conversion
Carve and adjust order zsync, can be realized as behind 7 XDRDY interval ZDRDY Yu XDRDY and
The re-synchronization of YDRDY.
Claims (5)
1. single channel ADC fault diagnosis and a restoration methods in the acquisition system of adc data more than, the method realizes in many ADC Channels Synchronous Data Acquisition System, and described many ADC Channels Synchronous Data Acquisition System is made up of FPGA and multichannel ADC；Described FPGA is connected with each passage ADC as master controller, control each passage ADC synchronize conversion, and parallel, the data of synchronous acquisition each passage ADC；It is characterized in that: the method particularly as follows: described FPGA is diagnosed to be fault ADC in passage automatically, described FPGA data updating rate f to each passage ADC respectivelyDATAIt is monitored, if the f that fpga logic recordsDATAValue is inconsistent with the value set, and thinks fault, otherwise the most normal；It will be resetted after being diagnosed to be fault ADC by described FPGA, and reconfigure the parameters of this ADC, and parameter configuration is entirely by reference to the ADC of normal channel；Described FPGA sends the analog digital conversion moment at an appropriate time point to fault ADC after resetting, reconfiguring and adjusts order again, can be achieved with fault ADC and exports Tong Bu with the data of other normal channels ADC.
Single channel ADC fault diagnosis and restoration methods in the most adc datas acquisition system, it is characterized in that: described FPGA is joined directly together with each passage ADC by the interface of self, unified sampling clock, and independent controlling of sampling sequential is provided for each passage ADC.
Single channel ADC fault diagnosis and restoration methods in the most adc datas acquisition system, it is characterised in that: described FPGA data updating rate f to each passage ADC respectivelyDATAIt is monitored, particularly as follows: after each EOC of described ADC, all can produce and convert marking signal；Described ADC is normally operated under continuous translative mode, converts marking signal with the good f of software arrangementsDATAFrequency occurs；The marking signal that converts of described ADC is attached directly on the I/O pin of FPGA, fpga logic convert the interval that marking signal occurs to adjacent two and carry out clock pulse count, calculate f in real timeDATAValue.
Single channel ADC fault diagnosis and restoration methods in the most adc datas acquisition system, it is characterized in that: fault ADC is resetted and reconfigures by described FPGA, particularly as follows: the reset pin of described fault ADC and other normal channels ADC is respectively coupled on the I/O pin of FPGA, fpga logic controls each ADC respectively and reset；Described fault ADC is operated under continuous translative mode after resetting and reconfiguring, its data updating rate fDATAAs the ADC of normal channel, but data output is asynchronous.
Single channel ADC fault diagnosis and restoration methods in the most adc datas acquisition system, it is characterized in that: described FPGA sends analog digital conversion at an appropriate time point to fault ADC and adjusts order, can be achieved with the ADC after fault recovery Tong Bu with the output of the data of other normal channels ADC, particularly as follows: described ADC has switch instant controls pin, described switch instant controls pin and is attached directly on the I/O pin of FPGA, when FPGA controls pin transmission triggering pulse to the switch instant of ADC, ADC can terminate current analog digital conversion state, start the conversion of a new round；One proper time point is to be calculated by the anti-method pushed away, described Backstipping design is described as follows: FPGA with normal channel ADC convert marking signal effectively along as time zero, after the time delay m time, ADC after fault recovery sends conversion and adjusts order, and m value meets functional relationship: N* (1/fDATA)= Tads
+ m；Wherein, TadsFor from conversion adjust order be issued to ADC first convert marking signal effectively along the time required for occurring；1/fDATAMarking signal is converted effectively along the interval occurred, i.e. the data update cycle of ADC for ADC；N is positive integer；M value just can be calculated in turn after choosing N value according to above formula；Then, this appropriate time point also it has been known that after calculating m value.
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| CN105099449B (en) * | 2015-07-21 | 2018-06-08 | 深圳市同川科技有限公司 | ADC automatic fault diagnosis methods |
| CN110609499B (en) * | 2019-09-18 | 2021-06-29 | 深圳市航顺芯片技术研发有限公司 | Method and device for switching analog-to-digital converter (ADC) real-time sampling and non-real-time sampling |
| CN112290946B (en) * | 2020-09-16 | 2022-12-06 | 中国航空工业集团公司洛阳电光设备研究所 | High-reliability AD sampling method for POWER-DOWN mode |
| CN113518300B (en) * | 2021-06-15 | 2023-12-22 | 翱捷科技(深圳)有限公司 | I2S-based automatic configuration method and system for parameters of audio acquisition chip |
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| US8279100B2 (en) * | 2010-09-30 | 2012-10-02 | Lockheed Martin Corporation | Complex analog to digital converter (CADC) system on chip double rate architecture |
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| Title |
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| 多片AD并行数据采集技术的研究与实现;刘进军;《中国优秀硕士学位论文全文数据库 信息科技辑》;20051115(第07期);I136-605 * |
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