CN103684455A

CN103684455A - One-channel ADC (Analog to Digital Converter) fault diagnosis and recovery method in multi-ADC data acquisition system

Info

Publication number: CN103684455A
Application number: CN201310576706.8A
Authority: CN
Inventors: 叶凌云; 宋开臣; 罗云; 黄添添; 朱智娟
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2013-11-19
Filing date: 2013-11-19
Publication date: 2014-03-26
Anticipated expiration: 2033-11-19
Also published as: CN103684455B

Abstract

The invention discloses a one-channel ADC (Analog to Digital Converter) fault diagnosis and recovery method in a multi-ADC data acquisition system. The method comprises the following steps: an FPGA (Field Programmable Gate Array) automatically diagnoses a failed ADC in a channel, and respectively monitors a data update rate of an fDATA in each channel; if an fDATA value monitored by an FPGA logic is not consistent with a set value, then a fault is detected, and otherwise a normal state is detected; after the FPGA diagnoses the failed ADC, the failed ADC is reset, and parameters of the failed ADC are reconfigured, wherein the reconfigured parameters completely refer to the ADC in a normal channel; and the FPGA, at a proper time point, sends an analog-to-digital conversion moment readjustment instruction to the failed ADC which is reset and reconfigured, and then data output synchronization can be achieved for the failed ADC and other ADCs in the normal channel. According to the invention, the characteristics of rapid diagnosis, high reliability, and the like are realized.

Description

Single channel ADC failure diagnosis and restoration methods in many adc datas acquisition system

Technical field

The invention belongs to data acquisition technology field, relate in particular to a kind of multi-channel parallel, synchronous data collection method.

Background technology

At present, in inertia measurement field, accelerometer is used to measure the three-dimensional acceleration signal of movable body, and navigation information is by acceleration, time integral to be obtained.Acceleration carries out integration to the time can obtain speed, and speed can obtain positional information through an integration again.Before to time integral, must guarantee that the acceleration information in three directions is synchronization, i.e. time synchronized.If asynchronous, the navigation information of being extrapolated by integration is so just unreliable.Similar this to the free synchronous occasion requiring of the data of multi-channel synchronous, data acquisition system will be accomplished can each channel data of synchronous acquisition.

The multi-channel synchronous data acquisition system of current main-stream is based on FPGA(FPGA, Field Programmable Gate Array, field programmable gate array), it has the advantage of parallel processing, rich interface and flexible in programming, be applicable to gathering multi-channel A/D C(ADC simultaneously, Analog-to-Digital Converter, analog to digital converter) data.FPGA is connected with each passage ADC by the interface of self, for each passage ADC provides independently controlling of sampling sequential and common sampling clock.

For described multi-channel synchronous data acquisition system, when the fault such as the non-destructive such as locking single particle, exceptional reset occurs the ADC of one of them passage, fault ADC is just no longer synchronizeed with other normal ADC, causes system works abnormal.Fault ADC is resetted and restarted, and the ADC after now restarting and other normal ADC are nonsynchronous, thereby cause each passage adc data that FPGA collects, are not synchronizations.Therefore, realizing the re-synchronization of fault ADC and other normal channels ADC, is that multi-channel synchronous data acquisition system is recovered normal prerequisite.Yet, do not have at present a kind of effective method and can accomplish do not affecting under the prerequisite that normal channel adc data is gathered, realize ADC after fault recovery and the re-synchronization of other ADC.

Summary of the invention

The present invention has overcome the deficiencies in the prior art, and single channel ADC failure diagnosis and restoration methods in a kind of many adc datas acquisition system is provided.The method passage ADC that can automatic diagnosis be out of order, then resets to fault ADC and analog-to-digital conversion is adjusted constantly again, thereby after realizing fault ADC and recovering and other normal channels ADC subsynchronous again.

For achieving the above object, the present invention adopts following technical scheme: single channel ADC failure diagnosis and restoration methods in a kind of many adc datas acquisition system, the method realizes in many ADC Channels Synchronous Data Acquisition System, and described many ADC Channels Synchronous Data Acquisition System is comprised of FPGA and multichannel ADC; Described FPGA is connected with each passage ADC as master controller, and control each passage ADC and synchronously change, and data parallel, each passage of synchronous acquisition ADC; It is characterized in that: the method is specially: described FPGA automatic diagnosis has the fault ADC in passage, and described FPGA is the data updating rate f to each passage ADC respectively _dATAmonitor, if the f that fpga logic records _dATAvalue and the value of setting be inconsistent thinks fault, otherwise normal; Described FPGA diagnosis is out of order after ADC and will be resetted to it, and reconfigures the parameters of this ADC, and parameter configuration is completely with reference to the ADC of normal channel; Described FPGA sends analog-to-digital conversion at an appropriate time point to the fault ADC after resetting, reconfiguring and constantly adjusts order again, just can realize fault ADC and synchronize with the data output of other normal channels ADC.

The invention has the beneficial effects as follows, the present invention only needs separately fault ADC to be resetted, reconfigured and the constantly operation such as adjustment again of analog-to-digital conversion, do not relate to the analog-to-digital interference to normal channel ADC, can realize and not affecting under the prerequisite that normal channel adc data is gathered, realize ADC after fault recovery and the re-synchronization of other ADC.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, in below embodiment being described, the accompanying drawing of required use is done a simply introduction.

The structure chart of the multi-channel synchronous data acquisition system based on FPGA that Fig. 1 provides for the embodiment of the present invention;

Fig. 2 provides the sequential chart of the method for San road ADC synchronized sampling for the embodiment of the present invention; XDRDY is the marking signal that converts of ADC device #1, and YDRDY is the marking signal that converts of ADC device #2, and what ZDRDY was respectively ADC device #3 converts marking signal, Low level effective; Sync Pulse is that ADC analog-to-digital conversion is adjusted order constantly; T _adsfor conversion certainly, adjusting order is issued to ADC first converts the effective in occurring the needed time of marking signal; f _dATAfor ADC converts marking signal effectively along the interval occurring, i.e. the Data Update frequency of ADC;

The schematic diagram of the re-synchronization method after the fault ADC that Fig. 3 provides for the embodiment of the present invention recovers; Zsync is ADC device #3(fault ADC) analog-to-digital conversion constantly adjust order.

Embodiment

Multi-channel synchronous data acquisition system is comprised of on-site programmable gate array FPGA and multi-channel A/D C, and each passage ADC is same model; Described FPGA is connected with each passage ADC as master controller, controls the synchronous conversion of each passage ADC and gathers.

Described ADC has conversion and constantly controls pin, and when this pin receives effective trigger impulse, ADC can finish current analog-to-digital conversion state, starts the conversion of a new round; After the each EOC of described ADC, all can produce and convert marking signal; Described ADC is normally operated under continuous translative mode, converts marking signal with predefined f _dATAfrequency occurs.

Described FPGA is the data updating rate f to each passage ADC respectively _dATAmonitor, if the f that fpga logic records _dATAvalue and the value of setting be inconsistent thinks fault, otherwise normal; Described monitoring method is: by fpga logic, clock pulse count is carried out in adjacent two intervals that convert marking signal appearance, calculate in real time f _dATAvalue.

Described FPGA diagnosis is out of order after ADC and will be resetted to it, and reconfigures the parameters of this ADC, and parameter configuration is completely with reference to the ADC of normal channel.

Described FPGA sends analog-to-digital conversion adjustment order at an appropriate time point to the ADC after fault recovery, the ADC that just can realize after fault recovery is synchronizeed with the data output of other normal channels ADC, a described proper time point is to be calculated by the anti-method pushing away, and the described anti-method that pushes away is described below:

It is time zero that FPGA be take the effective edge that converts marking signal of normal channel ADC, and the ADC after the backward fault recovery of time delay m time sends conversion and adjusts order,

M value meets functional relation: N* (1/f _dATA)=T _ads+ m (a)

Wherein, T _ads(known quantity): conversion is adjusted order and is issued to ADC first converts the effective in occurring the needed time of marking signal certainly; 1/f _dATA(known quantity): for ADC converts marking signal effectively along the interval occurring, i.e. the Data Update cycle of ADC; N is positive integer;

According to functional relation (a), choose N value and just can calculate conversely m value afterwards.So, also just known the time point that this is appropriate after calculating m value.

Below in conjunction with the accompanying drawing in the embodiment of the present invention; technical scheme in the embodiment of the present invention is clearly and completely described; obviously; described embodiment is only a part of embodiment of the present invention; the every other embodiment obtaining not making creative work based on embodiment provided by the invention, belongs to the scope of protection of the invention.

The embodiment of the present invention provides a kind of multi-channel synchronous data parallel, synchronous collection method based on FPGA, as shown in Figure 1.ADC device #1, #2, #3 specification are: ADS1281, FPGA 4 Yu San road ADC are directly connected, each tunnels analogy input signal is sent into the device of each self-corresponding ADC, is controlled the synchronous acquisition of each ADC by fpga logic, and FPGA provides unified sampling clock FCLK=4.096MHZ for each ADC.

The self-diagnosis technology of a kind of ADC fault that the embodiment of the present invention provides, as shown in Figure 2.In the present embodiment, suppose that ADC device #3 breaks down, ADC device #1 and #2 are normal.At the XDRDY of FPGA Zhong Dui tri-road ADC, YDRDY, adjacent two trailing edge intervals of ZDRDY signal walk abreast and carry out step-by-step counting.The f of ZDRDY _dATAvalue is obviously greater than standard value, so think that ADC device #3 breaks down.

A kind of fault ADC that the embodiment of the present invention provides is from recovery technology, and as shown in Figure 3, time delay m adds T _adstotal time length can equal adjacent two integral multiples that convert the interval time that marking signal occurs of ADC, m value meets functional relation N* (1/f _dATA)=T _ads+ m.The data updating rate f of each ADC in the present embodiment _dATAfor 16K, f _clkfor the periodicity of sampling clock (frequency is 4.096MHZ), so 1/f _dATA=256 f _clk, from the technical documentation of ADS1281, can find f simultaneously _dATAcorresponding T during for 16K _ads=1672 f _clk, while therefore getting N=7, can instead release m=120 f _clk.It is time zero that fpga logic be take the trailing edge of XDRDY or YDRDY, 120 backward fault ADC of sampling clock cycle of time delay send analog-to-digital conversion and constantly adjust order zsync, behind 7 XDRDY intervals, just can realize the re-synchronization of ZDRDY and XDRDY and YDRDY.

Claims

1. single channel ADC failure diagnosis and a restoration methods in the acquisition system of adc data more than, the method realizes in many ADC Channels Synchronous Data Acquisition System, and described many ADC Channels Synchronous Data Acquisition System is comprised of FPGA and multichannel ADC etc.; Described FPGA is connected with each passage ADC as master controller, and control each passage ADC and synchronously change, and data parallel, each passage of synchronous acquisition ADC; It is characterized in that: the method is specially: described FPGA automatic diagnosis has the fault ADC in passage, and described FPGA is the data updating rate f to each passage ADC respectively _dATAmonitor, if the f that fpga logic records _dATAvalue and the value of setting be inconsistent thinks fault, otherwise normal; Described FPGA diagnosis is out of order after ADC and will be resetted to it, and reconfigures the parameters of this ADC, and parameter configuration is completely with reference to the ADC of normal channel; Described FPGA sends analog-to-digital conversion at an appropriate time point to the fault ADC after resetting, reconfiguring and constantly adjusts order again, just can realize fault ADC and synchronize with the data output of other normal channels ADC.

2. single channel ADC failure diagnosis and restoration methods in many adc datas acquisition system according to claim 1, it is characterized in that: described FPGA is directly connected with each passage ADC by the interface of self, for each passage, ADC provides unified sampling clock, and controlling of sampling sequential independently.

3. single channel ADC failure diagnosis and restoration methods in many adc datas acquisition system according to claim 1, is characterized in that: described FPGA is the data updating rate f to each passage ADC respectively _dATAmonitor, be specially: after the each EOC of described ADC, all can produce and convert marking signal; Described ADC is normally operated under continuous translative mode, converts the f that marking signal configures with software _dATAfrequency occurs; The marking signal that converts of described ADC is directly linked on the I/O pin of FPGA, by fpga logic, clock pulse count is carried out in adjacent two intervals that convert marking signal appearance, calculates in real time f _dATAvalue.

4. single channel ADC failure diagnosis and restoration methods in many adc datas acquisition system according to claim 1, it is characterized in that: described FPGA resets and reconfigures fault ADC, be specially: the reset pin of described fault ADC and other normal channels ADC is linked respectively on the I/O pin of FPGA, by fpga logic, control respectively each ADC and reset; Described fault ADC is operated under continuous translative mode after resetting and reconfiguring, its data updating rate f _dATAthe same with the ADC of normal channel, but data output is asynchronous.

5. single channel ADC failure diagnosis and restoration methods in many adc datas acquisition system according to claim 1, it is characterized in that: described FPGA sends analog-to-digital conversion adjustment order at an appropriate time point to fault ADC, the ADC that just can realize after fault recovery is synchronizeed with the data output of other normal channels ADC, be specially: described ADC has conversion and controls pin constantly, described conversion is constantly controlled pin and is directly linked on the I/O pin of FPGA, when FPGA controls pin transmission trigger impulse constantly to the conversion of ADC, ADC can finish current analog-to-digital conversion state, start the conversion of a new round, a described proper time point is to be calculated by the anti-method pushing away, the described anti-method that pushes away is described below: it is time zero that FPGA be take the effective edge that converts marking signal of normal channel ADC, ADC after the backward fault recovery of time delay m time sends conversion and adjusts order, and m value meets functional relation: N* (1/f _dATA)=T _ads+ m, wherein, T _adsfor conversion certainly, adjusting order is issued to ADC first converts the effective in occurring the needed time of marking signal, 1/f _dATAfor ADC converts marking signal effectively along the interval occurring, i.e. the Data Update cycle of ADC, N is positive integer, after choosing N value according to above formula, just can calculate conversely m value, so, also just known the time point that this is appropriate after calculating m value.