CN103681792A - Structure for improving puncture voltage of semiconductor electron device and semiconductor electron device - Google Patents
Structure for improving puncture voltage of semiconductor electron device and semiconductor electron device Download PDFInfo
- Publication number
- CN103681792A CN103681792A CN201210326246.9A CN201210326246A CN103681792A CN 103681792 A CN103681792 A CN 103681792A CN 201210326246 A CN201210326246 A CN 201210326246A CN 103681792 A CN103681792 A CN 103681792A
- Authority
- CN
- China
- Prior art keywords
- grid
- channel array
- drain electrode
- electronic device
- puncture voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 229910002601 GaN Inorganic materials 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000002090 nanochannel Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a structure for improving puncture voltage of a semiconductor electron device and the semiconductor electron device. The structure comprises a channel array consisting of a plurality of parallelly arranged micro-nano level channels; through the arrangement of the channel array in an active area, positioned between a source electrode and a drain electrode, of the semiconductor electron device and in an area below a grid electrode, the electric field distribution between grid leaks can be effectively improved, so that the off state puncture voltage and the like of the semiconductor electron device can be greatly improved. The structure is suitable for various semiconductor electron devices operating based on two-dimensional electron gas on the heterojunction interface, and meanwhile can meet the requirements of practical application.
Description
Technical field
The present invention relates to a kind of terminal structure of semiconductor device, relate in particular to a kind of structure and semi-conductor electronic device that improves semi-conductor electronic device puncture voltage.
Background technology
HFET (HFET), because have the excellent specific properties such as high electron mobility, device speed be fast, becomes one of the important devices in high-frequency microwave field.Along with the development of wide bandgap semiconductor gallium nitride (GaN) material, people have had new understanding to the performance of GaN base HFET in recent years.Due to excellent properties such as the mobility of GaN material are high, electronics saturation drift velocity is fast, critical breakdown electric field intensity is high, working junction temperature is high, GaN-HFET is not only applicable to high-frequency high-power application, and is suitable for low-frequency high-voltage high-power applications.HFET is planar device, and electric current is along plane, to flow in the quantum well forming at heterojunction.Device is under reverse bias condition, the distribution of electric field is normally inhomogeneous, generally speaking can be at gate electrode edge or drain terminal edge produce serious electric field and concentrate, and the electric field at this place can increase fast along with the increase of reverse voltage, when reaching critical breakdown strength, cause device breakdown.At this moment puncture voltage, lower than the product of critical electric field strength and grid leak spacing, is supposed the limit puncture voltage that can reach when electric field strength is consistent between grid leak in theory.
High puncture voltage means that the voltage range of device work is larger, can obtain higher power density, and the reliability of device is improved.Therefore the puncture voltage that how to improve device is the problem that electronic device researcher pays close attention to.At present, there is several different methods to improve HFET device electric breakdown strength, such as: adopt the material of high critical electric field, with GaN sill, replace GaAs sill; Under grid, increase dielectric and form MIS or MOS structure, improve critical breakdown electric field intensity, reduce electric leakage of the grid; With double heterojunction AlGaN/GaN/AlGaN, replace AlGaN/GaN etc.
Except said method, also having class methods is voltage termination structural designs of device, so-called voltage termination structural design refers to by design the electric field concentration effect in some special construction suppression devices in device, the electric field that makes device is uniformity as far as possible, thereby obtain, levels off to desirable puncture voltage.In Si power device, this class voltage termination structure has: field plate, potential dividing ring, deep trouth etc.In compound semiconductor device, take GaN HFET as example, conventional voltage termination structure is field plate structure, comprises the combination of source field plate, grid field plate, leakage field plate and these several field plates.Field plate as voltage termination structure can improve the distribution of device electric fields really, reduces peak value electric field, improves the puncture voltage of device.But field plate also can cause grid source, grid leak and source to leak the increase of parasitic capacitance, affects the operating rate of device.And, for the composite field plate structure that can effectively improve puncture voltage, i.e. source field plate, grid field plate, the combining structure of leaking field plate, the processing cost of device chip can obviously increase.
Summary of the invention
In view of many defects of the prior art, main purpose of the present invention is to provide a kind of structure that improves semi-conductor electronic device puncture voltage, it by arranging channel array structure in semi-conductor electronic device, particularly between the source of semi-conductor electronic device, drain electrode, and in the active area of grid below, produce the channel array of micro/nano level, significantly promoted the puncture voltage (approximately more than 28%) of device.
For achieving the above object, the present invention has adopted following technical scheme:
A kind of structure that improves semi-conductor electronic device puncture voltage, comprise heterojunction structure, on described heterojunction structure, be distributed with source electrode, grid and drain electrode, described heterojunction structure is comprised of upper and lower layer dissimilar materials, this upper and lower layer Bimaterial in terface place is formed with the two-dimensional electron gas that quantum well limits, wherein
On described heterojunction structure upper surface source electrode and drain electrode between, and the region that is arranged in grid below is provided with channel array, described channel array comprises that parallel two of arranging have nanoscale above to the raceway groove of micron order width, the degree of depth of described raceway groove is greater than the thickness of upper strata dissimilar materials, and grid and drain electrode are pointed to respectively in the two ends of each raceway groove
And, described grid length is Lg, spacing between described grid and drain electrode is Lgd, spacing between grid and channel array is L1, and the length of channel array is L2, and the spacing between channel array and drain electrode is L3, wherein,-Lg<L1<Lgd, L3<Lgd, L2>0.
As one of comparatively preferred scheme, the width of described raceway groove is 1nm～10 μ m.
As one of comparatively preferred scheme, in described channel array, the spacing of adjacent two raceway grooves is 1nm～10 μ m.
As one of selectable embodiment, between described grid and upper strata dissimilar materials, can form Schottky contacts, metal-insulator layer-semiconductor contacts or the contact of metal-oxide layer-semiconductor, but be not limited to this.
As one of selectable embodiment, described semi-conductor electronic device can comprise HFET.
Further, in described HFET, can adopt planar isolated or mesa-isolated.
Described semi-conductor electronic device can be selected from GaN based hemts, GaAs based hemts and InP based hemts, but is not limited to this.
Another object of the present invention is to provide a kind of semi-conductor electronic device, the structure that it comprises raising semi-conductor electronic device puncture voltage as above.
Another object of the present invention is to provide a kind of HFET, include source region, on described active area, be distributed with source electrode, grid and drain electrode, described active area is comprised of upper and lower layer dissimilar materials, this upper and lower layer Bimaterial in terface place is formed with the two-dimensional electron gas that quantum well limits, wherein
On upper surface, described active area source electrode and drain electrode between, and the region that is arranged in grid below is provided with channel array, described channel array comprises parallel a plurality of raceway grooves of arranging, the width of described raceway groove is 1nm～10 μ m, the degree of depth is greater than the thickness of upper strata dissimilar materials, and the spacing of adjacent two raceway grooves is 1nm～10 μ m, and grid and drain electrode are pointed to respectively in the two ends of each raceway groove
Simultaneously, described grid length is Lg, spacing between described grid and drain electrode is Lgd, spacing between grid and channel array is L1, and the length of channel array is L2, and the spacing between channel array and drain electrode is L3, wherein,-Lg<L1<Lgd, L3<Lgd, L2>0.
Accompanying drawing explanation
Fig. 1 a in the present invention arrives channel array structure applications the three-dimensional structure schematic diagram of Schottky gate HFET;
Fig. 1 b is the partial enlarged drawing of the channel array terminal structure of Schottky gate HFET shown in Fig. 1 a;
Fig. 1 c is the puncture voltage correlation curve figure of Schottky gate HFET shown in Fig. 1 a and common HFET;
Description of reference numerals: semiconductor 1, semiconductor 2, source electrode 3, drain electrode 4, channel array 5, grid 6, two-dimensional electron gas 7.
Embodiment
As previously mentioned, the puncture voltage that how to improve semi-conductor electronic device is that the technical problem solving is thirsted in this area always, yet, although numerous electronic device researchers has paid a large amount of research and practices, the scheme of its proposition is Shortcomings more or less all, such as, when effectively improving the puncture voltage of device, also may make the structure complicated of device, cost increases, or can make the operating rate of device reduce.
In view of this, this case inventor has also carried out in this area studying for a long period of time and a large amount of practice for a long time, and find very unexpectedly, by producing the channel array being formed by parallel a plurality of micro/nano level raceway grooves that arrange in the region between source, drain electrode, below grid in the heterojunction structure of semi-conductor electronic device, can significantly improve the puncture voltage of device, and can not impact the operating rate of device.
Based on above-mentioned unexpected discovery, this case inventor is again through lot of experiment validation, thereby proposed technical scheme of the present invention, and it is not yet seen in any open report so far.
Technical scheme of the present invention is specific as follows:
A kind of structure that improves semi-conductor electronic device puncture voltage, comprise heterojunction structure, on described heterojunction structure, be distributed with source electrode, grid and drain electrode, described heterojunction structure is comprised of upper and lower layer dissimilar materials, this upper and lower layer Bimaterial in terface place is formed with the two-dimensional electron gas that quantum well limits, wherein
On described heterojunction structure upper surface source electrode and drain electrode between, and the region that is arranged in grid below is provided with channel array, described channel array comprises that parallel two of arranging have nanoscale above to the raceway groove of micron order width, the degree of depth of described raceway groove is greater than the thickness of upper strata dissimilar materials, and grid and drain electrode are pointed to respectively in the two ends of each raceway groove
And, described grid length is Lg, spacing between described grid and drain electrode is Lgd, spacing between grid and channel array is L1, and the length of channel array is L2, and the spacing between channel array and drain electrode is L3, wherein,-Lg<L1<Lgd, L3<Lgd, L2>0.
In aforementioned channel array, channel width can be from several nanometers to several micron, such as, be preferably the scope of 1nm～10 μ m.
In aforementioned channel array, the spacing of adjacent two raceway grooves can also be for several nanometers be to several micron, such as, be preferably the scope of 1nm～10 μ m.
In aforementioned channel array, the profile geometric shape of raceway groove is regular shape or irregular shape.
In aforementioned channel array, the size of raceway groove can be identical or not identical side by side, and the shape of raceway groove also can be identical or not identical side by side.
Contacting that aforementioned grid metal forms with heterojunction structure can be Schottky contacts, or in order further to reduce the puncture voltage of grid leakage current and increase device, also can adopt the contact of metal-insulator layer-semiconductor or metal-oxide layer-semiconductor contact.
This case inventor is according to aforementioned abundant experimental results and a large amount of theoretical research, knowing operation principle of the present invention by inference should be: between grid and drain electrode, have one section of channel array, when device is in off state, that is: drain electrode connects positive voltage, source ground, gate bias is when threshold voltage is following, under grid, two-dimensional electron gas is depleted, and extend to drain terminal depletion region, if depletion region expands to channel array district, because wall scroll raceway groove nanometer is to micron-sized geometric widths restriction, electric charge in channel array district is tending towards all exhausting, according to Poisson's equation, can know that the electric field in channel array district reaches unanimity, that is: be tending towards even, so just can effectively improve the puncture voltage of device.This channel array voltage termination structure can not only improve the breakdown voltage of device, in like manner also can improve device grids reverse breakdown voltage.
In addition, it is graphical that aforementioned channel array structure can adopt contact photolithography, electron beam lithography, projection exposure, nano impression means to realize, recycle conventional etching means etc., as ICP, IBE and other process meanses are finally processed to form, therefore, its course of processing is very simple, and easy operating is with low cost.
Following only with the present invention, in HFET, be applied as example, technical scheme of the present invention is further described, wherein, this HFET can be for having field plate or there is no the GaN based hemts of field plate, also can be combined with MIS structure, or, can be also GaAs based hemts and InP based hemts etc.Meanwhile, in this HFET, also can adopt planar isolated or mesa-isolated.
Consult shown in Fig. 1 a-Fig. 1 b, it relates to a kind of Schottky gate HFET, mainly heterogenous junction epitaxy material, source electrode 3, drain electrode 4, channel array 5 and grid 6, consists of.
Wherein, heterojunction can mainly be comprised of upper strata dissimilar materials (semiconductor layer 1) and lower floor's dissimilar materials (semiconductor 2), and this semiconductor layer 1,2 can adopt any semi-conducting material that forms two-dimensional electron gas 7 at heterojunction place.
Aforementioned grid length is Lg, the spacing of grid and drain electrode is Lgd, the spacing of grid and channel array is L1, channel array length is L2, and the spacing of raceway groove and drain electrode is L3, and,-Lg<L1<Lgd, L3<Lgd, and, L2>0.
Preferably, the width W 1 of aforementioned raceway groove can be 1nm～10 μ m.
Preferably, in aforementioned channel array, the spacing W2 of adjacent two raceway grooves can be 1nm～10 μ m.
For making substantial structure feature, implementation method and the beneficial effect of nano-channel array of the present invention be easier to understand, take AlGaN/GaN HEMT as follows as example is to further nonrestrictive detailed description of technical scheme do of the present invention, it is that 80nm channel pitch W2 is 140nm that the HEMT of the present embodiment adopts wall scroll channel width W1, be highly 45nm, grid 6 metal thickness are 300nm, grid 6 length L g are 100nm, grid 6 is 0 with the spacing L1 of channel array 5, the length of channel array 5 is 300nm, and the spacing Lgd between grid 6 and drain electrode 4 is the design of 2 μ m.Consult Fig. 1 c, the puncture voltage that the present embodiment HEMT device obtains is 132V, and the puncture voltage of same gate length conventional device is 103V, and the terminal structure of this explanation channel array can make the puncture voltage of device effectively be improved (more than 28%).
It is pointed out that above-described embodiment is only explanation technical conceive of the present invention and feature, its object is to allow person skilled in the art can understand content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, within all should being encompassed in protection scope of the present invention.
Claims (9)
1. a structure that improves semi-conductor electronic device puncture voltage, comprise heterojunction structure, on described heterojunction structure, be distributed with source electrode, grid and drain electrode, described heterojunction structure is comprised of upper and lower layer dissimilar materials, this upper and lower layer Bimaterial in terface place is formed with the two-dimensional electron gas that quantum well limits, and it is characterized in that:
On described heterojunction structure upper surface source electrode and drain electrode between, and the region that is arranged in grid below is provided with channel array, described channel array comprises that parallel two of arranging have nanoscale above to the raceway groove of micron order width, the degree of depth of described raceway groove is greater than the thickness of upper strata dissimilar materials, and grid and drain electrode are pointed to respectively in the two ends of each raceway groove
And, described grid length is Lg, spacing between described grid and drain electrode is Lgd, spacing between grid and channel array is L1, and the length of channel array is L2, and the spacing between channel array and drain electrode is L3, wherein,-Lg<L1<Lgd, L3<Lgd, L2>0.
2. the structure of raising semi-conductor electronic device puncture voltage according to claim 1, is characterized in that, the width of described raceway groove is 1nm～10 μ m.
3. the structure of raising semi-conductor electronic device puncture voltage according to claim 1, is characterized in that, in described channel array, the spacing of adjacent two raceway grooves is 1nm～10 μ m.
4. the structure of raising semi-conductor electronic device puncture voltage according to claim 1, is characterized in that, forms Schottky contacts, metal-insulator layer-semiconductor contacts or the contact of metal-oxide layer-semiconductor between described grid and upper strata dissimilar materials.
5. the structure of raising semi-conductor electronic device puncture voltage according to claim 1, is characterized in that, described semi-conductor electronic device comprises HFET.
6. the structure of raising semi-conductor electronic device puncture voltage according to claim 5, is characterized in that, adopts planar isolated or mesa-isolated in described HFET.
7. according to the structure of the raising semi-conductor electronic device puncture voltage described in any one in claim 5-6, it is characterized in that, described semi-conductor electronic device is at least selected from any one in GaN based hemts, GaAs based hemts and InP based hemts.
8. a semi-conductor electronic device, is characterized in that, the structure that it comprises the raising semi-conductor electronic device puncture voltage as described in any one in claim 1-7.
9. a HFET, include source region, be distributed with source electrode, grid and drain electrode on described active area, described active area is comprised of upper and lower layer dissimilar materials, this upper and lower layer Bimaterial in terface place is formed with the two-dimensional electron gas that quantum well limits, and it is characterized in that:
On upper surface, described active area source electrode and drain electrode between, and the region that is arranged in grid below is provided with channel array, described channel array comprises parallel a plurality of raceway grooves of arranging, the width of described raceway groove is 1nm～10 μ m, the degree of depth is greater than the thickness of upper strata dissimilar materials, and the spacing of adjacent two raceway grooves is 1nm～10 μ m, and grid and drain electrode are pointed to respectively in the two ends of each raceway groove
Simultaneously, described grid length is Lg, spacing between described grid and drain electrode is Lgd, spacing between grid and channel array is L1, and the length of channel array is L2, and the spacing between channel array and drain electrode is L3, wherein,-Lg<L1<Lgd, L3<Lgd, L2>0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210326246.9A CN103681792A (en) | 2012-09-06 | 2012-09-06 | Structure for improving puncture voltage of semiconductor electron device and semiconductor electron device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210326246.9A CN103681792A (en) | 2012-09-06 | 2012-09-06 | Structure for improving puncture voltage of semiconductor electron device and semiconductor electron device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103681792A true CN103681792A (en) | 2014-03-26 |
Family
ID=50318761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210326246.9A Pending CN103681792A (en) | 2012-09-06 | 2012-09-06 | Structure for improving puncture voltage of semiconductor electron device and semiconductor electron device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103681792A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428420A (en) * | 2015-12-28 | 2016-03-23 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method thereof and thin-film transistor |
| CN110518067A (en) * | 2018-05-21 | 2019-11-29 | 中国科学院苏州纳米技术与纳米仿生研究所 | Heterojunction field effect transistor based on channel array and preparation method thereof and application |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010258148A (en) * | 2009-04-23 | 2010-11-11 | Sharp Corp | Compound semiconductor element |
| CN102201442A (en) * | 2011-04-02 | 2011-09-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Heterojunction field effect transistor based on channel array structure |
| CN102403349A (en) * | 2011-11-18 | 2012-04-04 | 中国科学院苏州纳米技术与纳米仿生研究所 | III nitride MISHEMT device |
-
2012
- 2012-09-06 CN CN201210326246.9A patent/CN103681792A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010258148A (en) * | 2009-04-23 | 2010-11-11 | Sharp Corp | Compound semiconductor element |
| CN102201442A (en) * | 2011-04-02 | 2011-09-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Heterojunction field effect transistor based on channel array structure |
| CN102403349A (en) * | 2011-11-18 | 2012-04-04 | 中国科学院苏州纳米技术与纳米仿生研究所 | III nitride MISHEMT device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428420A (en) * | 2015-12-28 | 2016-03-23 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method thereof and thin-film transistor |
| WO2017113451A1 (en) * | 2015-12-28 | 2017-07-06 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method thereof |
| US10109648B2 (en) | 2015-12-28 | 2018-10-23 | Wuhan China Star Optoelectonics Technology Co., Ltd | Semiconductor layer structure |
| CN105428420B (en) * | 2015-12-28 | 2018-12-04 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method and thin film transistor (TFT) |
| CN110518067A (en) * | 2018-05-21 | 2019-11-29 | 中国科学院苏州纳米技术与纳米仿生研究所 | Heterojunction field effect transistor based on channel array and preparation method thereof and application |
| CN110518067B (en) * | 2018-05-21 | 2023-03-07 | 中国科学院苏州纳米技术与纳米仿生研究所 | Heterojunction field effect transistor based on channel array and manufacturing method and application thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Jebalin et al. | The influence of high-k passivation layer on breakdown voltage of Schottky AlGaN/GaN HEMTs | |
| CN104282758B (en) | Metal-oxide semiconductor (MOS) with increased channel periphery（MOS）Device and the method for manufacture | |
| CN103531615A (en) | Nitride power transistor and manufacturing method thereof | |
| Jebalin et al. | Unique model of polarization engineered AlGaN/GaN based HEMTs for high power applications | |
| CN108028273A (en) | The method of semiconductor device and manufacture semiconductor device | |
| CN105118830B (en) | A kind of enhanced HEMT of integrated SBD | |
| CN102201442B (en) | Heterojunction field effect transistor based on channel array structure | |
| CN103337517B (en) | Device architecture based on III group nitride material containing multilayer back of the body potential barrier | |
| CN107093629B (en) | Enhanced HFET | |
| Ge et al. | Effects of gate work function on E-mode AlGaN/GaN HEMTs with stack gate β-Ga2O3/p-GaN structure | |
| CN103681792A (en) | Structure for improving puncture voltage of semiconductor electron device and semiconductor electron device | |
| CN105118858A (en) | A vertical tunneling field effect transistor | |
| Deng et al. | High performance enhancement-mode HEMT with 3DEG to conduct current and 3DHG as back barrier | |
| CN106601792A (en) | Gallium nitride transistor of high electron mobility and preparation method of transistor | |
| CN115472696A (en) | SiC power MOS device structure for reducing electric field at grid groove | |
| CN205723544U (en) | A kind of GaN base transistor with high electronic transfer rate | |
| CN107564960A (en) | A kind of GaNFinFETHEMT devices | |
| Wang et al. | Recessed-anode AlGaN/GaN diode with a high Baliga's FOM by combining a p-GaN cap layer and an anode-connected p-GaN buried layer | |
| TWI606574B (en) | Semiconductor device | |
| Zhu et al. | Theoretical investigation of high-voltage superjunction GaN-based vertical hetero-junction field effect transistor with ununiformly doped buffer to suppress charge imbalance effect | |
| Yoon et al. | High-performance SiC MOSFET embedded heterojunction diode with electric field protection region | |
| CN104201200B (en) | A kind of gallium nitride radical heterojunction field effect transistor with eelctric dipole Rotating fields | |
| CN109817711B (en) | Gallium nitride transverse transistor with AlGaN/GaN heterojunction and manufacturing method thereof | |
| Fei et al. | TCAD simulation of a breakdown-enhanced double channel GaN metal–insulator–semiconductor field-effect transistor with a P-buried layer | |
| Yoon et al. | A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140326 |