CN103681618B - The functional glass with through hole processes wafer - Google Patents
The functional glass with through hole processes wafer Download PDFInfo
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- CN103681618B CN103681618B CN201310428799.XA CN201310428799A CN103681618B CN 103681618 B CN103681618 B CN 103681618B CN 201310428799 A CN201310428799 A CN 201310428799A CN 103681618 B CN103681618 B CN 103681618B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Abstract
The functional glass that the present invention relates to have through hole processes wafer.Disclose and there is electricity run through composite wiring circuit and the manufacture method thereof of connection.Described composite wiring circuit includes the glass with the first conductive through hole.Described first conductive through hole leads to the bottom surface of described glassy layer from the end face of described glassy layer.Described composite wiring circuit also includes the interposed layer with the second conductive through hole.Described second conductive through hole leads to the bottom surface of described interposed layer from the end face of described interposed layer.Described second conductive through hole is electrically coupled to described first conductive through hole.
Description
Technical field
The present invention relates to integrated circuit carrier, more particularly, to having through hole (through via)
Functional glass process wafer.
Background technology
In the encapsulation of semiconductor chip, typically use organic laminated substrates, this organic laminated substrates
By convex for fine pitch (fine pitch) (typically 0.15 arrives 0.2mm) the C4 solder in silicon die
Play (solder bump) and be shattered into bigger spacing (typically 1.0 arrive 1.2mm) BGA(ball bar battle array
Row) or LGA(connect land grid array, land grid array) connect.For BGA, pass through
Reflux soldered ball to be formed and permanently connected chip packing-body is attached on printed circuit board (PCB), and
LGA type insert (interposer) on a printed circuit board (pcb) can at chip packing-body
The local offer being easily removed and changing connects.The spacing of C4 limits and can be supplied to core
The amount of the input/output signal (i.e. I/O) of sheet.Noting, power output typically needs the phase of C4
When big part.Minimum C4 spacing between chip and its attached package substrate be chip with
The difference of the thermal coefficient of expansion (TCE) between substrate and the function of chip size.If TCE is not
With, then thermal cycle C4 junction between chip and substrate causes stress.Generally also compare high
Large pitch C4 can alleviate bigger strain before the failure.
A kind of method that I/O increasing chip developed recently turns off (I/O off) is to use silicon
Carrier or insert, described silicon carrier or insert be placed between chip and laminated substrates, and
The fine pitch microprotrusion (bump) providing chip connects and large pitch C4 to laminated substrates
Space deformation between connection.Owing to chip and second seals are made up of silicon, therefore owing to not having
TCE difference, it is possible to use fine pitch microprotrusion.
Using and assembling of conventional silicon carrier can include using polymeric layer by silicon wafer bonding to glass
Process wafer (handler wafer).After sawing, silicon carrier is then placed on package substrate
On so that C4 and corresponding pad alignment and be reflowed to form the electrical connection through C4, described
That package substrate is typically organic lamination it may also be multi-layer ceramics.The most typically use laser
Release process (laser release process) removes glass treatment container portion, and described laser discharges
Polymer adhesive between technique ablation/evaporation silicon carrier and glass treatment thing (handler).?
After suitable cleaning and surface process, then use microprotrusion by described (one or more) chip
It is connected to silicon carrier, and underfill (underfill) material is applied to C4 and dimpling aliquation two
Person, and solidify this underfill.Such as to Si carrier before chip is attached with microprotrusion
The alternative assembling sequence carrying out underfill is also possible.
Summary of the invention
Although use silicon carrier to have a lot of significantly advantage, but owing to needs are attached at temporary glass
Reason wafer processes the back side of described carrier with permission, and this manufacturing process is complicated.Additionally, Si carrier is thin
(20-150 micron), and due to the character of crisp fritter of Si carrier and coefficient of thermal expansion mismatch stress,
Big Si carrier is generally not capable of being attached to organic laminated substrates by C4 soldered ball.
Therefore, an illustrative aspects of the present invention is that one has electricity and runs through connection (electrical
Through connection) composite wiring circuit.Described composite wiring circuit includes that having first leads
The glassy layer of electric through-hole.Described first conductive through hole leads to described glassy layer from the end face of described glassy layer
Bottom surface.Described composite wiring circuit also includes the interposed layer (interposer with the second conductive through hole
Layer).Described second conductive through hole leads to the bottom surface of described interposed layer from the end face of described interposed layer.
Described second conductive through hole is electrically coupled to described first conductive through hole.
Accompanying drawing explanation
Claim at the ending of description particularly points out and is distinctly claimed and is considered
It it is subject of the present invention.From the detailed description be given below in conjunction with accompanying drawing, the present invention aforementioned and other
Objects, features and advantages are apparent from, in the accompanying drawings:
Fig. 1 show according to an embodiment of the invention have electricity run through connection composite wiring electricity
Road.
Fig. 2 shows one embodiment of the present of invention, and wherein glassy layer and interposed layer are by the first coupling
Layer and be electrically coupled together.
Fig. 3 shows one embodiment of the present of invention, and wherein composite wiring circuit includes the first redistribution
Wiring layer.
Fig. 4 shows one embodiment of the present of invention, and wherein composite wiring circuit also includes passive electrical equipment
Part.
Fig. 5 shows one embodiment of the present of invention, and wherein composite wiring circuit attachment is to laminated substrates.
Fig. 6 shows the method forming composite wiring circuit according to one embodiment of present invention.
Fig. 7 shows and according to an embodiment of the invention is formed with the second metallic vias (via) on it
Insertion wafer.
Fig. 8 shows the process wafer in the chamber having and etching according to an embodiment of the invention.
Fig. 9 shows according to an embodiment of the invention have the first metallic vias and ball and limit gold
Belong to liner and the process wafer of coupling layer.
Figure 10 exemplifies the process wafer being joined to insert wafer according to an embodiment of the invention.
Figure 11 show according to an embodiment of the invention, be assembled into have and be electrically coupled to microprotrusion
Via process wafer thinning silicon wafer.
Figure 12 shows and is attached with thinning silicon wafer the most after milling
The process wafer of sheet, the second metallic vias wherein exposed is electrically coupled to soldered ball.
Figure 13 shows the composite wiring being attached to package substrate according to an embodiment of the invention
Circuit.
Detailed description of the invention
With reference to embodiments of the invention, the present invention is described.Run through the description of the present invention, with reference to Fig. 1-13.
When mentioning figure, run through the similar structure shown in figure and the similar reference instruction of element.
Fig. 1 show according to an embodiment of the invention have electricity run through connection composite wiring electricity
Road 102.This composite wiring circuit 102 includes glassy layer 104 He with the first conductive through hole 106
There is the interposed layer (interposer layer) 112 of the second conductive through hole 114.In one embodiment,
Use standard silicon wafers to process and manufacture interposed layer 112 from silicon (Si) wafer.Glassy layer 104 is in just conduct
When wafer is processed overleaf, the interposed layer 112 for relative thin provides mechanical support.
Silicon insert comprises through silicon via (thru silicon via, TSV), redistribution wiring, and
It is typically greater than (one or more) chip 128, and to a certain extent less than laminated substrates 126.
TSV 114 and the first redistribution wiring 124 are for the microprotrusion on the end face of composite wiring circuit
Formed between 130 with the C4110 on the bottom surface of composite wiring circuit and electrically connect.Due to silicon BEOL class
Processing procedure and can be used for Si carrier and fine pitch (20-150 micron) microprotrusion spaced design rule,
Silicon carrier or insert can be used for two or more chips being installed on public silicon carrier it
Between greater amount of input and output (I/O) signal are provided, then can be equipped with conventional encapsulating structure.
Some manufacturing process require to cause silicon carrier thin, 20 to 150 microns of thick magnitudes.At TSV
In forming step, generally use deep reactive ion etch (DRIE) to etch aspect ratio and be about 10:1
Or less groove and further feature, and expect the width of the metal filled feature in a dimension
Limit and be about four to eight microns, in order to make stress minimum in process subsequently.
The first conductive through hole 106 in glassy layer 104 leads to the bottom surface of glassy layer from the end face of glassy layer.
In one embodiment, the first conductive through hole 106 terminates at C4 solder bump 110.Such as can lead to
Cross the blasting treatment (grit blasting) combined with masking material and form the first conductive through hole.?
In one embodiment, described through hole is selectively copper filled.
The second conductive through hole 114 in interposed layer 112 leads to the bottom surface of interposed layer from the end face of interposed layer.
Additionally, the second conductive through hole 114 is by the first redistribution wiring being positioned on the end face of Si carrier 112
(RDL) 124 and be electrically coupled to the first conductive through hole 106.First conductive through hole 106 and second
Conductive through hole 114 both of which can be filled by such as copper.Note, when by by glass treatment wafer and silicon
When insertion wafer is joined together and forms composite wiring circuit 102, they are face-to-face or end face is to top
Ground, face engages, and this will explain in Fig. 6-13.Therefore, the end face of composite wiring circuit 102 corresponds to
The bottom of insert, and the bottom of composite wiring circuit 102 is corresponding to the bottom of glass treatment thing.
Composite wiring circuit 102 can also include that such as " OBAR " (resin applied in projection) is brilliant
The Underfill layer 120 of chip level underfill, described Underfill layer 120 is being attached to glass
It is applied to be formed the wafer of insert 112 before layer 104.Underfill layer 120 is positioned at interposed layer
Between 112 and glassy layer 104.With the electric coupling device phase between interposed layer 112 and glassy layer 104
In conjunction with, Underfill layer 120 engages the end face of interposed layer and the end face of glassy layer.
Fig. 2 shows one embodiment of the present of invention, and wherein glassy layer 104 and interposed layer 112 pass through
First coupling layer 122(is also referred herein as solder layer) and be electrically coupled together.In this embodiment,
First coupling layer 122 may be located at the end face of the first conductive through hole 106 and the second conductive through hole 114
Between bottom surface.Noting, various unremarkable metallurgical, bond devices are possible, and although depicted as
Solder, it is not intended that be limited to solder, but can also include intermetallic phase formation, Jin-gold or copper
-copper hot press, Au-Sn alloy bond etc..
In one embodiment of the invention, the first conductive through hole 106 has the first diffusion barrier
(barrier) 202.First diffusion barrier 202 is carried by the end face of the first conductive through hole 106.
Second conductive through hole 114 is connected to by redistribution wiring layer 124 by the first redistribution wiring layer
Second diffusion barrier 204 of the bottom surface carrying of 124.
First diffusion barrier 202 is electrically coupled to the end face of the first conductive through hole 106.First coupling layer
122 end faces being electrically coupled to the first diffusion barrier 202 and the bottom surface of the second diffusion barrier 204.
The bottom surface of the second diffusion barrier 204 is electrically coupled to the also by redistribution wiring layer 124
The bottom surface of two conductive through holes 114.In one embodiment of the invention, the first diffusion barrier 202
Can include that ball limits metal gasket (ball limiting metallurgy with the second diffusion barrier 204
Pad) and be of a material that: described material " is moistened " by solder and is used for reducing or preventing
The metal (metallurgy) of through hole or redistribution wiring layer inserts with for glass treatment wafer and silicon
Less desirable reaction between solder or other material of the electrical connection between thing.
Fig. 3 shows one embodiment of the present of invention, and wherein composite wiring circuit 102 includes first again
Distribution wiring layer 302.First redistribution wiring layer 302 can be carried by the end face of silicon interposed layer 112,
Silicon interposed layer 112 is described as after assembling in the face of glass treatment thing.First redistribution wiring layer 302
Coupling layer 122 is used to be coupled with the second conductive through hole 114 by first conductive through hole 106.?
In one embodiment of the present of invention, composite wiring circuit 102 includes being carried by the bottom surface of interposed layer 112
Second redistribution wiring layer 304, this interposed layer 112 insert wafer and process wafer assembling and
It is positioned at after process on the end face of this composite wiring circuit.
As it is shown on figure 3, the first conductive through hole 106 can have different from the second conductive through hole 114
Spacing.In one embodiment of the invention, the first conductive through hole 106 has the first spacing 306,
And the second conductive through hole 114 has the second spacing 308.First spacing 306 can be more than the second spacing
308.In order to make stress minimum and improve productivity, it is desirable to glass treatment wafer and silicon insert between wafer
Coupling abutment spacing the biggest.This can be by being best accomplished by as follows: makes first to divide again
Cloth wiring layer is positioned on the end face of silicon insert, in order to the spacing of solder joint can increase and
RDL process can occur before thinning on wafer.
Fig. 4 shows one embodiment of the present of invention, and wherein composite wiring circuit 102 also includes passive
Electrical part 402.Passive electrical device 402 is carried by glassy layer 104.Passive electrical device 402 can be electric
Be coupled in conductive through hole 106 or 114 is one or more.In one embodiment, passive electrical equipment
Part 402 is inducer.
One embodiment of the present of invention can include having the compound of multiple first redistribution wiring layer 302
Wired circuit 102.Redistribute in wiring layer 302 the plurality of first, the first redistribution wiring layer
At least one in 302 is electrically coupled at least one in the first conductive through hole 106 and second and leads
At least one in electric through-hole 114.This embodiment can also include dielectric layer 406.Dielectric layer
406 for redistributing each first redistribution wiring layer of electric insulation between wiring layer the plurality of first
302。
One embodiment of the present of invention includes the composite wiring circuit with the second redistribution wiring layer 304
102.Second redistribution wiring layer 304 is electrically coupled to the collection carried by the second redistribution wiring layer 304
Become circuit 408, described second redistribution wiring layer 304 be positioned at this composite wiring circuit end face or
The bottom of interposed layer 112.In one embodiment of the invention, integrated circuit 408 is by second again
It is distributed wiring layer 304 and is electrically coupled at least one in the second conductive through hole 114.
Fig. 5 shows one embodiment of the present of invention, and wherein composite wiring circuit 102 is by laminated substrates
502 carryings.This laminated substrates can be have core or centreless, organic or ceramic, and can
To comprise multiple layer (core and assembling layer (buildup layer)).In one embodiment, compound
Wired circuit 102 can also include the second coupling layer 504.Second coupling layer 504 can be by Compound Fabric
Line circuit 102 and laminated substrates 502 are electrically coupled together.Such as, the second coupling layer 504 is refluxed
To the liner being arranged on substrate 502.In another embodiment, composite wiring circuit 102 also may be used
To include the second Underfill layer 508.Second Underfill layer 508 and the second coupling layer 504 are permissible
Engage composite wiring circuit 102 and laminated substrates 502.
In one embodiment of the invention, composite wiring circuit 102 includes the second redistribution wiring layer
304 and one or more IC chip.Second redistribution wiring layer 304 is electrically coupled to second
At least one in conductive through hole 114 and integrated circuit.Composite wiring circuit 102 can also include
3rd coupling layer 506.Without the second redistribution wiring layer 304, then the 3rd coupling layer 506
It is electrically coupled directly to IC chip and the second conductive through hole 114；Or, if there is second
Redistribution wiring layer 304, then the 3rd coupling layer 506 redistributes wiring layer 304 and quilt by second
It is electrically coupled to IC chip and the second conductive through hole 114.Composite wiring circuit 102 can also wrap
Include for bonded integrated circuit and interposed layer and the 3rd Underfill layer protecting solder joint
510。
In one embodiment of the invention, composite wiring circuit 102 includes the first integrated circuit 512
With the second integrated circuit 514.Integrated circuit 512 and 514 both of which can be carried by interposed layer 112.
The second redistribution wiring layer 304 on interposed layer 112 may be used for electric coupling the first integrated circuit 512
With the second integrated circuit 514.
Fig. 6 shows the method forming composite wiring circuit according to one embodiment of present invention.The party
Method includes etching step 602.During etching step 602, etching inserts wafer (also referred herein as
Silicon wafer) end face to form the second chamber.In one embodiment, the chamber (etched cavity) etched
It it is the blind hole (blind via) not extending across the bottom inserting wafer.DRIE can be used in the phase
Hope in the position of TSV in wafer, etch described chamber.Then wafer is carried out thermal oxide with described
Electric insulation layer is produced on all surface in chamber.After completing etching step 602, the method proceeds to
Forming step 604.
In forming step 604, in the second chamber inserting wafer, form the second metallic vias.Fig. 7 shows
Go out the insertion wafer 702 being formed with the second metallic vias 704 on it.For example, it is possible to it is (logical with metal
Often for tungsten or copper) fill described chamber, and use chemically mechanical polishing to remove cover layer
(overburden), i.e. excess metal in wafer surface between chamber.Use typical silicon wafer
Back-end process (BEOL) processes, and can be formed and is connected to be filled with the chamber of metal and is positioned at filling
Redistribution wiring above the chamber of metal.If so desired, can be at suitable silicon oxide and silicon nitride
Layer is used for protecting being on wafer of copper cash to set up multiple redistribution wiring levels (level).Formed
Final metal layer limited metal (BLM) liner by ball and constitute, micro-solder bump can be attached subsequently
Metal gasket (see figure 3) is limited to this ball.These typically have thin Au layer, in order to provide this
The surface of sample: described surface can be soldered to subsequently by the glass treatment wafer of attachment and by pattern
Change and match with the solder pattern with described glass treatment wafer.After completing forming step 604,
The method proceeds to etching step 606.
At etching step 606, (also referred herein as chip glass or glass treatment is brilliant for etch processes wafer
Sheet) end face to manage in this place, wafer forms the first chamber.Fig. 8 shows have the chamber 804 etched
Process wafer 802.Process wafer can have and silicon starting wafer (～0.75mm is thick) approximation phase
Same thickness, and be circular, there is the nominal diameter identical with silicon wafer laminated thereon.
It will be understood by those skilled in the art that formation via can be simultaneously in inserting wafer and process wafer
Carry out or carry out in a different order.Therefore, order discussed above should not be regarded as limited to institute
The scope of claimed invention.
In one embodiment, the chamber etched is the blind hole not extending across the bottom processing wafer.
There is the multiple possible method of etch-hole in chip glass, described method includes but not limited to: use
The blasting treatment of mask, use mask dry etching, use the wet etching of mask, machine drilling,
Laser drill, laser or UV exposure strengthen glass etching, micro-water jet etching, heat embossing method,
The wet etching of acoustic agitation enhancing or the back side wet etching of induced with laser.
In one embodiment, perform in the case of being used for dry film photoresist limiting region to be etched
Blasting treatment.Using this technique, side wall angle is about 15 degree, and 2:1 or 3:1 aspect ratio hole is
Possible.Such as, the spacing in described hole can be 300-400 micron, and it is micro-that described hole has about 200
The top diameter of rice and the degree of depth of about 500 microns.Described blind hole can be taper, but for
Some other hole manufacture method, sidewall will be vertical or near vertical.Then wet method erosion can be performed
Carve the glass breakage region during step caves in removal, and remove such as low-pressure chemical vapor deposition
(LPVCD) the thin compression layer of silicon nitride, or perform chemical/heat treatments with produce compression layer thus
Reinforce glass.Once completing etching step 606, the method proceeds to forming step 608.
In forming step 608, the first chamber processing wafer forms the first metallic vias with metallization
Process (glass) wafer.This forming step can include depositing such as Ta, Ta (N) by sputtering
Or the code-pattern stop/seed layer of Cu, and then copper facing to fill blind chamber.At this point it is possible to by changing
Learning mechanical polishing (CMP) or use lithography step to remove the copper of excess, the copper of described excess can be by
Wet etching is to form redistribution wiring layer (RDL).The technique substituted can be to sink in stop/seed layer
Long-pending after-applied mask and plating are to fill blind chamber, and concurrently form line alternatively.?
In one embodiment, fill the first metallic vias with copper.Then insulant planarization copper cash is used.
In step 612, limit metal and for the solder engaged at the first metallic vias disposed thereon ball.
Fig. 9 shows have the first metallic vias 902, ball restriction metal level 904 and the solder for joint
The process wafer 802 of layer 906.If there is redistribution wiring layer, open last the most in the passivation layer
Via after, by use block masks or by sputtering seed layer, masking, plating also
And then remove seed layer from field areas, the ball depositing such as Ni/Au limits metal level.If necessary, with
In the solder engaged, the most described solder can be plated after BLM layer, or subsequently by note
Die welding material or other similar techniques are deposited.
Noting, in glass, the size of the spacing in the chamber of depression connects between chip area array and is encapsulated into
In the middle of BGA or LGA of plate connects；Further, functional glass process wafer and silicon carrier wafer it
Between projection, solder joint or other electric joint method, process on wafer not at functional glass
It is identical spacing when there is RDL, or processes existence one or many on wafer at functional glass
Close to identical spacing during individual redistributing layer.If using solder bump or ball between two wafers
The connection of type, then they can be fabricated on arbitrary wafer.In this case, it is assumed that solder is convex
Rise to manufacture and process on wafer at functional glass.
Should be appreciated that as above process wafer and insert the process of wafer can carry out simultaneously or
Carry out in reverse order, without departing from the spirit and scope of the present invention.In optional design variant,
Can use for manufacturing the step of metal filled depression and/or redistribution wiring layer on a glass substrate
In the passive electrical device building the such as inducer being difficult to integrate in silicon wafer.Once complete step
612, the method proceeds to engagement step 614.
In engagement step 614, the first metallic vias is electrically coupled to the second via.First metallic vias
Electric coupling with the second metallic vias includes the first metallic vias being electrically connected by the first redistribution wiring layer
Receive the second metallic vias.This step can also include being joined to process wafer insert wafer.Figure 10
Exemplify the process wafer 802 being joined to insert wafer 702.Noting, they Face to face or push up
In the face of end face ground engages.
Before the two wafer is bonded together, can apply to the wafer with projection
" OBAR " (resin applied in projection) wafer level underfill material.It is then aligned with wafer, with
Just protruding, solder joint or other electric engagement device are comprising the functional glass of metal filled depression
Glass process wafer end face with on the end face of silicon carrier/insertion wafer comprising metal filled depression
It is directed between coupling BLM liner, and applies heat and pressure to form electrical connection between which also
And solidification OBAR material.Noting, this is the crystalline substance in the case of through thickness silicon carrier to chip glass
Sheet is to wafer bonding process, and wherein blind hole or metal filled depression are towards the structure on the two wafer
Center.
After completing engagement step 614, the end face inserting wafer is connect with the end face processing wafer
Close to form composite wiring wafer.Then the method proceeds to grinding steps 616.
At grinding steps 616, the end face of composite wiring wafer is ground so that the second metallic vias exists
Expose at the end face of this composite wiring wafer.This step can include grind/polishing silicon wafer the back side with
The depression that exposing metal is filled.RIE can be used to expose will become TSV's with the combination of polishing
Metal filled chamber.After planarization, using selectivity dry etching to make silicon dent, deposition is absolutely
Velum, and then use chemically mechanical polishing to carry out the end face removal insulator from TVS.Additionally, can
To form BLM microprotrusion joint liner on the back side at the thinning silicon wafer being directed at TSV.
It is possible if desired to used BEOL type technique at thinning silicon before building BLM liner
Other redistributing layer is formed on the back side of wafer.Figure 11 shows thinning silicon wafer 702, its tool
There is the via 704 being electrically coupled to microprotrusion BLM liner 1102.In this point, can be at BLM
The protective layer of the optional such as polyimides of deposition on liner, to protect it during process subsequently
?.After completing grinding steps 616, the method proceeds to grinding steps 618.
At grinding steps 618, process wafer and be ground so that the first metallic vias is processing wafer
Expose at bottom surface.Process the bottom surface corresponding to composite wiring wafer, the bottom surface of wafer.This step can be wrapped
The depression that the back side of spotting-in mill and/or polished glass wafer is filled with exposing metal, and then deposit
BLM is metal laminated and solder bump is for being joined to package substrate.Figure 12 shows in grinding
After process wafer 802, the first metallic vias 902 wherein exposed is electrically coupled to soldered ball 1202.
After completing grinding steps 618, the method proceeds to slicing step 620.
At slicing step 620, composite wiring wafer is sliced to form at least one composite wiring circuit.
Described composite wiring circuit includes processing layer and interposed layer.
After completing slicing step 620, the method proceeds to be attached step 622.It follows that
In step 622, composite wiring circuit it is directed at package substrate and places on the package substrate, making
Obtain corresponding projection or soldered ball and correct pad alignment, and be then reflowed to form electrical connection.
Figure 13 is shown attached to the composite wiring circuit 1302 in package substrate 1304.Complete attachment step
After rapid 622, the method proceeds to coupling step 624.Then wired circuit 1302 is carried out bottom
Fill, and then remove any protective layer on silicon carrier, process it in suitable cleaning and surface
After, (one or more) chip is directed at, places, refluxes and underfill.
At coupling step 624, the integrated circuit of attachment is electrically coupled to composite wiring circuit.As above institute
Stating, integrated circuit and composite wiring circuit can be by the second redistribution wiring layer electric coupling.At Fig. 1
In the structure that shown.
By with comprise conductive through hole chip glass replace temporary glass process wafer, compound glass and
The final thickness of Si carrier and hardness (stiffness) can increase.Additionally, solder bump spacing or arrive
The height of laminated substrates can increase.This reduce stress, and the metal of thickness can be used to come at glass
Glass manufactures inducer.
The description of degree of giving various embodiments of the present invention the most for illustrative purposes, but described
Describe and be not intended as exhaustive or be limited to the disclosed embodiments.Without departing from described embodiment
Scope and spirit in the case of, for those of ordinary skills, a lot of amendments and modification
It is apparent from.Term used herein is selected as most preferably explaining the principle of embodiment, reality
Trample application or the technological improvement compared to the technology found on market, or make ordinary skill
Personnel are it will be appreciated that embodiment disclosed herein.
Claims (13)
1. having electricity and run through a composite wiring circuit for connection, described composite wiring circuit includes:
Having the glassy layer of the first conductive through hole, described first conductive through hole is from the end face of described glassy layer
Lead to the bottom surface of described glassy layer；
Having the interposed layer of the second conductive through hole, described second conductive through hole is from the end face of described interposed layer
Leading to the bottom surface of described interposed layer, wherein, described second conductive through hole is electrically coupled to described first and leads
Electric through-hole；And
First coupling layer, the end face of the first conductive through hole described in wherein said first coupling layer electric coupling with
The bottom surface of described second conductive through hole,
Wherein, described first conductive through hole includes first carried by the end face of described first conductive through hole
Diffusion barrier, described first diffusion barrier is electrically coupled to the end face of described first conductive through hole,
And described first coupling layer is electrically coupled to the end face of described first diffusion barrier；
Wherein, described second conductive through hole includes second carried by the bottom surface of described second conductive through hole
Diffusion barrier, described first coupling layer is electrically coupled to the bottom surface of described second diffusion barrier, and
And the bottom surface of described second diffusion barrier is electrically coupled to the bottom surface of described second conductive through hole；And
Wherein, described first diffusion barrier and described second diffusion barrier include that ball limits metal liner
Pad.
Composite wiring circuit the most according to claim 1, also includes: the first redistribution wiring layer,
It is carried by the end face of the described interposed layer in the face of described glassy layer, described first redistribution wiring layer electricity
Couple described first conductive through hole and described second conductive through hole.
Composite wiring circuit the most according to claim 1, also includes: multiple first redistribution cloth
Line layer, wherein, at least one in described first redistribution wiring layer is electrically coupled to described first and leads
At least one at least one and described second conductive through hole in electric through-hole.
Composite wiring circuit the most according to claim 3, also includes: dielectric layer, described electricity
Dielectric layer is by each first redistribution wiring layer electric insulation.
Composite wiring circuit the most according to claim 1, also includes: the second redistribution wiring layer,
It is by the bottom surface carrying of the described interposed layer deviating from described glassy layer, described second redistribution wiring layer quilt
It is electrically coupled to the integrated circuit carried by the end face of described interposed layer.
Composite wiring circuit the most according to claim 5, wherein, described integrated circuit is by thermocouple
Close at least one in described second conductive through hole.
Composite wiring circuit the most according to claim 1, also includes: the first Underfill layer,
Described first Underfill layer composition surface is to the end face of the described interposed layer of described glassy layer and described glass
The end face of layer.
Composite wiring circuit the most according to claim 1, also includes: laminated substrates, Qi Zhongsuo
State composite wiring circuit to be carried by described laminated substrates.
Composite wiring circuit the most according to claim 8, also includes: the second coupling layer, described
Composite wiring circuit described in second coupling layer electric coupling and described laminated substrates.
Composite wiring circuit the most according to claim 8, also includes: the second Underfill layer,
Described second Underfill layer engages described composite wiring circuit and described laminated substrates.
11. composite wiring circuit according to claim 1, also include:
The first integrated circuit carried by described interposed layer；And
The second integrated circuit carried by described interposed layer, wherein, described in described interposed layer electric coupling
One integrated circuit and described second integrated circuit.
12. composite wiring circuit according to claim 1, also include: held by described glassy layer
The passive electrical device carried, described passive electrical device is electrically coupled at least one conductive through hole.
13. composite wiring circuit according to claim 12, wherein, described passive electrical device bag
Include inducer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/623,873 US9059161B2 (en) | 2012-09-20 | 2012-09-20 | Composite wiring board with electrical through connections |
| US13/623,873 | 2012-09-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103681618A CN103681618A (en) | 2014-03-26 |
| CN103681618B true CN103681618B (en) | 2016-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310428799.XA Expired - Fee Related CN103681618B (en) | 2012-09-20 | 2013-09-18 | The functional glass with through hole processes wafer |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9059161B2 (en) |
| CN (1) | CN103681618B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9312219B2 (en) * | 2012-12-28 | 2016-04-12 | Dyi-chung Hu | Interposer and packaging substrate having the interposer |
| US20140339706A1 (en) * | 2013-05-17 | 2014-11-20 | Nvidia Corporation | Integrated circuit package with an interposer formed from a reusable carrier substrate |
| US20140339705A1 (en) * | 2013-05-17 | 2014-11-20 | Nvidia Corporation | Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon vias |
| US20230005834A1 (en) * | 2014-08-18 | 2023-01-05 | Samtec, Inc. | Electrically conductive vias and methods for producing same |
| US9514093B2 (en) | 2014-09-26 | 2016-12-06 | Intel Corporation | Method and apparatus for stacking core and uncore dies having landing slots |
| WO2016161434A1 (en) | 2015-04-02 | 2016-10-06 | Nanopac Technologies, Inc. | Method for creating through-connected vias and conductors on a substrate |
| US10593562B2 (en) | 2015-04-02 | 2020-03-17 | Samtec, Inc. | Method for creating through-connected vias and conductors on a substrate |
| WO2017109537A1 (en) * | 2015-12-21 | 2017-06-29 | Intel IP Corporation | An electrical device and a method for forming an electrical device |
| US10790232B2 (en) * | 2018-09-15 | 2020-09-29 | International Business Machines Corporation | Controlling warp in semiconductor laminated substrates with conductive material layout and orientation |
| US11195789B2 (en) | 2018-11-30 | 2021-12-07 | International Business Machines Corporation | Integrated circuit module with a structurally balanced package using a bottom side interposer |
| CN111753478B (en) * | 2020-07-01 | 2022-02-18 | 无锡中微亿芯有限公司 | Multi-die FPGA (field programmable gate array) for realizing built-in analog circuit by utilizing active silicon connection layer |
| US11817359B2 (en) * | 2020-09-01 | 2023-11-14 | International Business Machines Corporation | Warp mitigation using pattern-matched metal layers in organic substrates |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1678175A (en) * | 2004-03-31 | 2005-10-05 | 阿尔卑斯电气株式会社 | Circuit component module and method of manufacturing the same |
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| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| US5807783A (en) | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
| US7312487B2 (en) | 2004-08-16 | 2007-12-25 | International Business Machines Corporation | Three dimensional integrated circuit |
| US7258010B2 (en) | 2005-03-09 | 2007-08-21 | Honeywell International Inc. | MEMS device with thinned comb fingers |
| US7576435B2 (en) * | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
| US20080284037A1 (en) * | 2007-05-15 | 2008-11-20 | Andry Paul S | Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers |
| US20100084752A1 (en) | 2008-10-08 | 2010-04-08 | Honeywell International Inc. | Systems and methods for implementing a wafer level hermetic interface chip |
| US8115292B2 (en) * | 2008-10-23 | 2012-02-14 | United Test And Assembly Center Ltd. | Interposer for semiconductor package |
| US8295056B2 (en) | 2009-07-22 | 2012-10-23 | International Business Machines Corporation | Silicon carrier structure and method of forming same |
| US8048794B2 (en) | 2009-08-18 | 2011-11-01 | International Business Machines Corporation | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
| US8411459B2 (en) * | 2010-06-10 | 2013-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd | Interposer-on-glass package structures |
-
2012
- 2012-09-20 US US13/623,873 patent/US9059161B2/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1678175A (en) * | 2004-03-31 | 2005-10-05 | 阿尔卑斯电气株式会社 | Circuit component module and method of manufacturing the same |
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| Publication number | Publication date |
|---|---|
| US20140078704A1 (en) | 2014-03-20 |
| CN103681618A (en) | 2014-03-26 |
| US9059161B2 (en) | 2015-06-16 |
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Effective date of registration: 20171030 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171030 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
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