CN103681583A - One-time eroding-before-plating metal frame subtraction embedded chip normally-arranged flat foot structure and technological method - Google Patents
One-time eroding-before-plating metal frame subtraction embedded chip normally-arranged flat foot structure and technological method Download PDFInfo
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- CN103681583A CN103681583A CN201310645357.0A CN201310645357A CN103681583A CN 103681583 A CN103681583 A CN 103681583A CN 201310645357 A CN201310645357 A CN 201310645357A CN 103681583 A CN103681583 A CN 103681583A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
The invention relates to a one-time eroding-before-plating metal frame subtraction embedded chip normally-arranged flat foot structure and a technological method. The one-time eroding-before-plating metal frame subtraction embedded chip normally-arranged flat foot structure is characterized in that a metal substrate frame is included, a paddle and pins are arranged in the metal substrate frame, the front face of the paddle and the front faces of the pins are aligned with the front face of the metal substrate frame, the back faces of the pins are aligned with the back face of the metal substrate frame, the back face of the paddle is aligned with the step faces of the pins, metal layers are arranged on the step faces of the pins, a chip is arranged on the back face of the paddle through conducting or non-conducting adhesion substances, the front face of the chip is connected with the surfaces of the metal layers on the step faces of the pins through metal wires, plastic packaging materials wrap the paddle, the pins, the chip and the metal wires, the plastic packaging materials are aligned with the upper surface and the lower surface of the metal substrate frame, and anti oxidation layers are plated on or organic solderability preservative (OSP) wraps the front face of the paddle, the front faces and the back faces of the pins and the surface of the metal substrate frame. The one-time eroding-before-plating metal frame subtraction embedded chip normally-arranged flat foot structure has the advantages of being capable of solving the problem that the function and the application of a metal wire frame are restricted due to the fact that objects cannot be buried in the thickness of the traditional metal wire frame.
Description
Technical field
After the present invention relates to a kind of once first erosion, plating frame subtraction buries the flat leg structure of chip formal dress and process.Belong to semiconductor packaging field.
Background technology
Traditional flat-four-side mainly contains two kinds without pin metal leadframe structure:
Be flat-four-side without pin package (QFN) lead frame, the lead frame of this structure forms (as shown in figure 15) by copper material metal framework and high temperature resistant glued membrane.
Be to seal in advance flat-four-side without pin package (pQFN) lead frame, the lead frame structure of this structure comprises pin Yu Ji island, and the etching area between pin Yu Ji island is filled with plastic packaging material (as shown in figure 16).
There is following shortcoming in above-mentioned traditional metal lead frame:
1, traditional metal lead frame is as the package carrier that loads chip, and itself does not possess systemic-function, thereby has limited integrated functionality and application performance after traditional metal leadframe package;
2,, because traditional metal lead frame itself does not possess systemic-function, can only carry out in lead frame front tiling or the stacked package of chip and assembly.And power device and control chip are encapsulated in same packaging body, the heat radiation of power device can affect the transmission of control chip signal;
3, because traditional metal lead frame itself does not possess systemic-function, so multifunction system integration module can only be in traditional metal lead frame front by tiling or stacking realization of multi-chip and assembly, correspondingly also just increase component module shared space on PCB.
summary of the invention
The object of the invention is to overcome above-mentioned deficiency, provide the rear plating frame subtraction of a kind of once first erosion to bury the flat leg structure of chip formal dress and process, it can solve the problem that traditional metal lead frame lacks systemic-function.
The object of the present invention is achieved like this: the process that after a kind of once first erosion, plating frame subtraction buries the flat leg structure of chip formal dress, described method comprises the steps:
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at metal substrate;
The metallic substrate surfaces of utilizing exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film;
In step 3, in the region of metallic substrate surfaces removal part photoresistance film, carry out chemical etching;
Remove the photoresistance film of metallic substrate surfaces;
Step 6, the operation of subsides photoresistance film
On the surface label of metal substrate, can carry out the photoresistance film of exposure imaging;
Part photoresistance film is removed at step 7, the metal substrate back side
Graph exposure is carried out, develops and removes part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side in the metal substrate back side that utilizes exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film;
At the metal substrate back side of step 7, carry out the plating work of metallic circuit layer, metallic circuit layer forms corresponding Ji Dao and pin on metal substrate according to figure after having electroplated;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, load
Positive by conduction or non-conductive bonding material implantation chip on step 8 Ji island;
Step 11, metal wire bonding
Between chip front side and pin metal-plated aspect, carry out the operation of bonding metal wire;
Step 12, seal
The inner plastic packaging material that adopts of the metal substrate of step 11 is carried out to plastic packaging, and plastic packaging material all flushes with the front and back of metal substrate;
Step 13, plating anti-oxidant metal layer or coating antioxidant (OSP)
The exposed metal of metallic substrate surfaces after completing steps 12 is electroplated anti-oxidant metal layer or coating antioxidant (OSP).
After a kind of once first erosion, plating frame subtraction buries the flat leg structure of chip formal dress, it comprises Metal Substrate sheet frame, in described Metal Substrate sheet frame inside, be provided with Ji Dao and pin, described pin is step-like, the front of described Ji Dao and pin flushes with Metal Substrate sheet frame front, the back side of described pin flushes with the back side of Metal Substrate sheet frame, the described Ji Dao back side flushes with the step surface of pin, on the step surface of described pin, be provided with metal level, the back side of described Ji Dao is provided with chip by conduction or non-conductive bonding material, between the front of described chip and layer on surface of metal on the step surface of pin, with metal wire, be connected, the region of periphery, described base island, region between Ji Dao and pin, region between pin and pin, the region on Ji Dao and pin top, the region of Ji Dao and pin bottom and chip and metal wire are all encapsulated with plastic packaging material outward, described plastic packaging material flushes with the upper and lower surface of Metal Substrate sheet frame, positive on described base island, the surface of the front and back of pin and Metal Substrate sheet frame is coated with anti oxidation layer or coating antioxidant (OSP).
Described chip Yu Ji island is provided with metal level between the back side.
Compared with prior art, the present invention has following beneficial effect:
1, the interlayer of metal frame subtraction technological frame can be because of the needs of system and function be imbedded active member or assembly or passive assembly in the position of needs or region, becomes a system-level metal lead wire frame of individual layer circuit.
2, from the outward appearance of subtractive metallization technological frame finished product, can't see inner interlayer completely and imbedded imbedding X-ray and all cannot inspecting of the object, especially the silicon material chip that need because of system or function, fully reach confidentiality and the protectiveness of system and function.
3, the interlayer of subtractive metallization technological frame can be imbedded high-power component in manufacturing process, secondary encapsulation carries out the load of control chip again, thereby high-power component and control chip are contained in respectively subtractive metallization lead frame both sides, can avoid high-power component to disturb the signal of control chip because of thermal radiation and transmit.
4, subtractive metallization technological frame itself includes the function of imbedding object, after secondary encapsulation, can fully realize the integrated of systemic-function and integrate, it is little that thereby the volume size of the component module of said function comes than the module of conventional lead frame encapsulation, corresponding space shared on PCB is also just fewer, thereby has also just reduced cost.
5, the interlayer of subtractive metallization technological frame can be because heat conduction or heat radiation need in manufacturing process be imbedded heat conduction or heat radiation object in the position of needs or region, thereby improves the radiating effect of whole encapsulating structure.
6, subtractive metallization technological frame finished product itself has just been rich in various assemblies, if no longer carried out in the situation of follow-up encapsulation for the second time, composite metal lead frame is cut according to each lattice unit, itself just can become a ultra-thin packaging body or compact system level encapsulation body.
7, subtractive metallization technological frame, except itself including imbedding of object can also superpose in packaging body periphery function different unit package or system in package, fully reaches the dual system of individual layer circuit metal lead wire frame or the encapsulation technology ability of polyphyly irrespective of size again.
8, object or the object in subtractive metallization technology lead frame, imbedded all flush with metal frame thickness, embody fully among the ultra-thin and highdensity thickness space being filled in subtractive metallization technology lead frame.
Accompanying drawing explanation
Fig. 1 ~ Figure 13 is that after the present invention once first loses, plating frame subtraction buries each operation schematic diagram of the process of the flat leg structure of chip formal dress.
Figure 14 is the schematic diagram that after the present invention once first loses, plating frame subtraction buries the flat leg structure of chip formal dress.
Figure 15 is that traditional flat-four-side is without the schematic diagram of pin package (QFN) lead frame structure.
Figure 16 is for to seal flat-four-side without the schematic diagram of pin package (pQFN) lead frame structure in advance.
Wherein:
Metal Substrate sheet frame 1
Base island 2
Conduction or non-conductive bonding material 4
Metal wire 6
Anti oxidation layer or coating antioxidant 8
Metal level 9.
Embodiment
The process that the rear plating frame subtraction of a kind of once first erosion of the present invention buries the flat leg structure of chip formal dress is as follows:
Referring to Fig. 1, get the metal substrate that a slice thickness is suitable, the material of this sheet material is mainly to take metal material as main, and the metallics of the material of metal material can be the zinc-plated Cai ﹑ of Tong Cai ﹑ Tie Cai ﹑ Bu rust Gang Cai ﹑ aluminium maybe can reach conducting function or non-all-metal material etc., and the selection of thickness can be selected according to product performance.
Referring to Fig. 2, at front and the back side of metal substrate, stick respectively the photoresistance film that can carry out exposure imaging, to protect follow-up etch process operation, photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Referring to Fig. 3, the metallic substrate surfaces (front and back) of utilizing exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film, and to expose, metallic substrate surfaces is follow-up need to carry out etched regional graphics.
Referring to Fig. 4, in step 3, in the region of metallic substrate surfaces removal part photoresistance film, carry out chemical etching, etching solution or technology can adopt copper chloride or iron chloride or liquid medicine or the technology that can carry out metal material chemical etching.
Referring to Fig. 5, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove photoresistance film.
Step 6, the operation of subsides photoresistance film
Referring to Fig. 6, on the surface label of metal substrate, can carry out the photoresistance film of exposure imaging, to protect follow-up electroplating technology operation, photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 7, the metal substrate back side
Referring to Fig. 7, graph exposure is carried out, develops and removes part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side in the metal substrate back side that utilizes exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film.
Referring to Fig. 8, at the metal substrate back side of step 7, carry out the plating work of metallic circuit layer, metallic circuit layer forms corresponding Ji Dao and pin on metal substrate after having electroplated, the material of metallic circuit layer can be copper, nickel gold, NiPdAu, silver or golden etc., and plating mode can be that pure metallide mode or chemical deposition add metallide or all use chemical deposition mode to plate out the thickness of needs.
Step 9, removal photoresistance film
Referring to Fig. 9, remove the photoresistance film of metallic substrate surfaces, the method for removing photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove photoresistance film.
Step 10, load
Referring to Figure 10, positive by conduction or non-conductive bonding material implantation chip on step 8 Ji island, implanting the mode of chip can select flexibly according to product performance, can adopt the positive millet cake mucilage binding of Ji Dao sheet, chip back covering glue layer or DAF(Die Attach Film) mode of film carries out load
Step 11, metal wire bonding
Referring to Figure 11, between chip front side and pin metal-plated aspect, carry out the operation of bonding metal wire, the material of described metal wire adopts gold, silver, copper, aluminium or the material of alloy, shape wiry can be thread can be also banded.
Step 12, seal
Referring to Figure 12, the inner plastic packaging material that adopts of the metal substrate of step 11 is carried out to plastic packaging, plastic packaging material all flushes with the front and back of metal substrate, plastic packaging mode can adopt mould encapsulating mode, spraying method, brush coating mode or pad pasting mode, and described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Step 13, plating anti-oxidant metal layer or coating antioxidant (OSP)
Referring to Figure 13, the exposed metal of metallic substrate surfaces after completing steps 12 is electroplated anti-oxidant metal layer, prevents burning, as gold, golden, the NiPdAu of nickel, tin or coating antioxidant (OSP).
Referring to Figure 14, for plating frame subtraction after a kind of once first erosion of the present invention buries the structural representation of the flat leg structure of chip formal dress, it comprises Metal Substrate sheet frame 1, in described Metal Substrate sheet frame 1 inside, be provided with base island 2 and pin 3, described pin 3 is step-like, the front of described base island 2 and pin 3 flushes with Metal Substrate sheet frame 1 front, the back side of described pin 3 flushes with the back side of Metal Substrate sheet frame 1, 2 back sides, described base island flush with the step surface of pin 3, on the step surface on described pin 3 He Ji islands 2, be provided with metal level 9, the back side on described base island 2 is provided with chip 5 by conduction or non-conductive bonding material 4, on the step surface on the front of described chip 5 and pin 3 He Ji islands 2, between metal level 9 surfaces, with metal wire 6, be connected, the region of 2 peripheries, described base island, region between base island 2 and pin 3, region between pin 3 and pin 3, the region on base island 2 and pin 3 tops, the outer plastic packaging material 7 that is all encapsulated with of the region of base island 2 and pin 3 bottoms and chip 5 and metal wire 6, described plastic packaging material 7 flushes with the upper and lower surface of Metal Substrate sheet frame 1, in 2 fronts, described base island, the surface of the front and back of pin 3 and Metal Substrate sheet frame 1 is coated with anti oxidation layer or coating antioxidant (OSP).
Claims (3)
1. the process that once the rear plating frame subtraction of first erosion buries the flat leg structure of chip formal dress, described method comprises the steps:
Step 1, get metal substrate
Step 2, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked respectively at front and the back side at metal substrate;
Step 3, metallic substrate surfaces are removed part photoresistance film
The metallic substrate surfaces of utilizing exposure imaging equipment that step 2 is completed to the operation of subsides photoresistance film is carried out graph exposure, develops and removes part figure photoresistance film;
Step 4, chemical etching
In step 3, in the region of metallic substrate surfaces removal part photoresistance film, carry out chemical etching;
Step 5, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 6, the operation of subsides photoresistance film
On the surface label of metal substrate, can carry out the photoresistance film of exposure imaging;
Part photoresistance film is removed at step 7, the metal substrate back side
Graph exposure is carried out, develops and removes part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side in the metal substrate back side that utilizes exposure imaging equipment that step 6 is completed to the operation of subsides photoresistance film;
Step 8, plated metal line layer
At the metal substrate back side of step 7, carry out the plating work of metallic circuit layer, metallic circuit layer forms corresponding Ji Dao and pin on metal substrate according to figure after having electroplated;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, load
Positive by conduction or non-conductive bonding material implantation chip on step 8 Ji island;
Step 11, metal wire bonding
Between chip front side and the pin back side, carry out the operation of bonding metal wire;
Step 12, seal
The inner plastic packaging material that adopts of the metal substrate of step 11 is carried out to plastic packaging, and plastic packaging material all flushes with the front and back of metal substrate;
Step 13, plating anti-oxidant metal layer or coating antioxidant (OSP)
The exposed metal of metallic substrate surfaces after completing steps 12 is electroplated anti-oxidant metal layer (OSP).
2. by plating frame subtraction after the prepared a kind of once first erosion of claim 1, bury the flat leg structure of chip formal dress, it is characterized in that it comprises Metal Substrate sheet frame (1), in described Metal Substrate sheet frame (1) inside, be provided with Ji Dao (2) and pin (3), described pin (3) is step-like, the front of described Ji Dao (2) and pin (3) flushes with Metal Substrate sheet frame (1) front, the back side of described pin 3 flushes with the back side of Metal Substrate sheet frame (1), described Ji Dao (2) back side flushes with the step surface of pin (3), on the step surface of described pin (3), be provided with metal level (9), the back side of described Ji Dao (2) is provided with chip (5) by conduction or non-conductive bonding material (4), between the front of described chip (5) and metal level 9 surfaces on the step surface of pin (3), with metal wire (6), be connected, the region that described Ji Dao (2) is peripheral, region between Ji Dao (2) and pin (3), region between pin (3) and pin (3), the region on Ji Dao (2) and pin (3) top, the outer plastic packaging material (7) that is all encapsulated with of the region of Ji Dao (2) and pin (3) bottom and chip (5) and metal wire (6), described plastic packaging material (7) flushes with the upper and lower surface of Metal Substrate sheet frame (1), in described Ji Dao (2) front, the surface of the front and back of pin (3) and Metal Substrate sheet frame (1) is coated with anti oxidation layer or coating antioxidant (OSP) (8).
3. after once first erosion according to claim 2, plating frame subtraction buries the flat leg structure of chip formal dress, it is characterized in that: described chip (5) Yu Ji island (2) is provided with metal level (9) between the back side.
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