CN103681500B - A kind of manufacture method of semiconductor device - Google Patents
A kind of manufacture method of semiconductor device Download PDFInfo
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- CN103681500B CN103681500B CN201210337269.XA CN201210337269A CN103681500B CN 103681500 B CN103681500 B CN 103681500B CN 201210337269 A CN201210337269 A CN 201210337269A CN 103681500 B CN103681500 B CN 103681500B
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- 238000000034 method Methods 0.000 title claims abstract description 144
- 239000004065 semiconductor Substances 0.000 title claims abstract description 110
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 185
- 238000005530 etching Methods 0.000 claims abstract description 39
- 238000005516 engineering process Methods 0.000 claims abstract description 37
- 238000012545 processing Methods 0.000 claims abstract description 31
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 28
- 230000008569 process Effects 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 55
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 47
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 238000001039 wet etching Methods 0.000 claims description 25
- 238000000059 patterning Methods 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 25
- 238000005303 weighing Methods 0.000 abstract description 9
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract 2
- 229910003978 SiClx Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 170
- 238000009826 distribution Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000012528 membrane Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a kind of manufacture method of semiconductor device, relate to technical field of semiconductors.The method comprises: after germanium silicon layer formation process, carries out etching processing to the germanium silicon shielding layer of nmos area and the hard mask of dummy grid, makes the step that germanium silicon shielding layer and the hard mask of dummy grid reach unanimity at the thickness of NMOS area and PMOS area.The invention solves and remove the uneven thickness weighing apparatus problem in NMOS area and PMOS area of germanium silicon shielding layer and the hard mask of dummy grid before technique, the removal of germanium silicon shielding layer and the hard mask of dummy grid can be realized when not needing very large carving technology amount excessively, the hard mask of dummy grid avoiding NMOS remains, side wall layer remains and the hard mask defect of dummy grid in PMOS district, dummy grid defect and AA district defect etc. are bad, avoid the abnormal nickel SiClx growth of dummy grid shoulder that dummy grid defect causes, improve performance and the yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor device.
Background technology
In technical field of semiconductors, for the polysilicon/silicon oxynitride technology of the advanced person below 45nm node, stress engineering becomes one of most important factor of device performance lifting.For PMOS, germanium silicon technology can improve carrier mobility by applying compression to raceway groove.Due to germanium siliceous deposits to the impurity of groove surfaces and oxide very responsive, therefore, usually total technique amount of the wet-etching techniques such as photoresist lift off, TMAH wet etching (be generally used for and improve groove shapes) and the prerinse of germanium silicon technology is arranged very large to reduce impurity and oxidation.In the prior art, because aforesaid wet-etching technique all can etching oxidation silicon, therefore germanium silicon shielding layer generally adopt silicon nitride (SiN) or with silicon nitride at the silica above for bulk composition+silicon nitride bilayer film, but not pure silica.In order to stop the improper depositional phenomenon of germanium silicon on PMOS top after wet etching, silicon nitride film is also often used as the hard mask of grid (or dummy grid).In prior art, generally by form the groove (can be sigma type or U-shaped etc.) of the PMOS for making germanium silicon dry quarter in conjunction with the mode of wet etching.Carve in the process forming groove dry; the germanium silicon shielding layer (also as the interim side wall of PMOS) in PMOS district can be etched away a part simultaneously; the germanium silicon shielding layer of nmos area then can not be etched due to the protection of photoresist, and this just causes germanium silicon shielding layer and weighs at the uneven thickness in nmos area and PMOS district.For the manufacture of semiconductor of application high-k/metal gate technology, germanium silicon shielding layer (interim side wall) the uneven thickness weighing apparatus phenomenon in above-mentioned nmos area and PMOS district will become affects the removal of germanium silicon shielding layer and stress closes on technology (StressProximityTechnique; Be called for short SPT) or interlayer dielectric layer (InterLayerDielectric; Be called for short ILD) chemico-mechanical polishing (ChemicalMechanicalPolishing; Be called for short CMP) etc. the significant problem of subsequent technique.
For high-k/metal gate technology, in nickle silicide (NiSi) deposition process, hard mask protection must be arranged at the top of polysilicon (dummy grid), otherwise metal silicide (nickle silicide) can be formed on the top of polysilicon.And remove in technique at dummy grid and cannot remove metal silicide, this just causes the residual of metal silicide, and then causes metal gate cannot normally be formed (groove that metal cannot stay after deposition growing to former dummy grid removal).
If germanium silicon shielding layer is removed immediately after germanium silicon layer is formed, so crossing carving technology amount (overetchamount) needs well to be controlled.If cross carving technology amount very little, the residual of the interim side wall (i.e. germanium silicon shielding layer) of nmos area can be caused, will directly affect the techniques such as follow-up side wall formation.If it is excessive to cross carving technology amount, then can damage the hard mask of the dummy grid of PMOS, dummy grid top flank, side wall, even AA district.After the prerinse of metal silicide formation process; the destroyed hard mask of dummy grid, dummy grid top flank and side wall cannot protect dummy grid top flank in nickle silicide (NiSi) deposition process, and then cause the metallization of dummy grid (polysilicon).
If germanium silicon shielding layer is carried over into by the part as side wall the processing step that stress closes on technology (SPT), the uneven thickness weighing apparatus problem of side wall still exists, cross the too small of carving technology amount or the excessive hard mask of the dummy grid of NMOS and/or the side wall of still causing remains, or, the destruction of dummy grid top flank.If the hard mask of the dummy grid that there is NMOS remains, undertaken more crossing polishing by needing in follow-up ILDCMP technique, and then the height of the metal gates of actual formation can be caused to reduce.If dummy grid top flank is destroyed, after the prerinse of metal silicide formation process, destroyed side wall cannot protect dummy grid (polysilicon), and then cause the metallization (silicidation) of polysilicon.If the polysilicon of PMOS is destroyed in SPT technique, metal gates will be caused to form rear metal gates and to be destroyed.Therefore, wet-etching technique is spent quarter and measured is a very important problem.And, the problem that side wall layer (comprising skew sidewall, interim side wall, master wall etc.) causes in NMOS area and PMOS area variable thickness, also cause harmful effect when forming source-drain electrode subsequently through ion implantation to the consistency of NMOS and PMOS, affecting the performance of device.
Below for a kind of manufacture method of traditional semiconductor device, introduce the above-mentioned problems in the prior art further.The manufacture method of semiconductor device of the prior art, generally comprises following steps:
Step 1: Semiconductor substrate 100 is provided, and form shallow trench isolation on a semiconductor substrate 100 from (STI) 101, the dummy grid 102A being positioned at nmos area, dummy grid hard mask 103A and skew sidewall 104A, the dummy grid 102B being positioned at PMOS district, the hard mask 103B of dummy grid and skew sidewall 104B, as shown in Figure 1A.Wherein, the material of hard mask 103A and 103B of dummy grid is silicon nitride.Dummy grid 102A and 102B is generally polysilicon or amorphous silicon material, is only the position temporarily occupying grid in the processing procedure of semiconductor device, can be removed in subsequent technique, and substitute by the real metal gates as grid.
Step 2: form germanium silicon shielding layer 105 on a semiconductor substrate 100, this germanium silicon shielding layer 105 comprises part (i.e. the germanium silicon shielding layer of the nmos area) 105A being positioned at NMOS area and part (i.e. the germanium silicon shielding layer in the PMOS district) 105B being positioned at PMOS area, as shown in Figure 1B.Wherein, the material of germanium silicon shielding layer 105 can be silicon nitride or silica+silicon nitride (silicon nitride above, and thicker, be material of main part, silica is mainly used in the protection offset side wall when removing all germanium silicon shielding layers and is not removed).
Wherein, between step 1 and step 2, generally can also comprise the processing step carrying out light dope (LDD).
Step 3: the photoresist 600A forming a pattern layers above the germanium silicon shielding layer 105A of nmos area, dry quarter is carried out to described Semiconductor substrate 100, the Semiconductor substrate 100 of the dummy grid 102B both sides of PMOS forms the groove 106 being used for deposit Germanium silicon, as shown in Figure 1 C.
In the process at dry quarter, the hard mask 103B of dummy grid in PMOS district is etched away a part, defines the hard mask 103B ' of the dummy grid after etching; The germanium silicon shielding layer 105B in PMOS district is etched away a part simultaneously, defines interim side wall layer 105B ', as shown in Figure 1 C in the both sides of the dummy grid 102B of PMOS.Now, there is difference in the thickness of the part 105A of germanium silicon shielding layer in NMOS area and the part 105B ' in PMOS area (i.e. interim side wall 105B '), difference has also appearred in the thickness of the dummy grid hard mask 103A of nmos area and the hard mask 103B ' of dummy grid in PMOS district.That is, germanium silicon shielding layer and the hard mask of dummy grid occur unbalanced in the distribution of NMOS and PMOS area.
Step 4: carry out wet etching to form the groove 106 ' of Sigma type, the depositing operation then carrying out germanium silicon forms germanium silicon layer 107 in groove 105 ', as shown in figure ip.Wherein, in the process of carrying out wet etching (generally adopting TMAH), interim side wall 105B ' and the hard mask 103B ' of PMOS are all further etched, and define the interim side wall 104B after etching further " and hard mask 103B ", as shown in figure ip.
Now, the part 105A of germanium silicon shielding layer in NMOS area and the part 105B in PMOS area " difference in thickness aggravate further; the dummy grid hard mask 103A of nmos area and the hard mask 103A of dummy grid in PMOS district " difference in thickness also aggravate further, as shown in figure ip.That is, germanium silicon shielding layer and the hard mask of dummy grid aggravate further at the uneven thickness weighing apparatus of NMOS and PMOS area.
After completing step 4, about the removal of germanium silicon shielding layer, prior art has two kinds of different schemes usually.Be respectively: scheme one, removal germanium silicon shielding layer immediately after formation germanium silicon layer (i.e. step 4); Scheme two, germanium silicon shielding layer are retained a part (interim side wall) as sidewall until be removed in follow-up SPT technique.Particularly, in scheme one, after completing steps 4, follow-up step generally comprises successively: step 5-1, removal germanium silicon shielding layer; Step 6-1, formation side wall (or claiming master wall); Step 7-1, formation source-drain electrode; Step 8-1, metallization process and stress close on technology (SPT); Step 9-1, formation ILD and metal gates; Step 10-1, formation contact hole and metal level.In scheme two, after completing steps 4, follow-up step generally comprises successively: step 5-2, formation side wall (or claiming master wall); Step 6-2, formation source-drain electrode; Step 7-2, Metalized gate formation process; Step 8-2, stress close on the part germanium silicon shielding layer that technology (SPT) removes final residual simultaneously; Step 9-2, formation ILD and metal gates; Step 10-2, formation contact hole and metal level.
Due to after completing step 4, germanium silicon shielding layer and the hard mask of dummy grid unbalanced in the thickness distribution in nmos area and PMOS district, therefore, in step 5-1 and step 8-2, when removing germanium silicon shielding layer, all can occur aforesaid because cross carving technology amount excessive or too small and cause bad.Specific as follows:
In scheme one:
Step 5-1 comprises: carry out dry etching to remove the germanium silicon shielding layer 105B in germanium silicon shielding layer 105A, PMOS district of nmos area " (interim side wall), the hard mask of dummy grid 103 of nmos area and the hard mask 103B of dummy grid in PMOS district ".
Thickness due to the germanium silicon shielding layer 105A of nmos area is greater than the germanium silicon shielding layer 105B in PMOS district ", therefore, must carry out quarter (the germanium silicon shielding layer 105B in relative PMOS district ") to remove the germanium silicon shielding layer 105A of nmos area completely.
If it's quarter the pasting technique amount very little, then can cause the residual 1051A forming germanium silicon shielding layer on the skew sidewall 104A of NMOS, as referring to figure 1e.The residual 1051A of germanium silicon shielding layer impacts forming the processing step such as (step 6-1), source-drain electrode formation (step 7-1) to follow-up side wall, will be easy to cause device bad.
If it is excessive to cross the technique amount of carving, then can to the hard mask 103B of the dummy grid of PMOS ", dummy grid top flank and AA district damage, and forms dummy grid top flank defect 1081 and AA district defect 1091, as shown in fig. 1f.And dummy grid top flank defect 1081 and AA district defect 1091, nickle silicide to be caused in subsequent metal metallization processes (step 7-2) in the improper deposition of defective locations, cause device performance to decline or device bad.In high-K metal gate technology, the dummy grid of NMOS and PMOS all can not grow NiSi.Especially for PMOS, the process risk of prior art is very large.
In scheme two:
Step 8-2 generally comprises: close on technology (SPT) by stress and carry out wet etching to remove germanium silicon shielding layer 105A, the hard mask 103 of dummy grid, the skew sidewall 104A of nmos area, and the germanium silicon shielding layer 105B in PMOS district " (interim side wall), the hard mask 103B of dummy grid " and skew sidewall 104B.If define other side wall layer (such as master wall), also need to remove in the lump.
Thickness due to the germanium silicon shielding layer 105A of nmos area is greater than the germanium silicon shielding layer 105B in PMOS district "; the thickness of dummy grid hard mask 103A is greater than the hard mask 103B of dummy grid ", therefore, must carry out quarter (the germanium silicon shielding layer 104B in relative PMOS district " and dummy grid hard mask 103B ") to remove germanium silicon shielding layer 105A and the hard mask 103A of dummy grid of nmos area completely.Those skilled in the art are appreciated that owing to also there are other steps before step 8-2, after step 4, therefore, in step 8-2, the pattern of the germanium silicon shielding layer of nmos area and the hard mask of dummy grid may there occurs change, is no longer the pattern of 105A and 103A, does not repeat herein.
If cross the technique amount of carving very little, then the hard mask of the dummy grid of nmos area can be caused to remain 1031A and side wall layer remains (be generally the residual of skew sidewall, or, skew sidewall and germanium silicon shielding layer residual) 1041A, as shown in Figure 1 G.The hard mask of dummy grid remains 1031A can be caused needing in follow-up ILDCMP technique to carry out more crossing polishing, and then the height of metal gates can be caused to reduce; Side wall layer remains 1041A and then can impact processing steps such as follow-up ILD formation, easily causes the device performance even device that declines bad.
If it is excessive to cross the technique amount of carving, then can damages the sidewall of the AA district of PMOS and dummy grid 102B and top, form dummy grid defect 1082 and AA district defect 1092, as shown in fig. 1h.And dummy grid defect 1082 and AA district defect 1092, nickle silicide to be caused in subsequent metal metallization processes (step 7-2) in the improper deposition of defective locations, causes the device performance even device that declines bad.In high-K metal gate technology, the dummy grid of NMOS and PMOS all can not grow NiSi.Especially for PMOS, the process risk of prior art is very large.
As can be seen here, in the manufacture method of existing semiconductor device, because germanium silicon shielding layer and the hard mask of dummy grid are in the uneven thickness weighing apparatus problem of NMOS area and PMOS area, caused crossing excessive or too small all will being easy to of carving technology amount and caused the bad of device.Therefore, in order to improve device performance and yield, removing the germanium silicon shielding layer before technique and the hard mask of the dummy grid uneven thickness weighing apparatus problem in NMOS area and PMOS area, be a technical problem urgently to be resolved hurrily.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising:
Step S101: Semiconductor substrate is provided, described Semiconductor substrate comprises the dummy grid, the hard mask of dummy grid that are positioned at nmos area and is positioned at dummy grid, the hard mask of dummy grid in PMOS district;
Step S102: form germanium silicon shielding layer on the semiconductor substrate, described germanium silicon shielding layer comprises the germanium silicon shielding layer of nmos area and the germanium silicon shielding layer in PMOS district;
Step S103: the photoresist forming patterning above the germanium silicon shielding layer of described nmos area, namely described NMOS area is completely by described photoresist covering protection; Interim side wall is formed for the germanium silicon shielding layer of mask to described PMOS district etches with the outside of the dummy grid in described PMOS district with described photoresist;
Step S104: etch described Semiconductor substrate and form groove with the both sides of the dummy grid in described PMOS district;
Step S105: wet etching process is carried out to described Semiconductor substrate;
Step S106: form germanium silicon layer in described groove;
Step S107: etching processing is carried out to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid, forms interim side wall with the outside of the dummy grid in described nmos area; The interim side wall of described nmos area is consistent with the interim side wall in described PMOS district and the thickness difference of the hard mask of dummy grid with the hard mask of dummy grid.
Preferably, the hard mask of dummy grid in the hard mask of the dummy grid of described nmos area, described PMOS district is silicon nitride; The material of described germanium silicon shielding layer is silicon nitride, or silica and silicon nitride (particularly, silicon nitride is upper, and silicon nitride is main body, and thickness is thicker, and silica is only for protecting the silicon nitride of offset side wall when germanium silicon shielding layer wet method is removed); And the consistency of thickness of the hard mask of dummy grid of described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district.
Preferably, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is greater than the thickness of the interim side wall in described PMOS district formed in described step S103.
Further, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is
, the thickness of the described germanium silicon shielding layer formed in described step S102 is
.
Wherein, in described step S101, the dummy grid of described nmos area and the dummy grid in described PMOS district are polysilicon or amorphous silicon material.
Preferably, in described step S102, the method for described formation germanium silicon shielding layer is: form one deck silicon nitride film on the semiconductor substrate, or forms the thin silicon oxide film of one deck and the thicker silicon nitride film of one deck.
Further, the method forming described silicon nitride film comprises: hot-forming method, chemical vapour deposition technique or atomic layer deposition method.
Preferably; in described step S103; the method forming the photoresist of patterning above the germanium silicon shielding layer of described nmos area is: apply one deck photoresist film on the semiconductor substrate; after utilizing mask board to explosure, development; above the germanium silicon shielding layer of described nmos area, form the photoresist of a pattern layers, namely described nmos area is completely by described photoresist covering protection.
Preferably, in described step S106, the method forming germanium silicon layer is epitaxial growth technology.
Preferably, described epitaxial growth technology is the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, ultra-high vacuum CVD, rapid thermal CVD and molecular beam epitaxy.
Preferably, described step S107 comprises:
Another photoresist of patterning is formed above the germanium silicon shielding layer in described PMOS district;
Utilize another photoresist described to be mask, etching processing is carried out to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid.
Further; in described step S107; the method forming another photoresist of patterning above the germanium silicon shielding layer in described PMOS district is: apply one deck photoresist film on the semiconductor substrate; after utilizing another mask board to explosure, development; above the germanium silicon shielding layer in described PMOS district, form another photoresist of a pattern layers, namely described PMOS district is completely by another photoresist institute covering protection described.
Further, in described step S107, the method for carrying out exposing is: adopt KrF photoetching equipment to carry out exposing or adopt argon fluoride photoetching equipment to expose.
Preferably, another photoresist described in the patterning formed in described step S107, with the described photoresist formed in described step S103, position on the semiconductor substrate exists overlapping.
Further, the width of described photoresist and another photoresist described overlapping region is on the semiconductor substrate 20-35nm.
Preferably, the method for carrying out etching processing to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid in described step S107 is dry etching.
Preferably, between described step S101 and described S102, also comprise the step of carrying out light dope process.
Further, after described step S107, also step S108 is comprised: remove the interim side wall of described nmos area and the interim side wall in described PMOS district.
Preferably, in described step S108, the method for the interim side wall of the nmos area described in removal and the interim side wall in described PMOS district is wet etching.
Preferably, in described step S108, the etching liquid that described wet etching uses is phosphoric acid.
Further, after described step S108, also comprise step S109: the master wall of the formation nmos area, outside of the dummy grid in described nmos area, the outside of the dummy grid in described PMOS district forms the master wall in PMOS district.
Further, after described step S109, also step S110 is comprised: carry out heavy ion doping on the semiconductor substrate with the source-drain electrode forming described NMOS and PMOS.
Further, after described step S110, also step S111 is comprised: on described source-drain electrode, form metal silicide.
Further, after described step S111, also step S112 is comprised: stress is carried out to described Semiconductor substrate and closes on technical finesse.
Further, after described step S112, also comprise the step forming metal gates.
The present invention carries out the technique of etching processing by the extra germanium silicon shielding layer to nmos area of increase and the hard mask of dummy grid, germanium silicon shielding layer and the hard mask of dummy grid are reached unanimity at the thickness of NMOS area and PMOS area, solve and remove the uneven thickness weighing apparatus problem in NMOS area and PMOS area of germanium silicon shielding layer and the hard mask of dummy grid before technique, the removal of germanium silicon shielding layer and the hard mask of dummy grid can be realized when not needing very large carving technology amount excessively, the hard mask of dummy grid avoiding NMOS remains, side wall layer remains and the dummy grid defect in PMOS district, AA district defect and the growth of dummy grid upper end flank abnormal nickle silicide etc. are bad, improve performance and the yield of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 H is the schematic cross sectional view of each step of manufacture method of semiconductor device in prior art;
Fig. 2 A-Fig. 2 J is the schematic cross sectional view of each step of manufacture method of the semiconductor device that the present invention proposes;
Fig. 3 is the flow chart of the manufacture method of a kind of semiconductor device that the present invention proposes.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the manufacture method of the semiconductor device that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the detailed step of a manufacture method illustrative methods of the semiconductor device that the present invention proposes is described with reference to Fig. 2 A-Fig. 2 J and Fig. 3.The method is the manufacture method of the semiconductor device of application high-k/metal gate technology, for improving device performance and yield.
With reference to Fig. 2 A-Fig. 2 J, illustrated therein is the schematic cross sectional view of each step of the manufacture method of the semiconductor device that the present invention proposes.
Step S201: Semiconductor substrate is provided.
This Semiconductor substrate 200 comprises NMOS area and PMOS area, and be formed with dummy grid 202A, the hard mask 203A of dummy grid and skew sidewall 204A that are positioned at nmos area on a semiconductor substrate, be positioned at the grid 202B in PMOS district, the hard mask 203B of dummy grid and skew sidewall 204B, as shown in Figure 2 A.Wherein, the dummy grid 202A of nmos area and the dummy grid 202B in PMOS district can be referred to as dummy grid, and their material is generally polysilicon.The dummy grid hard mask 203A of nmos area and the dummy grid hard mask 203B in PMOS district is referred to as the hard mask of dummy grid, the two consistency of thickness, and their material is preferably silicon nitride.The skew sidewall 204A of nmos area and the skew sidewall 204B in PMOS district is referred to as skew sidewall; the two consistency of thickness; skew sidewall can be one deck silicon nitride film; also can be the composite membrane of sull and silicon nitride film composition; the present embodiment is preferably the composite membrane of the main body silicon nitride film composition of very thin sull and thickening, and very thin silicon oxide film is not only for being removed substantially simultaneously except the protection of germanium silicon shielding layer silicon nitride offsets sidewall silicon nitride at wet etching etching off.The embodiment of the present invention is the manufacture method of the semiconductor device of application high-k/metal gate technology, in the method, dummy grid is only the position temporarily occupying grid in the processing procedure of semiconductor device, can be removed in subsequent technique, and substitute by the real metal gates as grid.
Exemplarily, in the present embodiment, described Semiconductor substrate selects single crystal silicon material to form.Isolation structure 201 (as shown in Figure 2 A) is formed in described Semiconductor substrate, described isolation structure be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, described isolation structure Semiconductor substrate is divided into NMOS part and PMOS part.Also be formed with various trap (well) structure in described Semiconductor substrate 200, in order to simplify, be omitted in diagram.The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure, by those skilled in the art are had the knack of, is described no longer in detail at this.
Step S202: form one deck germanium silicon shielding layer on a semiconductor substrate.
Form one deck germanium silicon shielding layer 205 on semiconductor substrate 200, this germanium silicon shielding layer comprises germanium silicon shielding layer (namely germanium silicon shielding layer is positioned at the part of the PMOS area) 205B in germanium silicon shielding layer (namely germanium silicon shielding layer is positioned at the part of NMOS area) 205A and the PMOS district of nmos area, as shown in Figure 2 B.Wherein, germanium silicon shielding layer 205 can be single layer structure, can be such as silicon nitride (SiN) film, also can be sandwich construction, can be such as the composite membrane of silicon nitride film and sull composition.The composite membrane that the present embodiment preferably adopts the main body silicon nitride film of very thin sull and thickening to form, very thin silicon oxide film is not only for being removed substantially simultaneously except the protection of germanium silicon shielding layer silicon nitride offsets sidewall silicon nitride at wet etching etching off.The material of main part of germanium silicon shielding layer 205 is silicon nitride, with the material identical (being silicon nitride) of the hard mask of dummy grid 203A with 203B, is convenient to subsequent technique and they is removed in the lump.
Wherein, the method forming germanium silicon shielding layer 205 can be: form one deck silicon nitride film on the semiconductor substrate.The method forming described silicon nitride film comprises: hot-forming method, chemical vapour deposition technique or atomic layer deposition method.
Preferably, in the embodiment of the present invention, the hard mask of dummy grid and germanium silicon shielding layer are silicon nitride material, and the thickness of the hard mask of dummy grid is greater than the thickness of germanium silicon shielding layer, namely the consistency of thickness of the hard mask 203B of the dummy grid in the dummy grid of nmos area hard mask 203A and PMOS district and thickness are greater than the thickness of germanium silicon shielding layer 205.Its object is to protect dummy grid better, preventing dummy grid top of the prior art flank defect.Further, in embodiments of the present invention, the thickness of the hard mask of dummy grid can be set to
, the thickness of germanium silicon shielding layer 205 can be set to
.
Wherein, in embodiments of the present invention, between step S201 and S202, the step of carrying out light dope (LDD) and processing can also be comprised, to prevent short-channel effect.In embodiments of the present invention, if do not carry out light dope (LDD) treatment process, then in step s 201, described Semiconductor substrate 200 can not be formed the skew sidewall 204A of nmos area and the skew sidewall 204B in PMOS district.It will be appreciated by those skilled in the art that, if do not form skew sidewall 204A and 204B in step s 201, then other steps follow-up also can not relate to the problems such as the removal of skew sidewall 204A and 204B, the each Rotating fields (such as interim side wall) be directly formed at outside skew sidewall 204A and 204B then directly can be formed at the outside of dummy grid, hereafter repeats no more.
Step S203: the photoresist forming a pattern layers above the germanium silicon shielding layer of nmos area, carries out to germanium silicon shielding layer the interim side wall that dry etching forms PMOS.
Particularly, step S203 comprises:
First, apply one deck photoresist film on a semiconductor substrate, after then utilizing mask board to explosure, development, above the germanium silicon shielding layer 205A of nmos area, form the photoresist 800A of a pattern layers, as shown in Figure 2 C.The photoresist 800A of this patterning is positioned at the part 205A of NMOS area for the protection of germanium silicon shielding layer.Wherein, can expose for adopting KrF (KrF) photoetching equipment or argon fluoride (ArF) photoetching equipment the method that photoresist film exposes.
Then, dry etching is carried out to germanium silicon shielding layer (namely germanium silicon shielding layer is positioned at the part of the PMOS area) 205B in PMOS district, etch away the part above the hard mask 203B of the dummy grid in PMOS district of the germanium silicon shielding layer 205B in PMOS district and the part between dummy grid 202B, interim side wall 205B ' is formed, as shown in Figure 2 C in the outside of skew sidewall 204B.Wherein, the thickness of the hard mask of dummy grid of the described nmos area in step S201 and the hard mask of dummy grid in described PMOS district; be greater than the thickness of the interim side wall in described PMOS district formed in described step S103; to protect dummy grid better, prevent dummy grid top of the prior art flank defect.
Step S204: form groove in the dummy grid both sides of PMOS area.
Carry out dry etching, the both sides of the dummy grid 202B in PMOS district etch the groove 206 for deposit Germanium silicon layer on semiconductor substrate 200, and this groove is similar bowl-shape, as shown in Figure 2 C.
In step S204, carrying out dry etching to be formed in the process of groove 206, the hard mask 203B of dummy grid can be etched to a certain extent, forms the hard mask 203B ' of dummy grid after etching, as shown in Figure 2 C.
Through abovementioned steps S203 and S204, there is difference in the thickness of the part 205A of germanium silicon shielding layer in NMOS area and the part 205B ' in PMOS area (i.e. interim side wall 205B '), difference has also appearred in the thickness of the dummy grid hard mask 203A of nmos area and the hard mask 203B ' of dummy grid in PMOS district.That is, there is in the distribution of NMOS and PMOS area the phenomenon that uneven thickness weighs in germanium silicon shielding layer 205 and the hard mask of dummy grid, as shown in Figure 2 C.
Step S205: carry out wet etching process.
Carry out wet etching treatment, use TMAH etc. are as etching liquid.The shape of groove 206 can be improved by wet etching, such as the similar bowl-shape groove 206 that abovementioned steps etching is formed is etched into similar orthohexagonal shape 206 ', so that the deposition of the germanium silicon of follow-up germanium silicon technology, as shown in Figure 2 D.For the photoresist 800A of nmos area, can remove before this step is carried out, also can remove after completing this step, can also row removal again after completing this step and complete follow-up germanium silicon-containing layer deposition technique.
In this step, in wet etching process, the interim sidewall 205B ' (i.e. the germanium silicon shielding layer in PMOS district) in PMOS district and the hard mask 203B ' of dummy grid will be etched further, forms interim sidewall (i.e. the germanium silicon shielding layer in the PMOS district) 205B after being further etched " and the hard mask 203B of dummy grid ".If removed photoresist 800A before this step, then the part 204A that germanium silicon shielding layer is positioned at NMOS area also can be etched to a certain extent, the present embodiment to be described at follow-up removal photoresist 800A, as shown in Figure 2 D.
Through this step, germanium silicon shielding layer and the hard mask of dummy grid are typically further exacerbated in the uneven thickness weighing apparatus phenomenon of NMOS and PMOS area, as shown in Figure 2 D.
Step S206: form germanium silicon layer in a groove.
Germanium silicon layer 207 is formed, as shown in Figure 2 D in groove 206 '.The method forming germanium silicon layer 207 can adopt epitaxial growth technology.Described epitaxial growth technology can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
Step S207: etching processing is carried out to the germanium silicon shielding layer of nmos area and the hard mask of dummy grid, form interim side wall with the both sides of the dummy grid in described nmos area (being specially the outside of skew sidewall), the interim side wall of described nmos area is consistent with the interim side wall in PMOS district and the thickness difference of the hard mask of dummy grid with the hard mask of dummy grid.Wherein, the method for carrying out etching processing is preferably dry etching.
Wherein, the interim side wall (i.e. the germanium silicon shielding layer of nmos area) of nmos area is consistent with the interim side wall (i.e. the germanium silicon shielding layer in PMOS district) in PMOS district and the thickness difference of the hard mask of dummy grid with the hard mask of dummy grid, refer to that the interim side wall of nmos area is consistent with the interim side wall thicknesses in PMOS district, the hard mask of dummy grid of nmos area is consistent with the hard mask thicknesses of the dummy grid in PMOS district.That is, germanium silicon shielding layer is balanced in the thickness distribution of NMOS area and PMOS area, and the hard mask of dummy grid is balanced in the thickness distribution in nmos area and PMOS district.
Particularly, step S207 can comprise the steps:
First, the germanium silicon shielding layer 205B in PMOS district " top of (namely germanium silicon layer is positioned at the part of PMOS area) forms another photoresist 800B of a pattern layers, as shown in Figure 2 E.It should be noted that, the photoresist 800A before formed, was removed before this step, and its time of removing can be one of kind of situation of three described in abovementioned steps S205, does not repeat herein.
Particularly, the method forming another photoresist 800B of patterning is: apply one deck photoresist film on a semiconductor substrate, then, after utilizing mask board to explosure, development, another photoresist 800B of a pattern layers on the part being positioned at PMOS area at germanium silicon shielding layer, is formed.The photoresist 800B of this patterning is for the protection of the germanium silicon shielding layer 205B in PMOS district ".Wherein, can expose for adopting KrF (KrF) or argon fluoride (ArF) the method that photoresist film exposes.The tone (tone) of the mask plate that the photoresist 800A that the mask plate that this step uses and abovementioned steps form patterning uses is contrary.
Preferably, the photoresist 800A position on semiconductor substrate 200 of the patterning formed in the photoresist 800B of patterning and abovementioned steps S203 is existed overlapping (overlap), is repeated etching to avoid the relevant position of Semiconductor substrate 200 (such as AA district).Further preferably, the width of photoresist 800B and photoresist 800A overlapping region on semiconductor substrate 200 can be set to 20-35nm.
Then, utilize photoresist 800B for mask, etching processing is carried out to the germanium silicon shielding layer 205A of nmos area and the hard mask 203A of dummy grid, form interim side wall 205A in the both sides (being specially the both sides of skew sidewall 204A) of the dummy grid 202A of described nmos area "; make the interim side wall 205A of described nmos area " with the interim side wall 205B in PMOS district " consistency of thickness; the dummy grid hard mask 203A of the nmos area after etching " with the hard mask 203B of dummy grid in PMOS district " consistency of thickness, as shown in Figure 2 F.In this step, after etching processing completes, also comprise the step removing photoresist 800B.Etching processing completes and after removing photoresist 800B, the figure of formation as shown in Figure 2 F.If be provided with overlapping (overlap) of photoresist, general meeting forms residual (silicon nitride residue) of germanium silicon shielding layer at overlapping region, but this remains can not cause negative effect to product processing procedure, and this residual meeting be removed in follow-up ILDCMP technique.
Wherein, described etching processing can adopt dry mode of carving.Specifically, the dry etching condition carved can be consistent with traditional handicraft, such as uses CF
4, CHF
3, O
2with Ar as etching gas, set their flow velocitys and be followed successively by 0-30sccm, 0-20sccm, 8-20sccm and 30-100sccm, pressure is 0-10mtor, and bias voltage is 100-300V.Further, CH
2f
2, CO
2, the gases such as CO also can be used.For another example: use CH
3f, He and O
2as etching gas, set their flow velocitys and be followed successively by 100-300sccm, 100-300sccm and 100-200sccm, pressure position 20-60mtor, bias voltage is 150-200V.For concrete etch technological condition, do not limit at this.When forming the hard mask of dummy grid and germanium silicon shielding layer with silicon nitride at first, if as previously mentioned the thickness of hard for dummy grid mask is set to
, the thickness of germanium silicon shielding layer 205 is set to
; So, after this step, the interim side wall 205A of nmos area " with the interim side wall 205B in PMOS district " thickness is approximately
.
Through this step, achieve germanium silicon shielding layer and the hard mask of the dummy grid thickness equiblibrium mass distribution in NMOS area and PMOS area.
Those skilled in the art will appreciate that this step S207 can be applied to " front germanium silicon (EarlySiGe) ", " middle germanium silicon (MiddleSiGe) ", in the technology such as " front germanium silicon (LateSiGe) ".
So far, the manufacture method of the semiconductor device of the embodiment of the present invention, by carrying out the technique of etching processing to the germanium silicon shielding layer of nmos area and the hard mask of dummy grid, germanium silicon shielding layer and the hard mask of dummy grid are reached unanimity at the thickness of NMOS area and PMOS area, solve and remove the uneven thickness weighing apparatus problem in NMOS area and PMOS area of germanium silicon shielding layer and the hard mask of dummy grid before technique, therefore the hard mask of the dummy grid of the nmos area occurred in prior art can be avoided to remain, side wall layer remain and the dummy grid defect and AA district defect etc. in PMOS district bad, improve performance and the yield of device.
After completing steps S207, subsequent step then can be selected the two schemes of the removal about germanium silicon shielding layer mentioned in background technology according to actual needs, below to remove germanium silicon shielding layer (scheme one in background technology) immediately after formation germanium silicon layer, brief description is carried out to the subsequent step of the embodiment of the present invention.Those skilled in the art will appreciate that subsequent step of the present invention is not as limit, on the contrary, the technical scheme (scheme two mentioned in such as background technology) of all application of aforementioned steps, all belongs to the protection range of the embodiment of the present invention.
In embodiments of the present invention, after step S207, proceed following processing step:
With the interim side wall 205B in PMOS district " step S208: the interim side wall 205A removing described nmos area ".
Utilize wet etching, adopt phosphoric acid (H
3pO
4) or other suitable etching liquids, etching processing is carried out to Semiconductor substrate 200, removes the interim side wall 205A being positioned at nmos area " and the interim side wall 205B in PMOS district ", retain skew sidewall 204A and 204B, the figure of formation after etching, as shown in Figure 2 G.In this step, the dummy grid hard mask 203A of nmos area " with the dummy grid hard mask 203B in PMOS district " also can be further etched (etching degree close), for statement convenience, the hard mask 203A of not shown dummy grid in Fig. 2 G " and 203B " associated change.
Because the germanium silicon shielding layer of nmos area and the hard mask of dummy grid are eliminated a part by step S207, achieve germanium silicon shielding layer and the hard mask of the dummy grid thickness equiblibrium mass distribution in NMOS area and PMOS area, therefore, in this step, there is when wet etching enough large process window (processwindow), germanium silicon shielding layer (interim side wall) can be removed well, and there will not be in prior art that nmos area germanium silicon shielding layer (interim side wall) that is that cause is residual or the dummy grid top flank defect in PMOS district and AA district defect etc. are bad owing to crossing that carving technology amount is too small or excessive, especially the dummy grid top flank defect in PMOS district can not be caused, can not impact subsequent technique (especially metallization forms the technique of NiSi), to a certain degree providing performance and the yield of device.
Step S209: form master wall in the outside of skew sidewall.
Form master wall in the outside of skew sidewall, particularly, the outside of the master wall 208A of the formation nmos area, outside of the skew sidewall 204A in nmos area, the skew sidewall 204B in PMOS district forms the master wall 208B in PMOS district, as illustrated in figure 2h.The master wall 208A of nmos area and the master wall 208B in PMOS district together constitutes the master wall of semiconductor device, and the two preferred thickness is consistent.Master wall 208A and master wall 208B can be single layer structure (such as silicon nitride film) also can be sandwich construction (composite membrane of such as sull and silicon nitride film composition); Preferably, master wall 208A and master wall 208B is silicon nitride film.
Step S210: carry out heavy ion doping on a semiconductor substrate with the source-drain electrode forming NMOS and PMOS.
After step S209, generally comprise and carry out the step that heavy ion doping forms the source-drain electrode of NMOS and PMOS.This step is identical with traditional handicraft, does not go to live in the household of one's in-laws on getting married herein.The perfection achieving germanium silicon shielding layer due to abovementioned steps is removed, and then by skew sidewall and the side wall layer that forms of the master wall consistency of thickness in NMOS area and PMOS area, therefore, the ion doping step forming source-drain electrode is more consistent, and then the device property of NMOS with PMOS formed is more consistent, thus makes device performance obtain certain raising.
Step S211, on source-drain electrode, form metal silicide.
By forming the processing steps such as self aligned polycide shielding layer (SAB), etching, prerinse, metal level deposition, heat treatment, source-drain electrode forms metal silicide (NiSi) 209, as shown in figure 2i.Form the step of metal silicide, method of the prior art can be adopted, do not repeat herein.
Due to aforementioned the germanium silicon shielding layer and the hard mask of dummy grid that define consistency of thickness, therefore, when follow-up removal germanium silicon shielding layer, the defect that can not produce the dummy grid 202B of PMOS and AA district is bad, thus in this step, metal silicide (NiSi) can not be produced, as shown in figure 2i in the top of dummy grid 202B and side and AA district.That is, there will not be of the prior art bad, relative to prior art, improve device performance and yield.
It should be noted that, when when forming the hard mask of dummy grid and germanium silicon shielding layer with silicon nitride at first, if as previously mentioned the thickness of hard for dummy grid mask is set to
, the thickness of germanium silicon shielding layer 205 is set to
; So, through before this step, the dummy grid hard mask 203A of nmos area " with the hard mask 203B of dummy grid in PMOS district " thickness is approximately
.
Step S212, stress carried out to described Semiconductor substrate close on technical finesse, and remove skew sidewall 204A, master wall 208A and the dummy grid hard mask 203A of nmos area " and skew sidewall 204B, the master wall 208B in PMOS district and the hard mask 203B of dummy grid ".
In order to improve device performance, stress being carried out to described Semiconductor substrate and closes on technology (SPT) process; Then, removed skew sidewall 204A, master wall 208A and the dummy grid hard mask 203A of nmos area in the lump by etching technics " and skew sidewall 204B, the master wall 208B in PMOS district and the hard mask 203B of dummy grid ", the figure of formation is as shown in fig. 2j.Wherein, stress closes on technical finesse, can adopt conventional method of the prior art; Remove skew sidewall 204A and 204B, master wall 208A and 208B, the hard mask 203A of dummy grid " and 203B " lithographic method, can dry etching or wet etching etc. be adopted.After completing this step, the external morphology of dummy grid 202A and 202B is good, does not occur defect and bad, as shown in fig. 2j.
After step s 212, generally also comprise: form the step of contact hole etching barrier layer (CESL) and interlayer dielectric layer (ILD), form the step of metal gates (MG), form the subsequent process steps such as the step of contact hole (CT) and metal level, to complete the manufacture of whole semiconductor device, these steps are identical with the manufacture method of traditional semiconductor device, repeat no more herein.
It will be appreciated by those skilled in the art that, in embodiments of the present invention, remove the step (i.e. step S208) of germanium silicon shielding layer (i.e. interim side wall), also can be placed on after carrying out SPT, then remove skew sidewall, interim side wall and master space sidewall together.Also other modes can be adopted to carry out; as long as comprise the manufacture method of the semiconductor device of the processing step that the technique of carrying out etching processing to the germanium silicon shielding layer of nmos area and the hard mask of dummy grid makes germanium silicon shielding layer and the hard mask of dummy grid reach unanimity at the thickness of NMOS area and PMOS area, all belong to the scope of protection of the invention.About specific implementation, be not limited with the embodiment of the present invention, do not repeat one by one herein.
The manufacture method of the semiconductor device of the embodiment of the present invention, the step of etching processing is carried out by increasing the extra germanium silicon shielding layer to nmos area and the hard mask of dummy grid, germanium silicon shielding layer and the hard mask of dummy grid are reached unanimity at the thickness of NMOS area and PMOS area, solve and remove the unbalanced problem of thickness distribution in NMOS area and PMOS area of germanium silicon shielding layer and the hard mask of dummy grid before technique, the good removal of germanium silicon shielding layer and the hard mask of dummy grid can be realized when not needing very large carving technology amount excessively, the hard mask of dummy grid avoiding the nmos area occurred in prior art remains, side wall layer remain and the dummy grid defect and AA district defect etc. in PMOS district bad, improve performance and the yield of device.
With reference to Fig. 3, illustrated therein is the flow chart of a kind of typical method in the manufacture method of the semiconductor device that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step S101, provide Semiconductor substrate, described Semiconductor substrate comprises the dummy grid, the hard mask of dummy grid that are positioned at nmos area and offsets sidewall and be positioned at the dummy grid in PMOS district, the hard mask of dummy grid and skew sidewall;
In step s 102, form germanium silicon shielding layer on the semiconductor substrate, described germanium silicon shielding layer comprises the germanium silicon shielding layer of nmos area and the germanium silicon shielding layer in PMOS district;
In step s 103, above the germanium silicon shielding layer of described nmos area, form the photoresist of patterning, form interim side wall for the germanium silicon shielding layer of mask to described PMOS district etches with the outside of the skew sidewall in described PMOS district with described photoresist;
In step S104, etch described Semiconductor substrate and form groove with the both sides of the dummy grid in described PMOS district;
In step S105, wet etching process is carried out to described Semiconductor substrate;
In step s 106, in described groove, germanium silicon layer is formed;
In step s 107, etching processing is carried out to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid, forms interim side wall with the outside of the skew sidewall in described nmos area; The interim side wall of described nmos area is consistent with the interim side wall in described PMOS district and the thickness difference of the hard mask of dummy grid with the hard mask of dummy grid.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (25)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S101: Semiconductor substrate is provided, described Semiconductor substrate comprises the dummy grid, the hard mask of dummy grid that are positioned at nmos area and is positioned at dummy grid, the hard mask of dummy grid in PMOS district;
Step S102: form germanium silicon shielding layer on the semiconductor substrate, described germanium silicon shielding layer comprises the germanium silicon shielding layer of nmos area and the germanium silicon shielding layer in PMOS district;
Step S103: the photoresist forming patterning above the germanium silicon shielding layer of described nmos area, forms interim side wall for the germanium silicon shielding layer of mask to described PMOS district etches with the outside of the dummy grid in described PMOS district with described photoresist;
Step S104: etch described Semiconductor substrate and form groove with the both sides of the dummy grid in described PMOS district;
Step S105: wet etching process is carried out to described Semiconductor substrate;
Step S106: form germanium silicon layer in described groove;
Step S107: etching processing is carried out to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid, forms interim side wall with the outside of the dummy grid in described nmos area; The interim side wall of described nmos area is consistent with the interim side wall in described PMOS district and the thickness difference of the hard mask of dummy grid with the hard mask of dummy grid.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the hard mask of dummy grid of described nmos area, the hard mask of dummy grid in described PMOS district are silicon nitride; The material of described germanium silicon shielding layer is silicon nitride, or is silica and silicon nitride; And the consistency of thickness of the hard mask of dummy grid of described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district.
3. the manufacture method of semiconductor device as claimed in claim 2, it is characterized in that, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is greater than the thickness of the interim side wall in described PMOS district formed in described step S103.
4. the manufacture method of semiconductor device as claimed in claim 3, it is characterized in that, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is
the thickness of the described germanium silicon shielding layer formed in described step S102 is
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S101, the dummy grid of described nmos area and the dummy grid in described PMOS district are polysilicon or amorphous silicon material.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S102, the method for described formation germanium silicon shielding layer is: form one deck silicon nitride film on the semiconductor substrate, or formation one deck silica adds silicon nitride film.
7. the manufacture method of semiconductor device as claimed in claim 6, it is characterized in that, the method forming described silicon nitride film comprises: hot-forming method, chemical vapour deposition technique or atomic layer deposition method.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S103, the method forming the photoresist of patterning above the germanium silicon shielding layer of described nmos area is: apply one deck photoresist film on the semiconductor substrate, after utilizing mask board to explosure, development, above the germanium silicon shielding layer of described nmos area, form the photoresist of a pattern layers.
9. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S106, the method forming germanium silicon layer is epitaxial growth technology.
10. the manufacture method of semiconductor device as claimed in claim 9, it is characterized in that, described epitaxial growth technology is the one in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, ultra-high vacuum CVD, rapid thermal CVD and molecular beam epitaxy.
The manufacture method of 11. semiconductor device as claimed in claim 1, it is characterized in that, described step S107 comprises:
Another photoresist of patterning is formed above the germanium silicon shielding layer in described PMOS district; Utilize another photoresist described to be mask, etching processing is carried out to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid.
The manufacture method of 12. semiconductor device as claimed in claim 11, it is characterized in that, in described step S107, the method forming another photoresist of patterning above the germanium silicon shielding layer in described PMOS district is: apply one deck photoresist film on the semiconductor substrate, after utilizing another mask board to explosure, development, above the germanium silicon shielding layer in described PMOS district, form another photoresist of a pattern layers.
The manufacture method of 13. semiconductor device as claimed in claim 12, is characterized in that, in described step S107, the method for carrying out exposing is: adopt KrF photoetching equipment to carry out exposing or adopt argon fluoride photoetching equipment to expose.
The manufacture method of 14. semiconductor device as claimed in claim 11, it is characterized in that, another photoresist described in the patterning formed in described step S107, with the described photoresist formed in described step S103, position on the semiconductor substrate exists overlapping.
The manufacture method of 15. semiconductor device as claimed in claim 14, is characterized in that, the width of described photoresist and another photoresist described overlapping region is on the semiconductor substrate 20-35nm.
The manufacture method of 16. semiconductor device as claimed in claim 11, is characterized in that, the method for carrying out etching processing to the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid in described step S107 is dry etching.
The manufacture method of 17. semiconductor device as claimed in claim 1, is characterized in that, between described step S101 and described S102, also comprise the step of carrying out light dope process.
The manufacture method of 18. semiconductor device as claimed in claim 1, is characterized in that, after described step S107, also comprise step S108: remove the interim side wall of described nmos area and the interim side wall in described PMOS district.
The manufacture method of 19. semiconductor device as claimed in claim 18, is characterized in that, in described step S108, the method for the interim side wall of the nmos area described in removal and the interim side wall in described PMOS district is wet etching.
The manufacture method of 20. semiconductor device as claimed in claim 19, is characterized in that, in described step S108, the etching liquid that described wet etching uses is phosphoric acid.
The manufacture method of 21. semiconductor device as claimed in claim 18, it is characterized in that, after described step S108, also comprise step S109: the master wall of the formation nmos area, outside of the dummy grid in described nmos area, the outside of the dummy grid in described PMOS district forms the master wall in PMOS district.
The manufacture method of 22. semiconductor device as claimed in claim 21, is characterized in that, after described step S109, also comprise step S110: carry out heavy ion doping on the semiconductor substrate with the source-drain electrode forming described NMOS and PMOS.
The manufacture method of 23. semiconductor device as claimed in claim 22, is characterized in that, after described step S110, also comprise step S111: on described source-drain electrode, form metal silicide.
The manufacture method of 24. semiconductor device as claimed in claim 23, is characterized in that, after described step S111, also comprise step S112: carry out stress to described Semiconductor substrate and close on technical finesse.
The manufacture method of 25. semiconductor device as claimed in claim 24, is characterized in that, also comprises the step forming metal gates after described step S112.
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| CN104979178B (en) * | 2014-04-10 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN104979294B (en) * | 2014-04-10 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN105097484A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN105097462B (en) * | 2014-04-22 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN105448832B (en) * | 2014-08-21 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN105304570A (en) * | 2015-10-26 | 2016-02-03 | 上海华力微电子有限公司 | Method for removing grid hard mask layers |
| CN109727855B (en) * | 2018-12-29 | 2020-11-24 | 上海华力集成电路制造有限公司 | Method for removing nitride mask layer after germanium-silicon growth |
| CN111180321A (en) * | 2020-02-04 | 2020-05-19 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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