CN103681500A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN103681500A CN103681500A CN201210337269.XA CN201210337269A CN103681500A CN 103681500 A CN103681500 A CN 103681500A CN 201210337269 A CN201210337269 A CN 201210337269A CN 103681500 A CN103681500 A CN 103681500A
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- germanium silicon
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- 238000005530 etching Methods 0.000 claims abstract description 45
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 47
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The invention provides a method for manufacturing a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: after a germanium-silicon forming process, etching a germanium-silicon shielding layer and a pseudo grid hard mask in an NMOS (N-Channel Metal Oxide Semiconductor) region so as to enable the thicknesses of the germanium-silicon shielding layers and the pseudo grid hard masks in the NMOS region and a PMOS (P-Channel Metal Oxide Semiconductor) region to be the same. Through the adoption of the method, the problem that the thicknesses of the germanium-silicon shielding layers and the pseudo grid hard masks in the NMOS region and the PMOS region are not uniform before the removal process is solved, pseudo grid hard mask residue in the NMOS region, side wall layer residue and pseudo grid hard mask defects of the PMOS region are avoided, badness of pseudo grid defects and defects of an AA (Acrylic Acid) region are avoided, the phenomenon of abnormal silicon nickel growth at the shoulder of the pseudo grid caused by the pseudo grid defects is avoided, and the performance and the yield of the device are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor device.
Background technology
In technical field of semiconductors, for the advanced polysilicon/silicon oxynitride technology below 45nm node, stress engineering becomes one of most important factor of device performance lifting.For PMOS, germanium silicon technology can improve carrier mobility by applying compression to raceway groove.Because germanium siliceous deposits is very responsive to the impurity of groove surfaces and oxide, therefore, conventionally total technique amount of the wet-etching techniques such as photoresist lift off, TMAH wet etching (be generally used for and improve groove shapes) and the prerinse of germanium silicon technology is arranged very greatly to reduce impurity and oxidation.In the prior art, because aforesaid wet-etching technique all can etching oxidation silicon, so germanium silicon shielding layer generally to adopt silicon nitride (SiN) or take silicon nitride be silica+silicon nitride bilayer film of main body composition in the above, but not pure silica.In order to stop, germanium silicon is in the improper depositional phenomenon on PMOS top after wet etching, and silicon nitride film is also often used as the hard mask of grid (or dummy grid).In prior art, generally by dry mode of carving in conjunction with wet etching, be formed for making the groove (can be sigma type or U-shaped etc.) of the PMOS of germanium silicon.Dry, carve in the process that forms groove; the germanium silicon shielding layer in PMOS district (also as interim side wall of the PMOS) can be etched away a part simultaneously; the germanium silicon shielding layer of nmos area can not be etched due to the protection of photoresist, and this has just caused the uneven thickness weighing apparatus of germanium silicon shielding layer in nmos area and PMOS district.For the manufacture of semiconductor of application high-k/metal gate technology, the germanium silicon shielding layer in above-mentioned nmos area and PMOS district (interim side wall) uneven thickness weighing apparatus phenomenon will become affects the removal of germanium silicon shielding layer and stress closes on technology (Stress Proximity Technique; Be called for short SPT) or interlayer dielectric layer (Inter Layer Dielectric; Be called for short ILD) chemico-mechanical polishing (Chemical Mechanical Polishing; Be called for short CMP) etc. the significant problem of subsequent technique.
For high-k/metal gate technology, in nickle silicide (NiSi) deposition process, hard mask protection must be arranged at the top of polysilicon (dummy grid), otherwise metal silicide (nickle silicide) can be formed on the top of polysilicon.And cannot remove metal silicide in dummy grid is removed technique, this has just caused the residual of metal silicide, and then causes metal gate cannot normally form (metal cannot deposition growing to the groove staying after former dummy grid removal).
If germanium silicon shielding layer is removed immediately after germanium silicon layer forms, cross so carving technology amount (over etch amount) and need to well be controlled.If cross carving technology amount very little, can cause interim side wall (being germanium silicon shielding layer) residual of nmos area, will directly affect the follow-up techniques such as side wall formation.If it is excessive to cross carving technology amount, can be to the hard mask of the dummy grid of PMOS, dummy grid top flank, side wall, even AA district damages.After metal silicide forms technique prerinse, the hard mask of destroyed dummy grid, dummy grid top flank and side wall cannot be protected dummy grid top flank in nickle silicide (NiSi) deposition process, and then cause the metallization of dummy grid (polysilicon).
If germanium silicon shielding layer is used as a part for side wall and is carried over into the processing step that stress closes on technology (SPT), the uneven thickness weighing apparatus problem of side wall still exists, too small or the excessive hard mask of dummy grid and/or the side wall of NMOS of still can causing of crossing carving technology amount is residual, or, the destruction of dummy grid top flank.If exist the hard mask of the dummy grid of NMOS residual, will in the ILD CMP technique follow-up, need to carry out more to cross polishing, and then can cause the height of the metal gates of actual formation to reduce.If dummy grid top flank is destroyed, after metal silicide forms the prerinse of technique, destroyed side wall cannot be protected dummy grid (polysilicon), and then cause the metallization (silicidation) of polysilicon.If the polysilicon of PMOS is destroyed in SPT technique, will cause metal gates to form rear metal gates destroyed.Therefore, to cross quarter amount be a very important problem to wet-etching technique.And, side wall layer (comprising skew sidewall, interim side wall, master wall etc.) is in territory, nmos area and the inconsistent problem of PMOS area thickness, also can to the consistency of NMOS and PMOS, cause harmful effect while forming source-drain electrode by Implantation follow-up, affect the performance of device.
A kind of manufacture method of traditional semiconductor device of take is below example, further introduces the above-mentioned problems in the prior art.The manufacture method of semiconductor device of the prior art, generally comprises following steps:
Step 1: Semiconductor substrate 100 is provided, and in Semiconductor substrate 100, form shallow trench isolation from (STI) 101, the hard mask 103A of dummy grid 102A, dummy grid that is positioned at nmos area and skew sidewall 104A, the hard mask 103B of dummy grid 102B, dummy grid that is positioned at PMOS district and skew sidewall 104B, as shown in Figure 1A.Wherein, the material of the hard mask 103A of dummy grid and 103B is silicon nitride.Dummy grid 102A and 102B are generally polysilicon or amorphous silicon material, are only in the processing procedure of semiconductor device, to occupy the position of grid temporarily, can be removed, and substituted by the real metal gates as grid in subsequent technique.
Step 2: form germanium silicon shielding layer 105 in Semiconductor substrate 100, this germanium silicon shielding layer 105 comprises part (being the germanium silicon shielding layer of the nmos area) 105A that is positioned at territory, nmos area and part (being the germanium silicon shielding layer in the PMOS district) 105B that is positioned at PMOS region, as shown in Figure 1B.Wherein, the material of germanium silicon shielding layer 105 can be silicon nitride or silica+silicon nitride (silicon nitride in the above, and thicker, be material of main part, silica is mainly used in protecting offset side wall not to be removed when removing all germanium silicon shielding layers).
Wherein, between step 1 and step 2, generally can also comprise the processing step that carries out light dope (LDD).
Step 3: the photoresist 600A that forms one deck patterning above the germanium silicon shielding layer 105A of nmos area, described Semiconductor substrate 100 is done to quarter, in the Semiconductor substrate 100 of the dummy grid 102B both sides of PMOS, be formed for the groove 106 of deposit Germanium silicon, as shown in Figure 1 C.
In dry process of carving, the hard mask 103B of dummy grid in PMOS district is etched away a part, has formed the hard mask 103B ' of the dummy grid after etching; The germanium silicon shielding layer 105B in PMOS district is etched away a part simultaneously, has formed interim side wall layer 105B ', as shown in Figure 1 C in the both sides of the dummy grid 102B of PMOS.Now, there is difference at the part 105A in territory, nmos area with at the thickness of the part 105B ' in PMOS region (being interim side wall 105B ') in germanium silicon shielding layer, difference has also appearred in the thickness of the hard mask 103A of dummy grid of nmos area and the hard mask 103B ' of dummy grid in PMOS district.That is, the hard mask of germanium silicon shielding layer and dummy grid has occurred unbalanced in the distribution in NMOS and PMOS region.
Step 4: carry out wet etching to form the groove 106 ' of Sigma type, the depositing operation that then carries out germanium silicon forms germanium silicon layer 107 in groove 105 ', as shown in Fig. 1 D.Wherein, in carrying out the process of wet etching (generally adopting TMAH), the interim side wall 105B ' of PMOS and hard mask 103B ' are all further etched, and have formed the interim side wall 104B after further etching " and hard mask 103B ", as shown in Fig. 1 D.
Now, germanium silicon shielding layer is at the part 105A in territory, nmos area with at the part 105B in PMOS region " difference in thickness further aggravate; the hard mask 103A of dummy grid of nmos area and the hard mask 103A of dummy grid in PMOS district " also further aggravation of difference in thickness, as shown in Fig. 1 D.That is, the hard mask of germanium silicon shielding layer and dummy grid is in the further aggravation of uneven thickness weighing apparatus in NMOS and PMOS region.
After completing steps 4, about the removal of germanium silicon shielding layer, prior art has two kinds of different schemes conventionally.Be respectively: scheme one, (after being step 4), remove immediately germanium silicon shielding layer forming germanium silicon layer; Scheme two, germanium silicon shielding layer are retained a part as sidewall (interim side wall) until be removed in follow-up SPT technique.Particularly, in scheme one, after completing steps 4, comprise successively as follow-up step 1: step 5-1, remove germanium silicon shielding layer; Step 6-1, formation side wall (or claiming master wall); Step 7-1, formation source-drain electrode; Step 8-1, metallization process and stress close on technology (SPT); Step 9-1, formation ILD and metal gates; Step 10-1, formation contact hole and metal level.In scheme two, after completing steps 4, comprise successively as follow-up step 1: step 5-2, form side wall (or claiming master wall); Step 6-2, formation source-drain electrode; Step 7-2, metallization grid form technique; Step 8-2, stress close on the part germanium silicon shielding layer that technology (SPT) is removed final residual simultaneously; Step 9-2, formation ILD and metal gates; Step 10-2, formation contact hole and metal level.
Due to after completing steps 4, the hard mask of germanium silicon shielding layer and dummy grid is unbalanced in the thickness distribution in nmos area and PMOS district, therefore, and in step 5-1 and step 8-2, while removing germanium silicon shielding layer, all can occur aforesaid because mistake carving technology amount is excessive or too small cause bad.Specific as follows:
In scheme one:
Step 5-1 comprises: carry out dry etching to remove the germanium silicon shielding layer 105A of nmos area, the germanium silicon shielding layer 105B in PMOS district " the hard mask 103B of dummy grid in the hard mask 103He PMOS of the dummy grid district of (interim side wall), nmos area ".
Because the thickness of the germanium silicon shielding layer 105A of nmos area is greater than the germanium silicon shielding layer 105B in PMOS district ", therefore, must carry out quarter (the germanium silicon shielding layer 105B in PMOS district relatively ") to remove the germanium silicon shielding layer 105A of nmos area completely.
If the technique amount of spending quarter very little, can cause the residual 1051A that forms germanium silicon shielding layer on the skew sidewall 104A of NMOS, as shown in Fig. 1 E.The residual 1051A of germanium silicon shielding layer forms the side wall to follow-up the processing steps such as (step 6-1), source-drain electrode formation (step 7-1) and impacts, and will be easy to cause device bad.
If it is excessive to cross the technique amount of carving, can be to the hard mask 103B of the dummy grid of PMOS ", flank HeAA district, dummy grid top damages, and forms dummy grid top flank defect 1081 HeAA district defects 1091, as shown in Fig. 1 F.And flank defect 1081 HeAA district defects 1091 in dummy grid top can cause nickle silicide in follow-up metallization process (step 7-2) in the improper deposition of defective locations, to cause device performance decline or device bad.In high-K metal grid technology, NiSi all can not grow on the dummy grid of NMOS and PMOS.Especially for PMOS, the technique of prior art is very risky.
In scheme two:
Step 8-2 generally comprises: by stress, closes on technology (SPT) and carries out wet etching to remove germanium silicon shielding layer 105A, the hard mask 103 of dummy grid, the skew sidewall 104A of nmos area, and the germanium silicon shielding layer 105B in PMOS district " (interim side wall), the hard mask 103B of dummy grid " and skew sidewall 104B.If formed other side wall layer (such as master wall), also needed to remove in the lump.
Because the thickness of the germanium silicon shielding layer 105A of nmos area is greater than the germanium silicon shielding layer 105B in PMOS district "; the thickness of the hard mask 103A of dummy grid is greater than the hard mask 103B of dummy grid ", therefore, must carry out quarter (the germanium silicon shielding layer 104B in PMOS district relatively " and the hard mask 103B of dummy grid ") to remove germanium silicon shielding layer 105A and the hard mask 103A of dummy grid of nmos area completely.Those skilled in the art are appreciated that owing to also there are other steps before step 8-2, after step 4, therefore, in step 8-2, may there is variation in the germanium silicon shielding layer of nmos area and the pattern of the hard mask of dummy grid, be no longer the pattern of 105A and 103A, do not repeat herein.
If cross the technique amount of carving very little, can cause the residual 1031A of the hard mask of dummy grid of nmos area and side wall layer residual (be generally the residual of skew sidewall, or, skew sidewall and germanium silicon shielding layer residual) 1041A, as shown in Figure 1 G.The residual 1031A of the hard mask of dummy grid can cause in follow-up ILD CMP technique, needing to carry out more to cross polishing, and then can cause the height of metal gates to reduce; The residual 1041A of side wall layer can impact the follow-up processing steps such as ILD formation, and even device is bad easily to cause device performance to decline.
If it is excessive to cross the technique amount of carving, can damage sidewall and the top of PMOS AA district and dummy grid 102B, form dummy grid defect 1082 HeAA district defects 1092, as shown in Fig. 1 H.And dummy grid defect 1082 HeAA district defects 1092 can cause the middle nickle silicide of follow-up metallization process (step 7-2) in the improper deposition of defective locations, even device is bad to cause device performance to decline.In high-K metal grid technology, NiSi all can not grow on the dummy grid of NMOS and PMOS.Especially for PMOS, the technique of prior art is very risky.
As can be seen here, in the manufacture method of existing semiconductor device, due to germanium silicon shielding layer and the hard mask of the dummy grid uneven thickness weighing apparatus problem in territory, nmos area and PMOS region, caused crossing carving technology amount excessive or too smallly all will be easy to cause the bad of device.Therefore,, in order to improve device performance and yield, the germanium silicon shielding layer before removing technique and the hard mask of dummy grid, in the uneven thickness weighing apparatus problem in territory, nmos area and PMOS region, are technical problems urgently to be resolved hurrily.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising:
Step S101: Semiconductor substrate is provided, and described Semiconductor substrate comprises the hard mask of dummy grid, dummy grid that is positioned at nmos area and the hard mask of dummy grid, dummy grid that is positioned at PMOS district;
Step S102: form germanium silicon shielding layer in described Semiconductor substrate, described germanium silicon shielding layer comprises the germanium silicon shielding layer of nmos area and the germanium silicon shielding layer in PMOS district;
Step S103: form the photoresist of patterning above the germanium silicon shielding layer of described nmos area, territory, described nmos area is completely by described photoresist covering protection; The described photoresist of take forms interim side wall as mask carries out etching to the germanium silicon shielding layer in described PMOS district with the outside of the dummy grid in described PMOS district;
Step S104: described in etching, Semiconductor substrate forms groove with the both sides of the dummy grid in described PMOS district;
Step S105: described Semiconductor substrate is carried out to wet etching processing;
Step S106: form germanium silicon layer in described groove;
Step S107: the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid are carried out to etching processing, form interim side wall with the outside of the dummy grid in described nmos area; The interim side wall of described nmos area is consistent respectively with the interim side wall in described PMOS district and the thickness of the hard mask of dummy grid with the hard mask of dummy grid.
Preferably, the hard mask of dummy grid in the hard mask of the dummy grid of described nmos area, described PMOS district is silicon nitride; The material of described germanium silicon shielding layer is silicon nitride, or silica and silicon nitride (particularly, silicon nitride is upper, and silicon nitride is main body, and thickness is thicker, and silica only for protecting the silicon nitride of offset side wall when germanium silicon shielding layer wet method is removed); And the consistency of thickness of the hard mask of dummy grid in the hard mask of the dummy grid of the described nmos area in described step S101 and described PMOS district.
Preferably, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is greater than the thickness of the interim side wall in described PMOS district forming in described step S103.
Further, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is
the thickness of the described germanium silicon shielding layer forming in described step S102 is
Wherein, in described step S101, the dummy grid in the dummy grid of described nmos area and described PMOS district is polysilicon or amorphous silicon material.
Preferably, in described step S102, the method for described formation germanium silicon shielding layer is: in described Semiconductor substrate, form one deck silicon nitride film, or form thin silicon oxide film and the thicker silicon nitride film of one deck of one deck.
Further, the method that forms described silicon nitride film comprises: hot-forming method, chemical vapour deposition technique or atomic layer deposition method.
Preferably; in described step S103; the method that forms the photoresist of patterning above the germanium silicon shielding layer of described nmos area is: in described Semiconductor substrate, apply one deck photoresist film; utilize after mask board to explosure, development; the photoresist that forms one deck patterning above the germanium silicon shielding layer of described nmos area, described nmos area is completely by described photoresist covering protection.
Preferably, in described step S106, the method that forms germanium silicon layer is epitaxial growth technology.
Preferably, described epitaxial growth technology is a kind of in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical vapour deposition, rapid heat chemical vapour deposition and molecular beam epitaxy.
Preferably, described step S107 comprises:
Above the germanium silicon shielding layer in described PMOS district, form another photoresist of patterning;
Utilizing described another photoresist is mask, and the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid are carried out to etching processing.
Further; in described step S107; the method that forms another photoresist of patterning above the germanium silicon shielding layer in described PMOS district is: in described Semiconductor substrate, apply one deck photoresist film; utilize after another mask board to explosure, development; another photoresist that forms one deck patterning above the germanium silicon shielding layer in described PMOS district, described PMOS district is completely by described another photoresist institute covering protection.
Further, in described step S107, the method for exposing is: adopt KrF photoetching equipment expose or adopt argon fluoride photoetching equipment to expose.
Preferably, described another photoresist of the patterning forming in described step S107, with the described photoresist forming in described step S103, the position in described Semiconductor substrate exists overlapping.
Further, the width of described photoresist and the overlapping region of described another photoresist in described Semiconductor substrate is 20-35nm.
The method of preferably, in described step S107, the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid being carried out to etching processing is dry etching.
Preferably, between described step S101 and described S102, also comprise the step of carrying out light dope processing.
Further, after described step S107, also comprise step S108: remove the interim side wall of described nmos area and the interim side wall in described PMOS district.
Preferably, in described step S108, removing the described interim side wall of nmos area and the method for the interim side wall in described PMOS district is wet etching.
Preferably, in described step S108, the etching liquid that described wet etching is used is phosphoric acid.
Further, after described step S108, also comprise step S109: the master wall in the formation nmos area, outside of the dummy grid of described nmos area, forms the master wall in PMOS district in the outside of the dummy grid in described PMOS district.
Further, after described step S109, also comprise step S110: in described Semiconductor substrate, carry out heavy ion doping to form the source-drain electrode of described NMOS and PMOS.
Further, after described step S110, also comprise step S111: on described source-drain electrode, form metal silicide.
Further, after described step S111, also comprise step S112: described Semiconductor substrate is carried out to stress and close on technical finesse.
Further, after described step S112, also comprise the step that forms metal gates.
The present invention is by increasing extra technique of the germanium silicon shielding layer of nmos area and the hard mask of dummy grid being carried out to etching processing, the hard mask of germanium silicon shielding layer and dummy grid is reached unanimity at the thickness in territory, nmos area and PMOS region, the front germanium silicon shielding layer of removal technique and the hard mask of dummy grid have been solved in the uneven thickness weighing apparatus problem in territory, nmos area and PMOS region, can be in the situation that do not need the very large removal that carving technology amount realizes germanium silicon shielding layer and the hard mask of dummy grid of crossing, avoided the hard mask of dummy grid of NMOS residual, the dummy grid defect in the residual and PMOS district of side wall layer, AA district defect and the undesired nickle silicide growth of dummy grid upper end flank etc. are bad, performance and the yield of device have been improved.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 H is the schematic cross sectional view of each step of manufacture method of semiconductor device in prior art;
Fig. 2 A-Fig. 2 J is the schematic cross sectional view of each step of manufacture method of the semiconductor device that proposes of the present invention;
Fig. 3 is the flow chart of the manufacture method of a kind of semiconductor device of proposing of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the manufacture method of the semiconductor device that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Below, the detailed step of an illustrative methods of manufacture method of the semiconductor device that the present invention proposes is described with reference to Fig. 2 A-Fig. 2 J and Fig. 3.The method is for the manufacture method of the semiconductor device of application high-k/metal gate technology, for improving device performance and yield.
With reference to Fig. 2 A-Fig. 2 J, wherein show the schematic cross sectional view of each step of the manufacture method of the semiconductor device that the present invention proposes.
Step S201: Semiconductor substrate is provided.
This Semiconductor substrate 200 comprises territory, nmos area and PMOS region, and in Semiconductor substrate, be formed with the hard mask 203A of dummy grid 202A, dummy grid and the skew sidewall 204A that are positioned at nmos area, be positioned at the hard mask 203B of grid 202B, dummy grid and the skew sidewall 204B in PMOS district, as shown in Figure 2 A.Wherein, the dummy grid 202A of nmos area and the dummy grid 202B in PMOS district can be referred to as dummy grid, and their material is generally polysilicon.The hard mask 203A of dummy grid of nmos area and the hard mask 203B of dummy grid in PMOS district are referred to as the hard mask of dummy grid, the two consistency of thickness, and their material is preferably silicon nitride.The skew sidewall 204B in the skew sidewall 204A of nmos area and PMOS district is referred to as skew sidewall; the two consistency of thickness; skew sidewall can be one deck silicon nitride film; also can be the composite membrane of sull and silicon nitride film composition; the present embodiment is preferably the composite membrane that the main body silicon nitride film of sull as thin as a wafer and thickening forms, and silicon oxide film is not as thin as a wafer only for removed except germanium silicon shielding layer silicon nitride protection skew sidewall silicon nitride at wet etching etching off simultaneously.The embodiment of the present invention is the manufacture method of the semiconductor device of application high-k/metal gate technology, in the method, dummy grid is only in the processing procedure of semiconductor device, to occupy the position of grid temporarily, can be removed, and substituted by the real metal gates as grid in subsequent technique.
As example, in the present embodiment, described Semiconductor substrate selects single crystal silicon material to form.In described Semiconductor substrate, be formed with isolation structure 201(as shown in Figure 2 A), described isolation structure be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, described isolation structure is divided into NMOS part and PMOS part by Semiconductor substrate.In described Semiconductor substrate 200, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure is had the knack of by those skilled in the art, at this, is described no longer in detail.
Step S202: form one deck germanium silicon shielding layer in Semiconductor substrate.
In Semiconductor substrate 200, form one deck germanium silicon shielding layer 205, this germanium silicon shielding layer comprises germanium silicon shielding layer (being the part that germanium silicon shielding layer is positioned at territory, the nmos area) 205A of nmos area and germanium silicon shielding layer (being the part that germanium silicon shielding layer the is positioned at PMOS region) 205B in PMOS district, as shown in Figure 2 B.Wherein, germanium silicon shielding layer 205 can be single layer structure, such as being silicon nitride (SiN) film, can be also sandwich construction, such as being the composite membrane of silicon nitride film and sull composition.The composite membrane that the present embodiment preferably adopts the main body silicon nitride film of sull as thin as a wafer and thickening to form, silicon oxide film is not as thin as a wafer only for removed except germanium silicon shielding layer silicon nitride protection skew sidewall silicon nitride at wet etching etching off simultaneously.The material of main part of germanium silicon shielding layer 205 is silicon nitride, with the material identical (being silicon nitride) of the hard mask 203A of dummy grid and 203B, is convenient to subsequent technique they are removed in the lump.
Wherein, the method for formation germanium silicon shielding layer 205 can be: in described Semiconductor substrate, form one deck silicon nitride film.The method that forms described silicon nitride film comprises: hot-forming method, chemical vapour deposition technique or atomic layer deposition method.
Preferably, in the embodiment of the present invention, the hard mask of dummy grid and germanium silicon shielding layer are silicon nitride material, and the thickness of the hard mask of dummy grid is greater than the thickness of germanium silicon shielding layer, the consistency of thickness of the hard mask 203B of dummy grid in the hard mask 203A of the dummy grid of nmos area and PMOS district and thickness are greater than the thickness of germanium silicon shielding layer 205.Its object is in order to protect better dummy grid, prevents dummy grid of the prior art top flank defect.Further, in embodiments of the present invention, the thickness of the hard mask of dummy grid can be set to
the thickness of germanium silicon shielding layer 205 can be set to
Wherein, in embodiments of the present invention, between step S201 and S202, can also comprise and carry out the step that light dope (LDD) is processed, to prevent short-channel effect.In embodiments of the present invention, if do not carry out light dope (LDD) treatment process,, in step S201, in described Semiconductor substrate 200, can not form the skew sidewall 204A of nmos area and the skew sidewall 204B in PMOS district.It will be appreciated by those skilled in the art that, if do not form skew sidewall 204A and 204B in step S201, follow-up other steps also can not relate to the problems such as removal of skew sidewall 204A and 204B, each layer of structure (such as interim side wall) that is directly formed at skew sidewall 204A and 204B outside can directly be formed at the outside of dummy grid, below repeats no more.
Step S203: form the photoresist of one deck patterning above the germanium silicon shielding layer of nmos area, germanium silicon shielding layer is carried out to the interim side wall that dry etching forms PMOS.
Particularly, step S203 comprises:
First, in Semiconductor substrate, apply one deck photoresist film, after then utilizing mask board to explosure, developing, above the germanium silicon shielding layer 205A of nmos area, form the photoresist 800A of one deck patterning, as shown in Figure 2 C.The photoresist 800A of this patterning is positioned at the part 205A in territory, nmos area for the protection of germanium silicon shielding layer.The method of wherein, photoresist film being exposed can be for adopting KrF (KrF) photoetching equipment or argon fluoride (ArF) photoetching equipment to expose.
Then, to the germanium silicon shielding layer in PMOS district (being the part that germanium silicon shielding layer is positioned at PMOS region), 205B carries out dry etching, etch away part above the hard mask 203B of the dummy grid in PMOS district of germanium silicon shielding layer 205B in PMOS district and the part between dummy grid 202B, outside at skew sidewall 204B forms interim side wall 205B ', as shown in Figure 2 C.Wherein, the thickness of the hard mask of dummy grid of the described nmos area in step S201 and the hard mask of dummy grid in described PMOS district; be greater than the thickness of the interim side wall in described PMOS district forming in described step S103; to protect better dummy grid, prevent dummy grid of the prior art top flank defect.
Step S204: the dummy grid both sides in PMOS region form groove
Carry out dry etching, in the both sides of the dummy grid 202B in Semiconductor substrate 200Shang PMOS district, etch the groove 206 for deposit Germanium silicon layer, this groove is similar bowl-shape, as shown in Figure 2 C.
In step S204, carrying out dry etching to form in the process of groove 206, the hard mask 203B of dummy grid can be etched to a certain extent, forms the hard mask 203B ' of dummy grid after etching, as shown in Figure 2 C.
Through abovementioned steps S203 and S204, there is difference at the part 205A in territory, nmos area with at the thickness of the part 205B ' in PMOS region (being interim side wall 205B ') in germanium silicon shielding layer, difference has also appearred in the thickness of the hard mask 203A of dummy grid of nmos area and the hard mask 203B ' of dummy grid in PMOS district.That is, there is the phenomenon of uneven thickness weighing apparatus in germanium silicon shielding layer 205 and the distribution of the hard mask of dummy grid in NMOS and PMOS region, as shown in Figure 2 C.
Step S205: carry out wet etching processing.
Carry out wet etching treatment, use TMAH etc. are as etching liquid.By wet etching, can improve the shape of groove 206, such as the similar bowl-shape groove 206 that abovementioned steps etching is formed is etched into similar orthohexagonal shape 206 ', so that the deposition of the germanium silicon of follow-up germanium silicon technology, as shown in Figure 2 D.For the photoresist 800A of nmos area, can before carrying out, this step remove, also can after completing this step, remove, can also row removal again after completing this step and completing follow-up germanium silicon-containing layer deposition technique.
In this step, in wet etching process, the interim sidewall 205B ' in PMOS district (being the germanium silicon shielding layer in PMOS district) and the hard mask 203B ' of dummy grid will further be etched, and form interim sidewall (being the germanium silicon shielding layer in the PMOS district) 205B after being further etched " and the hard mask 203B of dummy grid ".If removed photoresist 800A before this step, the part 204A that germanium silicon shielding layer is positioned at territory, nmos area also can be etched to a certain extent, and the present embodiment be take and described as example at follow-up removal photoresist 800A, as shown in Figure 2 D.
Through this step, the hard mask of germanium silicon shielding layer and dummy grid is further aggravated in the uneven thickness weighing apparatus phenomenon in NMOS and PMOS region, as shown in Figure 2 D.
Step S206: form germanium silicon layer in groove.
In groove 206 ', form germanium silicon layer 207, as shown in Figure 2 D.The method that forms germanium silicon layer 207 can adopt epitaxial growth technology.Described epitaxial growth technology can adopt a kind of in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high vacuum chemical vapour deposition (UHVCVD), rapid heat chemical vapour deposition (RTCVD) and molecular beam epitaxy (MBE).
Step S207: the germanium silicon shielding layer of nmos area and the hard mask of dummy grid are carried out to etching processing, both sides (being specially the outside of skew sidewall) with the dummy grid in described nmos area form interim side wall, and the interim side wall of described nmos area is consistent respectively with the interim side wall in PMOS district and the thickness of the hard mask of dummy grid with the hard mask of dummy grid.The method of wherein, carrying out etching processing is preferably dry etching.
Wherein, the interim side wall of nmos area (being the germanium silicon shielding layer of nmos area) is consistent respectively with the interim side wall (being the germanium silicon shielding layer in PMOS district) in PMOS district and the thickness of the hard mask of dummy grid with the hard mask of dummy grid, refer to that the interim side wall of nmos area and the interim side wall thicknesses in PMOS district are consistent, the hard mask of dummy grid of nmos area is consistent with the hard mask thicknesses of dummy grid in PMOS district.That is, germanium silicon shielding layer is balanced in the thickness distribution in territory, nmos area and PMOS region, and the hard mask of dummy grid is balanced in the thickness distribution in nmos area and PMOS district.
Particularly, step S207 can comprise the steps:
First, the germanium silicon shielding layer 205B in PMOS district " top of (being the part that germanium silicon layer is positioned at PMOS region) forms another photoresist 800B of one deck patterning, as shown in Figure 2 E.It should be noted that, the photoresist 800A before forming was removed before this step, and the time of its removal can, for one of three kinds of situations described in abovementioned steps S205, not repeat herein.
Particularly, the method that forms another photoresist 800B of patterning is: in Semiconductor substrate, apply one deck photoresist film, then, after utilizing mask board to explosure, developing, at germanium silicon shielding layer, be positioned at another photoresist 800B that forms one deck patterning on the part in PMOS region.The photoresist 800B of this patterning is for the protection of the germanium silicon shielding layer 205B in PMOS district ".The method of wherein, photoresist film being exposed can be for adopting KrF (KrF) or argon fluoride (ArF) to expose.The mask plate that this step is used is contrary with the tone (tone) of the mask plate that the photoresist 800A of abovementioned steps formation patterning is used.
Preferably, there is overlapping (overlap) in the position of the photoresist 800A that makes the patterning that forms in the photoresist 800B of patterning and abovementioned steps S203 in Semiconductor substrate 200, to avoid the relevant position (such as AA district) of Semiconductor substrate 200 to be repeated etching.Further preferably, can photoresist 800B and the width of the overlapping region of photoresist 800A in Semiconductor substrate 200 be set to 20-35nm.
Then, utilize photoresist 800B for mask, the germanium silicon shielding layer 205A of nmos area and the hard mask 203A of dummy grid are carried out to etching processing, in the both sides of the dummy grid 202A of described nmos area (being specially the both sides of skew sidewall 204A), form interim side wall 205A "; make the interim side wall 205A of described nmos area " with the interim side wall 205B in PMOS district " consistency of thickness; the hard mask 203A of dummy grid of the nmos area after etching " with the hard mask 203B of dummy grid in PMOS district " consistency of thickness, as shown in Figure 2 F.In this step, after etching processing completes, also comprise the step of removing photoresist 800B.After etching processing completes and remove photoresist 800B, the figure of formation as shown in Figure 2 F.If be provided with overlapping (overlap) of photoresist, generally can form at overlapping region residual (silicon nitride residue) of germanium silicon shielding layer, but this residually can not cause negative effect to product processing procedure, and this residual meeting is removed in follow-up ILDCMP technique.
Wherein, described etching processing can adopt dry mode of carving.Particularly, the dry etching condition of carving can be consistent with traditional handicraft, such as using CF
4, CHF
3, O
2, as etching gas, set their flow velocitys and be followed successively by 0-30sccm, 0-20sccm, 8-20sccm and 30-100sccm with Ar, pressure is 0-10mtor, and bias voltage is 100-300V.And, CH
2f
2, CO
2, the gases such as CO also can be used.For another example: use CH
3f, He and O
2as etching gas, set their flow velocitys and be followed successively by 100-300sccm, 100-300sccm and 100-200sccm, pressure position 20-60mtor, bias voltage is 150-200V.For concrete etch technological condition, at this, do not limit.When forming the hard mask of dummy grid and germanium silicon shielding layer with silicon nitride at first, if the thickness of the hard mask of dummy grid is set to as previously mentioned
the thickness of germanium silicon shielding layer 205 is set to
so, through after this step, the interim side wall 205A of nmos area " with the interim side wall 205B in PMOS district " thickness is approximately
Through this step, germanium silicon shielding layer and the hard mask of dummy grid have been realized at the thickness equiblibrium mass distribution in territory, nmos area and PMOS region.
Those skilled in the art will appreciate that this step S207 can be applied in the technologies such as " front germanium silicon (Early SiGe) ", " middle germanium silicon (Middle SiGe) ", " front germanium silicon (Late SiGe) ".
So far, the manufacture method of the semiconductor device of the embodiment of the present invention, by the germanium silicon shielding layer to nmos area and the hard mask of dummy grid, carry out the technique of etching processing, the hard mask of germanium silicon shielding layer and dummy grid is reached unanimity at the thickness in territory, nmos area and PMOS region, the front germanium silicon shielding layer of removal technique and the hard mask of dummy grid have been solved in the uneven thickness weighing apparatus problem in territory, nmos area and PMOS region, therefore can avoid the hard mask of dummy grid of the nmos area that occurs in prior art residual, the dummy grid defect HeAA district defect in the residual and PMOS district of side wall layer etc. is bad, performance and the yield of device have been improved.
After completing steps S207, subsequent step can be selected the two schemes of the removal about germanium silicon shielding layer of mentioning in background technology according to actual needs, take that after forming germanium silicon layer, to remove immediately germanium silicon shielding layer (scheme one in background technology) be example below, the subsequent step of the embodiment of the present invention is carried out to brief description.Those skilled in the art will appreciate that subsequent step of the present invention is not as limit, on the contrary, the technical scheme of all application of aforementioned steps (such as the scheme of mentioning two in background technology), all belongs to the protection range of the embodiment of the present invention.
In embodiments of the present invention, after step S207, proceed following processing step:
Step S208: the interim side wall 205A that removes described nmos area " with the interim side wall 205B in PMOS district ".
Utilize wet etching, adopt phosphoric acid (H
3pO
4) or other suitable etching liquids, Semiconductor substrate 200 is carried out to etching processing, remove the interim side wall 205A that is positioned at nmos area " and the interim side wall 205B in PMOS district ", retain and be offset sidewall 204A and 204B, the figure forming after etching, as shown in Figure 2 G.In this step, the hard mask 203A of dummy grid of nmos area " with the hard mask 203B of dummy grid in PMOS district " also can be further etched (etching degree is close), for statement convenience, the hard mask 203A of not shown dummy grid in Fig. 2 G " and 203B " associated change.
Because step S207 has removed a part by the germanium silicon shielding layer of nmos area and the hard mask of dummy grid, germanium silicon shielding layer and the hard mask of dummy grid have been realized at the thickness equiblibrium mass distribution in territory, nmos area and PMOS region, therefore, in this step, when wet etching, there is enough large process window (process window), can remove well germanium silicon shielding layer (interim side wall), and there will not be in prior art due to cross that carving technology amount is too small or the excessive nmos area germanium silicon shielding layer causing (interim side wall) is residual or flank defect HeAA district, the dummy grid top defect in PMOS district etc. bad, especially can not cause the dummy grid top flank defect in PMOS district, can not impact subsequent technique (especially metallization forms the technique of NiSi), performance and the yield of device are to a certain degree being provided.
Step S209: the outside at skew sidewall forms master wall.
Outside at skew sidewall forms master wall, and particularly, the master wall 208A in the formation nmos area, outside of the skew sidewall 204A of nmos area, forms the master wall 208B in PMOS district, as shown in Fig. 2 H in the outside of the skew sidewall 204B in PMOS district.The master wall 208B in the master wall 208A of nmos area and PMOS district has formed the master wall of semiconductor device jointly, and the two preferred thickness is consistent.Master wall 208A and master wall 208B can be also sandwich construction (such as the composite membrane of sull and silicon nitride film composition) for single layer structure (such as silicon nitride film); Preferably, master wall 208A and master wall 208B are silicon nitride film.
Step S210: carry out heavy ion doping to form the source-drain electrode of NMOS and PMOS in Semiconductor substrate.
After step S209, generally comprise and carry out the step that heavy ion doping forms the source-drain electrode of NMOS and PMOS.This step is identical with traditional handicraft, not superfluous herein.Due to abovementioned steps, having realized the perfection of germanium silicon shielding layer removes, and then the side wall layer consisting of skew sidewall and master wall is at the consistency of thickness in territory, nmos area and PMOS region, therefore, the ion doping step that forms source-drain electrode is more consistent, and then the device property of the NMOS forming and PMOS is more consistent, thereby make device performance obtain certain raising.
Step S211, on source-drain electrode, form metal silicide.
By forming the processing steps such as self aligned polycide shielding layer (SAB), etching, prerinse, metal level deposition, heat treatment, on source-drain electrode, form metal silicide (NiSi) 209, as shown in Fig. 2 I.The step that forms metal silicide, can adopt method of the prior art, does not repeat herein.
Due to aforementioned germanium silicon shielding layer and the hard mask of dummy grid that has formed consistency of thickness, therefore, when follow-up removal germanium silicon shielding layer, the defect in dummy grid 202B HeAA district that can not produce PMOS is bad, thereby in this step, can be at top and side and the AA district generation metal silicide (NiSi) of dummy grid 202B, as shown in Fig. 2 I.That is, there will not be of the prior art badly, with respect to prior art, improved device performance and yield.
It should be noted that, when when forming the hard mask of dummy grid and germanium silicon shielding layer with silicon nitride at first, if the thickness of the hard mask of dummy grid is set to as previously mentioned
the thickness of germanium silicon shielding layer 205 is set to
so, through before this step, the hard mask 203A of the dummy grid of nmos area " with the hard mask 203B of dummy grid in PMOS district " thickness is approximately
Step S212, described Semiconductor substrate carried out to stress close on technical finesse, and remove skew sidewall 204A, master wall 208A and the hard mask 203A of dummy grid of nmos area " and skew sidewall 204B, master wall 208B and the hard mask 203B of dummy grid in PMOS district ".
In order to improve device performance, described Semiconductor substrate is carried out to stress and close on technology (SPT) processing; Then, by etching technics, remove in the lump skew sidewall 204A, master wall 208A and the hard mask 203A of dummy grid of nmos area " and skew sidewall 204B, master wall 208B and the hard mask 203B of dummy grid in PMOS district ", the figure of formation is as shown in Fig. 2 J.Wherein, stress closes on technical finesse, can adopt conventional method of the prior art; Remove skew sidewall 204A and 204B, master wall 208A and 208B, the hard mask 203A of dummy grid " and 203B " lithographic method, can adopt dry etching or wet etching etc.Complete after this step, the external morphology of dummy grid 202A and 202B is good, does not occur defect and bad, as shown in Fig. 2 J.
After step S212, generally also comprise: the subsequent process steps such as step that form the step of contact hole etching barrier layer (CESL) and interlayer dielectric layer (ILD), the step that forms metal gates (MG), formation contact hole (CT) and metal level, to complete the manufacture of whole semiconductor device, these steps are identical with the manufacture method of traditional semiconductor device, repeat no more herein.
Those skilled in the art will appreciate that in embodiments of the present invention, remove the step (being step S208) of germanium silicon shielding layer (being interim side wall), after also can being placed on and carrying out SPT, then remove together skew sidewall, interim side wall and master space sidewall.Also can adopt other modes to carry out; as long as comprise that the technique that the germanium silicon shielding layer of nmos area and the hard mask of dummy grid are carried out to etching processing makes the manufacture method of the semiconductor device of the processing step that germanium silicon shielding layer and the thickness of the hard mask of dummy grid in territory, nmos area and PMOS region reaches unanimity, and all belongs to the scope of protection of the invention.About specific implementation, with the embodiment of the present invention, be not limited, do not repeat one by one herein.
The manufacture method of the semiconductor device of the embodiment of the present invention, by increasing extra step of the germanium silicon shielding layer of nmos area and the hard mask of dummy grid being carried out to etching processing, the hard mask of germanium silicon shielding layer and dummy grid is reached unanimity at the thickness in territory, nmos area and PMOS region, the front germanium silicon shielding layer of removal technique and the hard mask of dummy grid have been solved in the unbalanced problem of thickness distribution in territory, nmos area and PMOS region, can be in the situation that do not need the very large good removal that carving technology amount realizes germanium silicon shielding layer and the hard mask of dummy grid of crossing, avoided the hard mask of dummy grid of the nmos area that occurs in prior art residual, the dummy grid defect HeAA district defect in the residual and PMOS district of side wall layer etc. is bad, performance and the yield of device have been improved.
With reference to Fig. 3, wherein show the flow chart of a kind of typical method in the manufacture method of the semiconductor device that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step S101, Semiconductor substrate is provided, described Semiconductor substrate comprises the hard mask of dummy grid, dummy grid and the skew sidewall that is positioned at the hard mask of dummy grid, dummy grid of nmos area and is offset sidewall and is positioned at PMOS district;
In step S102, in described Semiconductor substrate, form germanium silicon shielding layer, described germanium silicon shielding layer comprises the germanium silicon shielding layer of nmos area and the germanium silicon shielding layer in PMOS district;
In step S103, above the germanium silicon shielding layer of described nmos area, form the photoresist of patterning, the described photoresist of take forms interim side wall as mask carries out etching to the germanium silicon shielding layer in described PMOS district with the outside of the skew sidewall in described PMOS district;
In step S104, Semiconductor substrate forms groove with the both sides of the dummy grid in described PMOS district described in etching;
In step S105, described Semiconductor substrate is carried out to wet etching processing;
In step S106, in described groove, form germanium silicon layer;
In step S107, the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid are carried out to etching processing, with the outside of the skew sidewall in described nmos area, form interim side wall; The interim side wall of described nmos area is consistent respectively with the interim side wall in described PMOS district and the thickness of the hard mask of dummy grid with the hard mask of dummy grid.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (25)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises:
Step S101: Semiconductor substrate is provided, and described Semiconductor substrate comprises the hard mask of dummy grid, dummy grid that is positioned at nmos area and the hard mask of dummy grid, dummy grid that is positioned at PMOS district;
Step S102: form germanium silicon shielding layer in described Semiconductor substrate, described germanium silicon shielding layer comprises the germanium silicon shielding layer of nmos area and the germanium silicon shielding layer in PMOS district;
Step S103: form the photoresist of patterning above the germanium silicon shielding layer of described nmos area, the described photoresist of take forms interim side wall as mask carries out etching to the germanium silicon shielding layer in described PMOS district with the outside of the dummy grid in described PMOS district;
Step S104: described in etching, Semiconductor substrate forms groove with the both sides of the dummy grid in described PMOS district;
Step S105: described Semiconductor substrate is carried out to wet etching processing;
Step S106: form germanium silicon layer in described groove;
Step S107: the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid are carried out to etching processing, form interim side wall with the outside of the dummy grid in described nmos area; The interim side wall of described nmos area is consistent respectively with the interim side wall in described PMOS district and the thickness of the hard mask of dummy grid with the hard mask of dummy grid.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the hard mask of dummy grid in the hard mask of dummy grid of described nmos area, described PMOS district is silicon nitride; The material of described germanium silicon shielding layer is silicon nitride, or is silica and silicon nitride; And the consistency of thickness of the hard mask of dummy grid in the hard mask of the dummy grid of the described nmos area in described step S101 and described PMOS district.
3. the manufacture method of semiconductor device as claimed in claim 2, it is characterized in that, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is greater than the thickness of the interim side wall in described PMOS district forming in described step S103.
4. the manufacture method of semiconductor device as claimed in claim 3, is characterized in that, the thickness of the hard mask of dummy grid of the described nmos area in described step S101 and the hard mask of dummy grid in described PMOS district is
the thickness of the described germanium silicon shielding layer forming in described step S102 is
5. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S101, the dummy grid in the dummy grid of described nmos area and described PMOS district is polysilicon or amorphous silicon material.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S102, the method for described formation germanium silicon shielding layer is: in described Semiconductor substrate, form one deck silicon nitride film, or formation one deck silica adds silicon nitride film.
7. the manufacture method of semiconductor device as claimed in claim 6, is characterized in that, the method that forms described silicon nitride film comprises: hot-forming method, chemical vapour deposition technique or atomic layer deposition method.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, in described step S103, the method that forms the photoresist of patterning above the germanium silicon shielding layer of described nmos area is: in described Semiconductor substrate, apply one deck photoresist film, after utilizing mask board to explosure, developing, above the germanium silicon shielding layer of described nmos area, form the photoresist of one deck patterning.
9. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S106, the method that forms germanium silicon layer is epitaxial growth technology.
10. the manufacture method of semiconductor device as claimed in claim 9, it is characterized in that, described epitaxial growth technology is a kind of in low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical vapour deposition, rapid heat chemical vapour deposition and molecular beam epitaxy.
The manufacture method of 11. semiconductor device as claimed in claim 1, is characterized in that, described step S107 comprises:
Above the germanium silicon shielding layer in described PMOS district, form another photoresist of patterning; Utilizing described another photoresist is mask, and the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid are carried out to etching processing.
The manufacture method of 12. semiconductor device as claimed in claim 11, it is characterized in that, in described step S107, the method that forms another photoresist of patterning above the germanium silicon shielding layer in described PMOS district is: in described Semiconductor substrate, apply one deck photoresist film, after utilizing another mask board to explosure, developing, above the germanium silicon shielding layer in described PMOS district, form another photoresist of one deck patterning.
The manufacture method of 13. semiconductor device as claimed in claim 12, is characterized in that, in described step S107, the method for exposing is: adopt KrF photoetching equipment expose or adopt argon fluoride photoetching equipment to expose.
The manufacture method of 14. semiconductor device as claimed in claim 11, it is characterized in that, described another photoresist of the patterning forming in described step S107, with the described photoresist forming in described step S103, the position in described Semiconductor substrate exists overlapping.
The manufacture method of 15. semiconductor device as claimed in claim 14, is characterized in that, the width of described photoresist and the overlapping region of described another photoresist in described Semiconductor substrate is 20-35nm.
The manufacture method of 16. semiconductor device as claimed in claim 11, is characterized in that, the method for in described step S107, the germanium silicon shielding layer of described nmos area and the hard mask of dummy grid being carried out to etching processing is dry etching.
The manufacture method of 17. semiconductor device as claimed in claim 1, is characterized in that, between described step S101 and described S102, also comprises the step of carrying out light dope processing.
The manufacture method of 18. semiconductor device as claimed in claim 1, is characterized in that, after described step S 107, also comprises step S108: remove the interim side wall of described nmos area and the interim side wall in described PMOS district.
The manufacture method of 19. semiconductor device as claimed in claim 18, is characterized in that, in described step S108, removing the described interim side wall of nmos area and the method for the interim side wall in described PMOS district is wet etching.
The manufacture method of 20. semiconductor device as claimed in claim 19, is characterized in that, in described step S108, the etching liquid that described wet etching is used is phosphoric acid.
The manufacture method of 21. semiconductor device as claimed in claim 18, it is characterized in that, after described step S108, also comprise step S109: the master wall in the formation nmos area, outside of the dummy grid of described nmos area, forms the master wall in PMOS district in the outside of the dummy grid in described PMOS district.
The manufacture method of 22. semiconductor device as claimed in claim 21, is characterized in that, also comprises step S110 after described step S109: in described Semiconductor substrate, carry out heavy ion doping to form the source-drain electrode of described NMOS and PMOS.
The manufacture method of 23. semiconductor device as claimed in claim 22, is characterized in that, also comprises step S111: on described source-drain electrode, form metal silicide after described step S110.
The manufacture method of 24. semiconductor device as claimed in claim 23, is characterized in that, also comprises step S112 after described step S111: described Semiconductor substrate is carried out to stress and close on technical finesse.
The manufacture method of 25. semiconductor device as claimed in claim 24, is characterized in that, also comprises the step that forms metal gates after described step S112.
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