CN103681330A - Fin and fin forming method - Google Patents

Fin and fin forming method Download PDF

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CN103681330A
CN103681330A CN201210332967.0A CN201210332967A CN103681330A CN 103681330 A CN103681330 A CN 103681330A CN 201210332967 A CN201210332967 A CN 201210332967A CN 103681330 A CN103681330 A CN 103681330A
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dielectric layer
fin
groove
semiconductor substrate
gradually
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CN103681330B (en
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三重野文健
周梅生
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

The invention discloses a fin and a fin forming method. The fin forming method includes the following steps: a semiconductor substrate is provided; a dielectric layer is formed on the semiconductor substrate and doped with foreign ions, and the molar concentrations of the foreign ions gradually change from the surface of the dielectric layer to the bottom of the dielectric layer; a mask layer is formed on the surface of the dielectric layer and provided with openings exposed on the surface of the dielectric layer; with the mask layer serving as a mask, the dielectric layer is etched along the openings through the isotropic etching technique to form grooves, and the dielectric layer etching rate decreases with the increasing molar concentrations of the foreign ions in the dielectric layer during the etching process; each groove is filled with an epitaxial layer which serves as the fin. The dielectric layer is doped with the foreign ions with the different molar concentrations in the thickness direction, so that when the dielectric layer is etched to form the grooves, the side walls forming the grooves are not perpendicular to the surface of the semiconductor substrate, which enlarges the surface areas of the fins formed in the grooves, and further increases driving currents passing the fins.

Description

Fin and forming method thereof
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of fin and forming method thereof
Background technology
Along with the development of semiconductor process techniques, along with process node reduces gradually, rear grid (gate-last) technique is widely applied, and obtains desirable threshold voltage, improves device performance.But the characteristic size (CD when device, while Critical Dimension) further declining, even grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and fin formula field effect transistor (Fin FET) is paid close attention to widely as alternative having obtained of conventional device.
Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, in described Semiconductor substrate 10, be formed with the fin 14 of protrusion, fin 14 is generally by obtaining after Semiconductor substrate 10 etchings; Dielectric layer 11, covers the part of the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across on described fin 14, covers top and the sidewall of described fin 14, and grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.
Manyly about fin formula field effect transistor, please refer to the patent No. for the United States Patent (USP) of " US7868380B2 ".
But the drive current of the fin formula field effect transistor of existing formation is still smaller.
Summary of the invention
The problem that the present invention solves is to provide a kind of fin and forming method thereof, has improved the drive current by fin.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of fin, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form dielectric layer, described dielectric layer is doped with foreign ion, and from the surface of dielectric layer to bottom, the molar concentration of described foreign ion gradually changes; On described dielectric layer surface, form mask layer, described mask layer has the opening that exposes dielectric layer surface; Take described mask layer as mask, along dielectric layer described in opening etching, form groove, in etching process, the etch rate of dielectric layer is increased along with the increase of the molar concentration of foreign ion in dielectric layer; In groove, fill full epitaxial loayer, described epitaxial loayer is as fin.
Optionally, described dielectric layer be silex glass doped with phosphonium ion, doped with the silex glass of boron ion, doped with the silex glass of boron phosphonium ion or doped with the silex glass of arsenic ion.
Optionally, to form technique be in-situ doped chemical vapor deposition method for described dielectric layer.
Optionally, the temperature of described in-situ doped chemical vapor deposition method is 300 ~ 500 degrees Celsius, and deposit cavity pressure is 0.2 ~ 0.5 holder, and the silicon source gas of employing is SiH 4, impurity source gas is PH 3, B 2h 6or AsH 3, other gases are O 2.
Optionally, the temperature of described in-situ doped chemical vapor deposition method is 350 ~ 550 degrees Celsius, and deposit cavity pressure is 600 holders, and the silicon source gas of employing is TEOS, and impurity source gas is TMP, TMB or TMAs, and other gases are O 3.
Optionally, while adopting in-situ doped chemical vapor deposition method to form dielectric layer, in deposition process, by regulating the flow of impurity source gas to regulate the molar concentration of the foreign ion adulterating in dielectric layer.
Optionally, along the technique of dielectric layer described in opening etching, be isotropic dry etch process, the gas that described isotropic dry etching adopts is CF 4and He, CF 4flow be 200 ~ 500sccm, the flow of He is 1 ~ 2slm, etch chamber pressure is 1 ~ 10Pa, radio-frequency power is 250 ~ 350W, the frequency of radio frequency is 13.56MHz.
Optionally, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, increases gradually, and when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove increases gradually.
Optionally, the sidewall of described groove and the angle of Semiconductor substrate are 80 ~ 85 degree.
Optionally, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, reduces gradually, and when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove reduces gradually.
Optionally, the sidewall of described groove and the angle of Semiconductor substrate are 95 ~ 100 degree.
Optionally, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, first reduce gradually, increase gradually again after reaching minimum value, when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove first reduces gradually, increases gradually after reaching minimum value again.
Optionally, the molar concentration of the foreign ion adulterating in described dielectric layer reaches minimum value in the centre position of dielectric layer, and the molar concentration of the surface of dielectric layer and the foreign ion of bottom equates.
Optionally, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, first increase gradually, reduce gradually again after reaching maximum, when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove first increases gradually, reduces gradually after reaching maximum again.
Optionally, the molar concentration of the foreign ion adulterating in described dielectric layer reaches maximum in the centre position of dielectric layer, and the molar concentration of the surface of dielectric layer and the foreign ion of bottom equates.
The embodiment of the present invention also provides a kind of fin, it is characterized in that, comprising: Semiconductor substrate; Be positioned at the some fins in described Semiconductor substrate, from the top surface of fin to bottom, the width of described fin gradually changes.
Optionally, from the top surface of fin to bottom, the width of described fin increases gradually, and the sidewall of described fin and the angle of Semiconductor substrate are 80 ~ 85 degree.
Optionally, from the top surface of fin to bottom, the width of described fin reduces gradually, and the sidewall of described fin and the angle of Semiconductor substrate are 95 ~ 100 degree.
Optionally, from the top surface of fin to bottom, the width of described fin first reduces gradually, after the centre position of fin reaches minimum value, increases gradually again.
Optionally, the width of described fin first increases gradually, after the centre position of fin reaches maximum, reduces gradually again.
Compared with prior art, technical solution of the present invention has the following advantages:
In dielectric layer, from adulterate to the bottom foreign ion of different molar concentrations of the top surface of dielectric layer, while adopting isotropic etching technics etching dielectric layer, make the etch rate of diverse location in dielectric layer (comprising lateral etching speed and longitudinal etch rate) different, the sidewall that makes to form groove is the surface non-perpendicular to Semiconductor substrate, improved the surface area of the fin forming in groove, thereby improved by the drive current of fin.
Further, from the surface of dielectric layer to bottom, the width of described groove increases gradually, the sidewall of described groove and the angle of semiconductor substrate surface are 80 ~ 85 degree, make to form the uniformity better (smooth surface) of the sidewall surfaces of groove, during follow-up formation fin, the surperficial uniformity of the sidewall of fin is better, when charge carrier is during by fin surperficial, a little less than the scattering process of charge carrier, improve the mobility of charge carrier, and when the sidewall of groove forming and the angle of Semiconductor substrate less (being less than 80 degree), the molar concentration of ion of needing to adulterate in dielectric layer is larger with the rate of change of thickness of dielectric layers, when etching dielectric layer, in dielectric layer, the rate of change of the etch rate at different-thickness place is also larger, easily make the uniformity poor (rough surface) of the sidewall surfaces of the groove that forms, during follow-up formation fin, the uniformity of the sidewall surfaces of fin is poor, and coarse sidewall surfaces is when by charge carrier, easily cause the scattering of charge carrier, reduced the mobility of charge carrier, and when the sidewall of groove forming and the angle of Semiconductor substrate are greatly when (being greater than 85 degree), can make the surface area of sidewall of the fin of follow-up formation increase less, be unfavorable for the raising of drive current.
Further, from the surface of dielectric layer to bottom, the width of described groove reduces gradually, the sidewall of described groove and the angle of semiconductor substrate surface are 95 ~ 100 degree, form the surperficial uniformity better (smooth surface) of the sidewall of groove, during follow-up formation fin, the surperficial uniformity of the sidewall of fin is better, when charge carrier is during by fin surperficial, a little less than the scattering process of charge carrier, improve the mobility of charge carrier, when the sidewall of groove and semiconductor substrate surface angle are when large (being greater than 100 degree), can make the surface uniformity of sidewall of the groove that forms poor, and when the sidewall of groove and semiconductor substrate surface angle less (be greater than 90 degree and be less than 95 degree), be unfavorable for the lifting of drive current of the fin of follow-up formation.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art fin field effect pipe;
Fig. 3 ~ Fig. 4 is the molar concentration distribution of foreign ion in embodiment of the present invention dielectric layer and the schematic diagram that is related to of thickness of dielectric layers;
Fig. 2, Fig. 5 ~ Figure 13 is the cross-sectional view of embodiment of the present invention fin forming process.
Embodiment
The fin of existing fin field effect pipe normally forms by etching semiconductor substrate, the sidewall of the fin forming is perpendicular to the surface of Semiconductor substrate, the surface area of fin (fin top surface and two side) is relatively little, formation is during across the grid structure of described fin sidewall surfaces and top surface, the width of the channel region of fin surface formation is restricted, the drive current of fin field effect pipe is difficult to improve, and the uniformity of the sidewall surfaces of the fin forming is poor, reduced by the mobility of fin sidewall surfaces charge carrier.
For addressing the above problem, inventor proposes a kind of fin and forming method thereof, the two side of described fin is not orthogonal to the surface of Semiconductor substrate, from the top surface of fin to bottom, the width of described fin gradually changes, thereby the surface area of the two side of fin is increased, when forming across the sidewall surfaces of fin and the grid structure of top surface, make the width of channel region become large, it is large that the drive current that channel region is passed through becomes.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.When the embodiment of the present invention is described in detail in detail, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
First, please refer to Fig. 2, Semiconductor substrate 300 is provided, in described Semiconductor substrate 300, form dielectric layer 400, described dielectric layer 400 is doped with foreign ion, from the surface of dielectric layer 400 to bottom, the molar concentration of described foreign ion gradually changes, and follow-up the etch rate of dielectric layer 400 is increased along with the increase of the molar concentration of foreign ion in dielectric layer 400.
Described Semiconductor substrate 300 can be silicon (Si) substrate, germanium (Ge) substrate or SiGe (GeSi) substrate, carborundum (SiC) substrate; Also can be silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate; Or can also be for other material, such as III-V compounds of group substrates such as GaAs.Semiconductor substrate described in the present embodiment 300 is silicon substrate.
Described dielectric layer 400 is silex glass (PSG) doped with phosphonium ion, doped with the silex glass (BSG) of boron ion, doped with the silex glass (BPSG) of boron phosphonium ion or doped with the silex glass (AsSG) of arsenic ion.Dielectric layer described in the present embodiment 400 is the silex glass (PSG) of Doping Phosphorus ion.
Doping Phosphorus ion in silex glass, when boron ion or arsenic ion, partial oxygen in silex glass and phosphonium ion, boron ion or arsenic ion are in conjunction with the oxide that forms phosphorus, the oxide of boron or the oxide of arsenic, in etching doped with phosphonium ion, when boron ion or arsenic ion silex glass, the oxide of phosphorus in silex glass, the oxide of boron or the oxide of arsenic can increase the etch rate to silex glass, and the molar concentration to the etch rate of silex glass along with foreign ion in silex glass increases and increases, be that in silex glass, the molar concentration of foreign ion is higher, etch rate to silex glass is higher.The embodiment of the present invention, utilize exactly the different feature of molar concentration different etching speed of the foreign ion adulterating in silex glass, in dielectric layer from the surface of dielectric layer to the adulterate foreign ion of different molar concentrations of the diverse location of bottom, when adopting isotropic dry etching dielectric layer, make etch rate (horizontal and vertical etch rate) difference of diverse location in dielectric layer, thereby make the sidewall of the groove that forms in dielectric layer there is different shapes, the follow-up epitaxial loayer of filling in groove is while forming fin, the sidewall of fin is corresponding with the sidewall of groove, increased the area of fin sidewall, while forming the grid structure across fin on the surface of fin, increased the width of channel region, improved the size of channel region drive current.
The in-situ doped chemical gaseous phase deposition technique of formation technique of described dielectric layer 400, the temperature of described in-situ doped chemical vapor deposition method is 300 ~ 500 degrees Celsius, and deposit cavity pressure is that deposit cavity pressure is 0.2 ~ 0.5 holder, and the silicon source gas of employing is SiH 4, impurity source gas is PH 3, B 2h 6or AsH 3, other gases are O2 .when form doped with boron ion silex glass (BSG) time, impurity source gas is B 2h 6; When form doped with boron phosphonium ion silex glass (BPSG) time, impurity source gas is PH 3and B 2h 6; Formation is during doped with the silex glass (AsSG) of arsenic ion, and impurity source gas is AsH 3.
In other embodiments of the invention, the silicon source gas that described in-situ doped chemical vapor deposition method adopts is TEOS(tetraethoxysilane), impurity source gas is TMP(trimethyl phosphorus or trimethoxy phosphorus), TMB(trimethyl borine or trimethoxy-boron) or TMAs(arsenic trimethide or trimethoxy arsenic), other gases are O 3, temperature is 350 ~ 550 degrees Celsius, deposit cavity pressure is 600 holders.
When carrying out in-situ doped chemical vapor deposition method, by regulating the flow of impurity source gas, make the dielectric layer 400 of formation different to the molar concentration of surface impurity ion from bottom.Please refer to Fig. 3 and Fig. 4, Fig. 3 and Fig. 4 are the molar concentration distribution of foreign ion in dielectric layer and the schematic diagram that is related to of thickness of dielectric layers.
With reference to figure 3, its cathetus B represents: from the surface of dielectric layer to bottom, the molar concentration of the foreign ion adulterating in dielectric layer is linear increase gradually, surface the closer to dielectric layer, the molar concentration of foreign ion is less, and the closer to the bottom of dielectric layer, the molar concentration of foreign ion is larger.When forming dielectric layer, the flow of impurity source gas is linear and reduces gradually, and the molar concentration that makes foreign ion reduces gradually with the increase of thickness of dielectric layers.Follow-up when etching dielectric layer forms groove, from the surface of dielectric layer to bottom, the width of described groove increases gradually.Straight line A represents: from the surface of dielectric layer to bottom, the concentration of the foreign ion adulterating in dielectric layer is linear reducing gradually, and the closer to the surface of dielectric layer, the molar concentration of foreign ion is larger, the closer to the bottom of dielectric layer, the molar concentration of foreign ion is less.Therefore, when forming dielectric layer, the flow of impurity source gas is linear and increases gradually, and the molar concentration that makes foreign ion increases gradually with the increase of thickness of dielectric layers.Follow-up when etching dielectric layer forms groove, from the surface of dielectric layer to bottom, the width of described groove reduces gradually, and the sidewall of groove and Semiconductor substrate are certain obtuse angle (referring to power 11).In other embodiments of the invention, from the surface of dielectric layer to bottom, the molar concentration of the foreign ion in described dielectric layer is nonlinear and increases gradually or reduce gradually, and the sidewall of the groove of follow-up formation is the sidewall with certain radian.
With reference to figure 4, wherein curve C represents: from the surface of dielectric layer to bottom, the molar concentration of the foreign ion adulterating in described dielectric layer, is first linear increase gradually, is linear reducing gradually after reaching maximum again.Therefore, when forming dielectric layer, the flow of described impurity source gas is first linear increase gradually, reaches after maximum, then is linear reducing gradually.Dielectric layer described in subsequent etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove first increases gradually, reduces gradually after reaching maximum again.In the present embodiment, the molar concentration of the foreign ion adulterating in described dielectric layer reaches maximum in the centre position of dielectric layer, the molar concentration of the foreign ion adulterating in the upper part of dielectric layer and lower part is symmetric with the centre position of dielectric layer, the molar concentration of the surface of dielectric layer and the foreign ion of bottom equates, make part and lower part on the groove of follow-up formation, symmetrical along the position that recess width is the widest.In other embodiments of the invention, from the surface of dielectric layer to bottom, the molar concentration of the foreign ion adulterating in described dielectric layer, is first nonlinear and increases gradually, reaches to be nonlinear after maximum again and to reduce gradually.In other embodiments of the invention, adulterate in the described dielectric layer maximum of molar concentration of ion is positioned at other positions outside dielectric layer centre position.
Wherein curve D represents: from the surface of dielectric layer to bottom, the molar concentration of the foreign ion adulterating in described dielectric layer, is first linear reducing gradually, is linear increase gradually after reaching minimum value again.Therefore, when forming dielectric layer, the flow of described impurity source gas is first linear reducing gradually, reaches after minimum value, then is linear increase gradually.Dielectric layer described in subsequent etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove first reduces gradually, increases gradually after reaching minimum value again.In the present embodiment, the molar concentration of the foreign ion adulterating in described dielectric layer reaches minimum value in the centre position of dielectric layer, the molar concentration of the foreign ion adulterating in the upper part of dielectric layer and lower part is symmetric with the centre position of dielectric layer, the molar concentration of the surface of dielectric layer and the foreign ion of bottom equates, make upper part and the lower part of the groove of follow-up formation, symmetrical along the position that recess width is the narrowest.In other embodiments of the invention, from the surface of dielectric layer to bottom, the molar concentration of the foreign ion adulterating in described dielectric layer, is first nonlinear and reduces gradually, reaches to be nonlinear after minimum value again and to increase gradually.In other embodiments of the invention, adulterate in the described dielectric layer minimum value of molar concentration of ion is positioned at other positions outside dielectric layer centre position.
Then, please refer to Fig. 5, on described dielectric layer 400 surfaces, form mask layer 401, described mask layer 401 has the some openings 402 that expose described dielectric layer 400 surfaces, and described opening 402 is corresponding with the position of the groove forming in subsequent dielectric layers 400.
The material of described mask layer 401 is photoresist or hard mask material.The width of mask layer 401 split sheds 402 is adjusted according to the top width of fin to be formed.
Then, please refer to Fig. 6, when the molar concentration (from surface to bottom) of the doping ion in dielectric layer 400 is linearity and increases gradually, along dielectric layer 400 described in opening 402 etchings, form groove 403, from the surface of dielectric layer 400 to bottom, the width of described groove 403 increases gradually, the sidewall of groove 403 and Semiconductor substrate 300 surfaces are the straight line of an inclination, the sidewall of described groove 403 and the angle of semiconductor substrate surface 10 are that 80 ~ 85 degree (it should be noted that, the sidewall of embodiments of the invention further groove and the angle of Semiconductor substrate are all angles of the Semiconductor substrate that exposes to the sidewall of groove and groove), make the uniformity better (smooth surface) of the sidewall surfaces of the groove 403 that forms, during follow-up formation fin, the surperficial uniformity of the sidewall of fin is better, when charge carrier is during by fin surperficial, a little less than the scattering process of charge carrier, improve the mobility of charge carrier, and when the sidewall of groove 403 forming and the angle of Semiconductor substrate less (being less than 80 degree), the molar concentration of ion of needing to adulterate in dielectric layer 400 is larger with the rate of change of dielectric layer 400 thickness, when etching dielectric layer 400, in dielectric layer, the rate of change of the etch rate at different-thickness place is also larger, easily make the uniformity poor (rough surface) of the sidewall surfaces of the groove 403 that forms, during follow-up formation fin, the uniformity of the sidewall surfaces of fin is poor, and coarse sidewall surfaces is when charge carrier passes through, easily cause the scattering of charge carrier, reduced the mobility of charge carrier, and when the sidewall of groove 403 forming and the angle of Semiconductor substrate are greatly when (being greater than 85 degree), can make the surface area of sidewall of the fin of follow-up formation increase less, be unfavorable for the raising of drive current.The follow-up completely epitaxial loayer of filling in groove 403, using described epitaxial loayer as fin.
Described in etching, the technique of dielectric layer 400 is isotropic dry etch process, make the horizontal etch rate of dielectric layer 400 and being consistent of etch rate longitudinally, the changing value of the etch rate of dielectric layer 400 diverse locations is also consistent, the molar concentration (from surface to bottom) of the doping ion in dielectric layer 400 is while increasing gradually, etch rate to dielectric layer 400 increases gradually, thereby the width of the groove 403 of formation in dielectric layer 400 is increased gradually.
The gas that described isotropic dry etching adopts is CF 4and He, CF 4flow be 200 ~ 500sccm(mark condition milliliter per minute), the flow of He is that 1 ~ 2slm(mark condition rises per minute), etch chamber pressure is 1 ~ 10Pa, radio-frequency power is 250 ~ 350W, the frequency of radio frequency is 13.56MHz, when subsequent etching dielectric layer 400, keep the rate of change with respect to the molar concentration of the ion that adulterates in dielectric layer 400 to the rate of change of the etch rate of dielectric layer 400 to keep linear or approach linear relation, guarantee the shape of recess sidewall and the uniformity on recess sidewall surface that form.
In another embodiment of the present invention, when in described dielectric layer 400, the molar concentration (from surface to bottom) of the foreign ion of doping is reducing gradually of linearity, please refer to Fig. 7, along dielectric layer 400 described in opening 402 etchings, form groove 403, from the surface of dielectric layer 400 to bottom, the width of described groove 403 reduces gradually, the sidewall of groove 403 and Semiconductor substrate 300 surfaces are the straight line of an inclination, the sidewall of described groove 403 and the angle of semiconductor substrate surface 20 are 95 ~ 100 degree, form the surperficial uniformity better (smooth surface) of the sidewall of groove 403, during follow-up formation fin, the surperficial uniformity of the sidewall of fin is better, when charge carrier is during by fin surperficial, a little less than the scattering process of charge carrier, improve the mobility of charge carrier, and when the sidewall of groove 403 and semiconductor substrate surface angle are when large (being greater than 100 degree), can make the surface uniformity of sidewall of the groove that forms poor, and when the sidewall of groove 403 and semiconductor substrate surface angle less (be greater than 90 degree and be less than 95 degree), be unfavorable for the lifting of drive current of the fin of follow-up formation.The follow-up completely epitaxial loayer of filling in groove 403, using described epitaxial loayer as fin.
In another embodiment of the present invention, the molar concentration of the foreign ion of doping in described dielectric layer 400, from the surface of dielectric layer 400 to bottom, first be linear reducing gradually, in the centre position of dielectric layer 400, reach after minimum value, while being again the increase gradually of linearity, please refer to Fig. 8, along dielectric layer 400 described in opening 402 etchings, form groove 403, from the surface of dielectric layer 400 to bottom, the width of described groove 403 first reduces gradually, centre position at dielectric layer 400 reaches after minimum value, then increases gradually.The angle of the extended line of the upper partial sidewall of described groove 403 and Semiconductor substrate 300 is 95 ~ 100 degree, the lower partial sidewall of described groove 403 and the angle of Semiconductor substrate 300 are 80 ~ 85 degree, make the sidewall surfaces of fin of follow-up formation long-pending larger time the uniformity of sidewall surfaces better, follow-up formation during across the top surface of fin and the grid structure of sidewall surfaces, has improved the drive current by fin.
In another embodiment of the present invention, the molar concentration of the foreign ion of doping in described dielectric layer 400, from the surface of dielectric layer 400 to bottom, first be linear increase gradually, in the centre position of dielectric layer 400, reach after maximum, be again linear while reducing gradually, please refer to Fig. 8, along dielectric layer 400 described in opening 402 etchings, form groove 403, from the surface of dielectric layer 400 to bottom, the width of described groove 403 first increases gradually, centre position at dielectric layer 400 reaches after maximum, then reduces gradually.The angle of the extended line of the upper partial sidewall of described groove 403 and Semiconductor substrate 300 is 80 ~ 85 degree, the lower partial sidewall of described groove 403 and the angle of Semiconductor substrate 300 are 95 ~ 100 degree, make the sidewall surfaces of fin of follow-up formation long-pending larger time the uniformity of sidewall surfaces better, follow-up formation during across the top surface of fin and the grid structure of sidewall surfaces, has improved the drive current by fin.
With reference to Figure 10, remove described mask layer 401(with reference to figure 6), at groove 403(with reference to figure 6) in fill full epitaxial loayer, described epitaxial loayer is as fin 404, from the top surface of fin 404 to bottom, the width of described fin 404 reduces gradually, and the angle 11 on the sidewall of described fin 404 and Semiconductor substrate 300 surfaces is 80 ~ 85 degree.
The fill process selective epitaxial process of described epitaxial loayer.The material of described epitaxial loayer is III-V compounds of group such as silicon, germanium, SiGe or GaAs.
Follow-uply also comprise: remove described dielectric layer 400, form across the top surface of described fin 400 and the grid structure of sidewall surfaces, described grid structure comprises gate dielectric layer and is positioned at the gate electrode (not shown) on gate dielectric layer surface; Source/drain region at the interior formation fin field effect of fin 400 pipe of grid structure both sides.
Because the surface area of the sidewall of fin 400 increases, the uniformity of sidewall surfaces is better, has improved the drive current of fin field effect pipe and the mobility of charge carrier.
In another embodiment of the present invention, please refer to Figure 11, remove described mask layer 401(with reference to figure 7), at groove 403(with reference to figure 7) in fill full epitaxial loayer, described epitaxial loayer is as fin 404, from the top surface of fin 404 to bottom, the width of described fin 404 increases gradually, and the angle 21 on the sidewall of described fin 404 and Semiconductor substrate 300 surfaces is 95 ~ 100 degree.
In another embodiment of the present invention, please refer to Figure 12, remove described mask layer 401(with reference to figure 8), at groove 403(with reference to figure 8) in fill full epitaxial loayer, described epitaxial loayer is as fin 404, from the top surface of fin 404 to bottom, the width of described fin 404 first reduces gradually, in centre, reach after minimum, increase gradually again, the angle of the extended line of the upper partial sidewall of described fin 404 and Semiconductor substrate 300 is 95 ~ 100 degree, and the lower partial sidewall of described fin 404 and the angle of Semiconductor substrate 300 are 80 ~ 85 degree.
In another embodiment of the present invention, please refer to Figure 13, remove described mask layer 401(with reference to figure 9), at groove 403(with reference to figure 9) in fill full epitaxial loayer, described epitaxial loayer is as fin 404, from the top surface of fin 404 to bottom, the width of described fin 404 first increases gradually, in centre, reach after maximum, reduce gradually again, the angle of the extended line of the upper partial sidewall of described fin 404 and Semiconductor substrate 300 is 80 ~ 85 degree, and the lower partial sidewall of described fin 404 and the angle of Semiconductor substrate 300 are 95 ~ 100 degree.
The fin that said method forms, comprising: Semiconductor substrate; Be positioned at the some fins in described Semiconductor substrate, from the top surface of fin to bottom, the width of described fin gradually changes.
In an embodiment, from the top surface of fin to bottom, the width of described fin increases gradually therein, and the sidewall of described fin and the angle of Semiconductor substrate are 80 ~ 85 degree.
In another embodiment, from the top surface of fin to bottom, the width of described fin reduces gradually, and the sidewall of described fin and the angle of Semiconductor substrate are 95 ~ 100 degree.
In yet another embodiment, from the top surface of fin to bottom, the width of described fin first reduces gradually, after the centre position of fin reaches minimum value, increases gradually again.
In yet another embodiment, from the top surface of fin to bottom, the width of described fin first increases gradually, after the centre position of fin reaches maximum, reduces gradually again.
To sum up, embodiment of the present invention fin and forming method thereof, in dielectric layer, from adulterate to the bottom foreign ion of different molar concentrations of the top surface of dielectric layer, while adopting isotropic etching technics etching dielectric layer, make the etch rate of diverse location in dielectric layer (comprising lateral etching speed and longitudinal etch rate) different, make to form the sidewall of groove non-perpendicular to the surface of Semiconductor substrate, improved the surface area of the fin forming in groove, thereby improved by the drive current of fin.
Further, from the surface of dielectric layer to bottom, the width of described groove increases gradually, the sidewall of described groove and the angle of semiconductor substrate surface are 80 ~ 85 degree, make to form the uniformity better (smooth surface) of the sidewall surfaces of groove, during follow-up formation fin, the surperficial uniformity of the sidewall of fin is better, when charge carrier is during by fin surperficial, a little less than the scattering process of charge carrier, improve the mobility of charge carrier, and when the sidewall of groove forming and the angle of Semiconductor substrate less (being less than 80 degree), the molar concentration of ion of needing to adulterate in dielectric layer is larger with the rate of change of thickness of dielectric layers, when etching dielectric layer, in dielectric layer, the rate of change of the etch rate at different-thickness place is also larger, easily make the uniformity poor (rough surface) of the sidewall surfaces of the groove that forms, during follow-up formation fin, the uniformity of the sidewall surfaces of fin is poor, and coarse sidewall surfaces is when by charge carrier, easily cause the scattering of charge carrier, reduced the mobility of charge carrier, and when the sidewall of groove forming and the angle of Semiconductor substrate are greatly when (being greater than 85 degree), can make the surface area of sidewall of the fin of follow-up formation increase less, be unfavorable for the raising of drive current.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (20)

1. a formation method for fin, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form dielectric layer, described dielectric layer is doped with foreign ion, and from the surface of dielectric layer to bottom, the molar concentration of described foreign ion gradually changes;
On described dielectric layer surface, form mask layer, described mask layer has the opening that exposes dielectric layer surface;
Take described mask layer as mask, adopt isotropic etching technics along dielectric layer described in opening etching, form groove, in etching process, the etch rate of dielectric layer is increased along with the increase of the molar concentration of foreign ion in dielectric layer;
In groove, fill full epitaxial loayer, described epitaxial loayer is as fin.
2. the formation method of fin as claimed in claim 1, is characterized in that, described dielectric layer is silex glass doped with phosphonium ion, doped with the silex glass of boron ion, doped with the silex glass of boron phosphonium ion or doped with the silex glass of arsenic ion.
3. the formation method of fin as claimed in claim 2, is characterized in that, it is in-situ doped chemical vapor deposition method that described dielectric layer forms technique.
4. the formation method of fin as claimed in claim 3, is characterized in that, the temperature of described in-situ doped chemical vapor deposition method is 300 ~ 500 degrees Celsius, and deposit cavity pressure is 0.2 ~ 0.5 holder, and the silicon source gas of employing is SiH 4, impurity source gas is PH 3, B 2h 6or AsH 3, other gases are O 2.
5. the formation method of fin as claimed in claim 3, is characterized in that, the temperature of described in-situ doped chemical vapor deposition method is 350 ~ 550 degrees Celsius, deposit cavity pressure is 600 holders, the silicon source gas adopting is TEOS, and impurity source gas is TMP, TMB or TMAs, and other gases are O 3.
6. the formation method of the fin as described in claim 4 or 5, it is characterized in that, while adopting in-situ doped chemical vapor deposition method to form dielectric layer, in deposition process, by regulating the flow of impurity source gas to regulate the molar concentration of the foreign ion adulterating in dielectric layer.
7. the formation method of fin as claimed in claim 2, is characterized in that, along the technique of dielectric layer described in opening etching, is isotropic dry etch process, and the gas that described isotropic dry etching adopts is CF 4and He, CF 4flow be 200 ~ 500sccm, the flow of He is 1 ~ 2slm, etch chamber pressure is 1 ~ 10Pa, radio-frequency power is 250 ~ 350W, the frequency of radio frequency is 13.56MHz.
8. the formation method of fin as claimed in claim 7, it is characterized in that, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, increase gradually, when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove increases gradually.
9. the formation method of fin as claimed in claim 8, is characterized in that, the sidewall of described groove and the angle of Semiconductor substrate are 80 ~ 85 degree.
10. the formation method of fin as claimed in claim 7, it is characterized in that, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, reduce gradually, when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove reduces gradually.
The formation method of 11. fins as claimed in claim 10, is characterized in that, the sidewall of described groove and the angle of Semiconductor substrate are 95 ~ 100 degree.
The formation method of 12. fins as claimed in claim 7, it is characterized in that, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, first reduces gradually, after reaching minimum value, increase gradually again, when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove first reduces gradually, increases gradually after reaching minimum value again.
The formation method of 13. fins as claimed in claim 12, is characterized in that, the molar concentration of the foreign ion adulterating in described dielectric layer reaches minimum value in the centre position of dielectric layer, and the molar concentration of the surface of dielectric layer and the foreign ion of bottom equates.
The formation method of 14. fins as claimed in claim 7, it is characterized in that, the molar concentration of the foreign ion adulterating in described dielectric layer, from the surface of dielectric layer to bottom, first increases gradually, after reaching maximum, reduce gradually again, when along dielectric layer described in opening etching, while forming groove, from the surface of dielectric layer to bottom, the width of described groove first increases gradually, reduces gradually after reaching maximum again.
The formation method of 15. fins as claimed in claim 14, is characterized in that, the molar concentration of the foreign ion adulterating in described dielectric layer reaches maximum in the centre position of dielectric layer, and the molar concentration of the surface of dielectric layer and the foreign ion of bottom equates.
16. 1 kinds of fins, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the some fins in described Semiconductor substrate, from the top surface of fin to bottom, the width of described fin gradually changes.
17. fins as claimed in claim 16, is characterized in that, from the top surface of fin to bottom, the width of described fin increases gradually, and the sidewall of described fin and the angle of Semiconductor substrate are 80 ~ 85 degree.
18. fins as claimed in claim 16, is characterized in that, from the top surface of fin to bottom, the width of described fin reduces gradually, and the sidewall of described fin and the angle of Semiconductor substrate are 95 ~ 100 degree.
19. fins as claimed in claim 16, is characterized in that, from the top surface of fin to bottom, the width of described fin first reduces gradually, after the centre position of fin reaches minimum value, increases gradually again.
20. fins as claimed in claim 16, is characterized in that, from the top surface of fin to bottom, the width of described fin first increases gradually, after the centre position of fin reaches maximum, reduces gradually again.
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