CN103681320A - Production method of germanium-silicon heterojunction bipolar triode device - Google Patents

Production method of germanium-silicon heterojunction bipolar triode device Download PDF

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CN103681320A
CN103681320A CN201210315732.0A CN201210315732A CN103681320A CN 103681320 A CN103681320 A CN 103681320A CN 201210315732 A CN201210315732 A CN 201210315732A CN 103681320 A CN103681320 A CN 103681320A
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CN103681320B (en
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周正良
潘嘉
陈曦
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

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Abstract

The invention discloses a production method of a germanium-silicon heterojunction bipolar triode device. A single crystal in an N-type extension region is etched to form a recess; a field oxide is grown; silicon oxide is deposited; a field oxygen recess lower than the surface of the single crystal for 500-1000 angstroms is formed by the chemical-mechanical grinding planarization; the silicon oxide and amorphous silicon are deposited; the photoetching and the dry etching are implemented for the amorphous silicon to open an active area of a base region; the edge of a window is positioned at a field oxygen beak; after the surface of the silicon is cleaned, germanium-silicon epitaxy is grown; the germanium-silicon upper surfaces of the active area and a field oxygen area are substantially leveled with each other; emitter window mediums are deposited; an emitter window and a collector active area are opened; N-type heavy-doped emitter polycrystalline silicon is deposited to form an emitter-base junction and a low-resistance channel. The production method adjusts the relative heights of field oxygen and monocrystalline silicon and the position of a germanium-silicon window opposite to the field oxygen beak; the germanium-silicon growth surfaces are even; the germanium-silicon and the emitter polycrystalline silicon have uniform thicknesses; the size of the emitter window is easy to control; germanium-silicon heterojunction bipolar transistor devices have stable characteristics.

Description

The manufacture method of Ge-Si heterojunction bipolar type triode device
Technical field
The present invention relates to semiconductor integrated circuit field, belong to especially a kind of manufacture method of Ge-Si heterojunction bipolar type triode device.
Background technology
In conventional Ge-Si heterojunction bipolar type triode technique, after n type buried layer 1 ', n type buried layer 2 ', low-doped N-type extension 3 ' and collector terminal 4 ' complete, raw long field oxide 6 ' or with shallow slot as isolation, deposit one deck silica and one deck amorphous silicon subsequently, photoetching and dry etching amorphous silicon are opened active area, base; Wet method is removed the silica exposing and is cleaned silicon face, carries out the growth of germanium and silicon epitaxial layer 9 ', the germanium and silicon epitaxial layer of growing single-crystal structure on active area, base, and other region is polysilicon structure.Subsequent technique comprises the dry removal polysilicon of collector terminal 4 ' and the polysilicon of perimeter, outer base area carved successively, deposit medium photoetching and dry quarter are opened emitter-window and collector terminal, deposit N-type heavily doped polysilicon, the emitter-polysilicon 12 ' that emitter-window place forms contacts with germanium silicon single crystal silicon and forms EB junction, N-type heavily doped polysilicon contacts with N-type heavy doping collector region monocrystalline silicon (being collector terminal 4 ') and forms low-resistance exit, resulting devices has just formed, the sectional view of device architecture as shown in Figure 1, in outer base area, can leave silica and amorphous si-layer.
In Ge-Si heterojunction bipolar type triode, Ge-Si heterojunction is the core of device, owing to having introduced the unformed silicon of one deck, the defect forming when reducing germanium silicon growth needs to adopt the high temperature pre-treatment higher than 900 degree in follow-up germanium and silicon epitaxial layer growth, and at high temperature unformed silicon crystallization again, make device surface pattern very coarse, cause subsequent technique be subject to this affect there will be such as photoetching cannot aim at, the problem such as defect increases, base collector junction leakage, technique are unstable.But for comprising except germanium silicium HBT in the manufacturing process that also has other devices, amorphous silicon is used for protecting other devices and necessary, isolation structure is optimized and is selected the position of active area, base window edge device performance is stablized most important.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method of Ge-Si heterojunction bipolar type triode device, can improve the thickness evenness of germanium and silicon epitaxial layer and emitter-polysilicon, reduce the defect of base, solve the junction leakage between collector electrode and base stage, improve stability and the product yield of technique.
For solving the problems of the technologies described above, the manufacture method of Ge-Si heterojunction bipolar type triode device of the present invention, comprises the following steps:
Step 1 forms n type buried layer on P type silicon substrate, the N-type of growing on n type buried layer epitaxial loayer; Carry out N-type Implantation, form the first ion implanted region that bottom is connected with n type buried layer in N-type epitaxial loayer, described the first ion implanted region becomes collector electrode draw-out area;
Step 2, growth one deck liner oxidation silicon, deposit one deck silicon nitride on it; The region that wish forms an oxygen is opened in photoetching, dry carve remove the silicon nitride of opened areas and the crystal formation of liner oxidation silicon etching N type epitaxial loayer recessed, in the raw long field oxide isolation of described recess;
Step 3, deposit one deck silica also carries out cmp planarization to this layer of silica, and wet method is removed silicon nitride and is removed liner oxidation silicon, and it is recessed that a partial oxygen SiClx for a wet method removal oxygen isolation forms an oxygen;
Step 4, growth one sacrificial silicon oxide layer, carries out N-type Implantation, forms the second ion implanted region under the emitter-window of follow-up definition, and described the second bottom, ion implanted region is connected with n type buried layer and becomes the low resistance of collector electrode base; Wet etching is removed sacrificial silicon oxide layer, and silicon chip surface is cleaned and obtains flawless monocrystalline silicon surface;
Step 5, growth one deck silica, first deposit one deck silica unformed silicon of deposit one deck again on it, the unformed silicon of photoetching and dry etching forms active area, base window, the edge of active area, described base window is positioned at a beak place for oxygen isolation, and other region outside the window of active area, base retains amorphous silicon and silica;
Step 6, growth germanium and silicon epitaxial layer, the germanium and silicon epitaxial layer at window place, active area, base is monocrystal silicon structure, the germanium and silicon epitaxial layer on an oxygen isolation and the first ion implanted region is polysilicon structure;
Step 7, makes to block with photoresist active area, base and outer base area, and dry etching is removed the polysilicon of the part that is not blocked and is parked on silica, and rewetting method is removed silica;
Step 8, deposit emitter-window medium, lithographic definition dry etching are opened emitter-window and collector electrode draw-out area, cleaning silicon chip surface deposit N-type polysilicon, described emitter-window medium is from bottom to top for silica adds silicon nitride;
Step 9, make to block with photoresist emitter and collector draw-out area, etching is removed the polysilicon of non-occluded area and the silicon nitride of emitter-window medium and is parked on silica, makes resilient coating P type Implantation formation injection region, outer base area is carried out in outer base area with silica; Remove photoresist, deposit medium also returns and carves formation polysilicon side wall;
Step 10, carries out thermal annealing, and the N-type impurity activation in emitter-polysilicon also diffuses to form emitter base junction, and the impurity activation of germanium and silicon epitaxial layer and collector region also diffuses to form base-collector junction; Depositing silicide alloy-layer, adopts contact hole technique with metal connecting line technique, emitter, base stage and collector electrode to be connected.
In step 1, n type buried layer is heavy doping, and injection ion is arsenic, and Implantation Energy is 30～120keV, and dosage is 10 15～10 16cm -2; The impurity of N-type epitaxial loayer is phosphorus, and doping content is 2 * 10 15～5 * 10 16cm -3; The injection ion of the first ion implanted region is phosphorus, and Implantation Energy is 80～180keV, and dosage is 10 15～10 16cm -2.
In step 1, after forming, n type buried layer adopt boiler tube to carry out high temperature propelling, regrowth N-type epitaxial loayer.The temperature that high temperature advances is 1000～1100 ℃, and the time is 30～120 minutes.
In step 2, the recessed degree of depth of the monocrystalline of N-type epitaxial loayer is 3000～8000 dusts, and the thickness of an oxygen isolation is 6000～15000 dusts, and the thickness of liner oxidation silicon is 100～300 dusts, and the thickness of silicon nitride is 1000～3000 dusts.
In step 3, the thickness of silica is 3000～8000 dusts, cmp is removed the silica on silicon nitride completely, the silicon oxide surface of field oxygen recess, than low 500～1000 dusts of the single-crystal surface of N-type epitaxial loayer, forms a mono-crystalline structures that is ramped shaped between the oxygen isolation of described field and N-type epitaxial loayer top.
In step 4, the thickness of sacrificial oxide layer is 100～300 dusts, the second ion implanted region is once injected by selective N type ion or is repeatedly injected and form, and wherein once injects or repeatedly inject the thickness that has at least the injection degree of depth of once injecting to reach N-type epitaxial loayer.
In step 5, the unformed silicon face in an oxygen isolation and the single-crystal surface of N-type epitaxial loayer flush.
In step 6, germanium and silicon epitaxial layer is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, and wherein germanium silicon layer and silicon cap layer are respectively doped with boron; The thickness of described silicon buffer layer is 100～500 dusts; The thickness of described germanium silicon layer is 200～800 dusts, 20～300 dust doped with boron wherein, and doping content is 2 * 10 19～6 * 10 19cm -3; The thickness of described silicon cap layer is 200～500 dusts, and doping content is 10 15～10 17cm -3; Difference in height between germanium policrystalline silicon surface in germanium silicon single crystal surface on active area, base and an oxygen isolation is-300～300 dusts.
In step 8, N-type polysilicon is doping in place or ion implantation doping, and doping ion is phosphorus and/or arsenic, and concentration is greater than 10 20cm -3.
In step 8, the oxide layer deposit N-type again polysilicon of the rear first rapid thermal oxidation growth in cleaning silicon chip surface 5～10 dusts.
In step 9, the injection ion of injection region, outer base area is boron or boron fluoride, and Implantation Energy is 5～120keV, and implantation dosage is 10 15～10 16cm -2.
In step 10, the temperature of thermal annealing is 1015～1050 ℃, and the time is 5～30 seconds, forms 300～500 dusts and gradual EB junction.
The present invention is recessed through monocrystalline silicon layer, field oxide growth, silicon oxide deposition and cmp form an oxygen isolated area, through wet etching, make an oxygen isolated area lower than active area, base, between active area, base and an oxygen isolated area, form slow mono-crystalline structures that is ramped shaped, make germanium and silicon epitaxial edge of window along being positioned at this region, at monocrystalline and polycrystalline junction, can obtain level and smooth pattern, and by reducing the height of relative active area, Chang Yang district, the upper surface that can obtain substantially flushing after germanium silicon growth, this improvement can obtain uniform germanium and silicon epitaxial layer thickness and emitter-polysilicon thickness, the crucial emitter-window size of better control, thereby obtain stable germanium silicium HBT device property.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of existing Ge-Si heterojunction bipolar type triode device;
Fig. 2 to Figure 16 is the schematic cross-section of Ge-Si heterojunction bipolar type triode device in manufacture process in the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation.
The manufacture method of Ge-Si heterojunction bipolar type triode device provided by the invention, comprises the following steps:
Step 1, on P type silicon substrate 1, form heavily doped n type buried layer 2, the lightly doped N-type epitaxial loayer 3 of growing on n type buried layer 2, wherein the injection ion of n type buried layer 2 for upwards spreading less arsenic when higher thermal expense, Implantation Energy is 30～120keV, and dosage is 10 15～10 16cm -2, the impurity of N-type epitaxial loayer 3 is phosphorus, doping content is 2 * 10 15～5 * 10 16cm -3; Carry out N-type Implantation, inject the phosphorus that ion preferably at high temperature easily advances, Implantation Energy is 80～180keV, and dosage is 10 15～10 16cm -2, in N-type epitaxial loayer 3, forming the first ion implanted region 4 that bottom is connected with n type buried layer 2, this first ion implanted region 4 becomes collector electrode draw-out area; Preferably, after n type buried layer 2 forms, adopting boiler tube to carry out temperature is that 1000～1100 ℃, time are that the high temperature of 30～120 minutes advances, regrowth N-type epitaxial loayer 3;
Step 2, the liner oxidation silicon of growth one deck 100～300 dusts, the silicon nitride 5 of deposit one deck 1000～3000 dusts on it; The region that wish forms an oxygen is opened in photoetching, and dry quarter removes the silicon nitride 5 of opened areas and the crystal formation degree of depth of liner oxidation silicon etching N type epitaxial loayer 3 is the recessed of 3000～8000 dusts, as shown in Figure 2;
Step 3 is the field oxygen isolation 6 of 6000～15000 dusts at described monocrystalline recess growth thickness, as shown in Figure 3;
Step 4, deposit a layer thickness is the silica of 3000～8000 dusts, as shown in Figure 4, then carries out cmp and removes the silica on silicon nitride 5 completely, wet method is removed silicon nitride 5 and is removed liner oxidation silicon, as shown in Figure 5;
Step 5, it is recessed that a partial oxygen SiClx for a wet method removal oxygen isolation 6 forms an oxygen, the silicon oxide surface of field oxygen recess is than low 500～1000 dusts of the single-crystal surface of N-type epitaxial loayer 3, between the oxygen isolation 6 of described field and N-type epitaxial loayer 3 tops, form slow mono-crystalline structures that is ramped shaped, as shown in Figure 6;
Step 6, the grow sacrificial silicon oxide layer of one 100～300 dusts, carry out selective N type Implantation, in 11 times formation the second ion implanted regions 7 of emitter-window of follow-up definition, 7 bottoms, described the second ion implanted region are connected with n type buried layer 2 becomes the low resistance of collector electrode base; Wet etching is removed sacrificial silicon oxide layer, and silicon chip surface is cleaned and obtains flawless monocrystalline silicon surface; The thin silicon oxide of regrowth one deck 30～80 dusts, first deposit one deck silica unformed silicon 8 of deposit one deck again on it, as shown in Figure 7, now unformed silicon 8 surfaces in an oxygen isolation 6 and the single-crystal surface of N-type epitaxial loayer 3 flush; The second ion implanted region 7 can be once to inject or repeatedly inject, and can regulate the puncture voltage of device, wherein has at least the energy once injecting will guarantee to inject the thickness that the degree of depth reaches N-type epitaxial loayer 3;
Step 7, the unformed silicon of photoetching and dry etching forms active area, base window, and the edge of active area, described base window is positioned at a beak place for oxygen isolation 6, and other region outside the window of active area, base retains amorphous silicon and silica, as shown in Figure 8, Figure 9;
Step 8, growth germanium and silicon epitaxial layer 9, the germanium and silicon epitaxial layer at window place, active area, base is monocrystal silicon structure, the germanium and silicon epitaxial layer in an oxygen isolation 6 is polysilicon structure; Germanium and silicon epitaxial layer 9 is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, and wherein germanium silicon layer and silicon cap layer are respectively doped with boron; The thickness of described silicon buffer layer is 100～500 dusts; The thickness of described germanium silicon layer is 200～800 dusts, 20～300 dust doped with boron wherein, and doping content is 2 * 10 19～6 * 10 19cm -3; The thickness of described silicon cap layer is 200～500 dusts, and doping content is 10 15～10 17cm -3; Be less than ± 300 dusts of difference in height on the polycrystalline surface in the single-crystal surface of active area, base and an oxygen isolation 6, as shown in figure 10;
Step 9, makes to block with photoresist active area, base and outer base area, and dry etching is removed the polysilicon of the part that is not blocked, and rewetting method is removed silica, as shown in figure 11;
Step 10, deposit emitter-window medium 10, described emitter-window medium 10 is preferably double-deck, and as silica adds silicon nitride, lithographic definition dry etching are opened emitter-window 11 and collector electrode draw-out area, as shown in figure 12;
Step 11, cleaning silicon chip surface deposit N-type polysilicon, as shown in figure 13, N-type polysilicon can be that doping in place can be also ion implantation doping, and doping ion is phosphorus and/or arsenic, and concentration is greater than 10 20cm -3; Also can cleaning silicon chip surface the oxide layer deposit N-type again polysilicon of rear first rapid thermal oxidation growth 5～10 dusts;
Step 12, make to block with photoresist emitter and collector draw-out area, etching is removed polysilicon and the silicon nitride in emitter-window medium 10 of non-occluded area and is parked on silica, with silica, make resilient coating and P type Implantation is carried out in outer base area, as shown in figure 14, injecting ion is boron or boron fluoride, and Implantation Energy is 5～120keV, and implantation dosage is 10 15～10 16cm -2, form injection region, outer base area 13;
Step 13, removes photoresist, and deposit medium also returns and carves formation polysilicon side wall, as shown in figure 15;
Step 14, carry out thermal annealing, temperature is 1015～1050 ℃, higher than 0～20 ℃ of conventional germanium silicon technology, time is 5～30 seconds, and the N-type impurity activation in emitter-polysilicon 12 also diffuses to form the gradual EB junction that the degree of depth is 300～500 dusts, and its side is due to the optimization of silica undercut shape, its depth profiles of dopant distribution is milder, can stop the improper increase of base recombination current; The impurity of germanium and silicon epitaxial layer and collector region is also activated and diffuses to form base-collector junction simultaneously;
Step 15, depositing silicide alloy-layer 14, adopts contact hole technique with metal connecting line technique, emitter, base stage and collector electrode to be connected, as shown in figure 16.
The present invention is recessed through monocrystalline silicon layer, field oxide growth, silicon oxide deposition and cmp form an oxygen isolated area, through wet etching, make an oxygen isolated area lower than active area, base, between active area, base and an oxygen isolated area, form slow mono-crystalline structures that is ramped shaped, make germanium and silicon epitaxial edge of window along being positioned at this region, at monocrystalline and polycrystalline junction, can obtain level and smooth pattern, and by reducing the height of relative active area, Chang Yang district, the upper surface that can obtain substantially flushing after germanium silicon growth, this improvement can obtain uniform germanium and silicon epitaxial layer thickness and emitter-polysilicon thickness, the crucial emitter-window size of better control, thereby obtain stable germanium silicium HBT device property.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement to the present invention, and these also should be considered as protection scope of the present invention.

Claims (13)

1. a manufacture method for Ge-Si heterojunction bipolar type triode device, is characterized in that, comprises the following steps:
Step 1, at the upper n type buried layer (2) that forms of P type silicon substrate (1), at the upper growth of n type buried layer (2) N-type epitaxial loayer (3); Carry out N-type Implantation, form the first ion implanted region (4) that bottom is connected with n type buried layer (2) in N-type epitaxial loayer (3), described the first ion implanted region (4) becomes collector electrode draw-out area;
Step 2, growth one deck liner oxidation silicon, deposit one deck silicon nitride (5) on it; The region that wish forms an oxygen is opened in photoetching, dry carve remove the silicon nitride (5) of opened areas and the crystal formation of liner oxidation silicon etching N type epitaxial loayer (3) recessed, at the raw long field oxide of described recess, isolate (6);
Step 3, deposit one deck silica also carries out cmp planarization to this layer of silica, and wet method is removed silicon nitride (5) and is removed liner oxidation silicon, and it is recessed that a partial oxygen SiClx for a wet method removal oxygen isolation (6) forms an oxygen;
Step 4, the sacrificial silicon oxide layer of growing, carry out N-type Implantation, in lower second ion implanted region (7) that forms of emitter-window (11) of follow-up definition, bottom, described the second ion implanted region (7) is connected with n type buried layer (2) and becomes the low resistance of collector electrode base; Wet etching is removed sacrificial silicon oxide layer, and silicon chip surface is cleaned and obtains flawless monocrystalline silicon surface;
Step 5, growth one deck silica, first deposit one deck silica unformed silicon of deposit one deck (8) again on it, the unformed silicon of photoetching and dry etching forms active area, base window, the edge of active area, described base window is positioned at a beak place for oxygen isolation (6), and other region outside the window of active area, base retains amorphous silicon and silica;
Step 6, growth germanium and silicon epitaxial layer (9), the germanium and silicon epitaxial layer at window place, active area, base is monocrystal silicon structure, the germanium and silicon epitaxial layer in an oxygen isolation (6) and the first ion implanted region (4) is polysilicon structure;
Step 7, makes to block with photoresist active area, base and outer base area, and dry etching is removed the polysilicon of the part that is not blocked and is parked on silica, and rewetting method is removed silica;
Step 8, deposit emitter-window medium (10), lithographic definition dry etching are opened emitter-window (11) and collector electrode draw-out area, cleaning silicon chip surface deposit N-type polysilicon, and described emitter-window medium (10) is from bottom to top for silica adds silicon nitride;
Step 9, make to block with photoresist emitter and collector draw-out area, etching is removed the polysilicon of non-occluded area and the silicon nitride of emitter-window medium (10) and is parked on silica, makes resilient coating P type Implantation formation injection region, outer base area (13) is carried out in outer base area with silica; Remove photoresist, deposit medium also returns and carves formation polysilicon side wall;
Step 10, carries out thermal annealing, and the N-type impurity activation in emitter-polysilicon (12) also diffuses to form EB junction, and the impurity activation of germanium and silicon epitaxial layer and collector region also diffuses to form base-collector junction; Depositing silicide alloy-layer, adopts contact hole technique with metal connecting line technique, emitter, base stage and collector electrode to be connected.
2. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, is characterized in that, in step 1, n type buried layer (2) is heavy doping, and injection ion is arsenic, and Implantation Energy is 30～120keV, and dosage is 10 15～10 16cm -2; The impurity of N-type epitaxial loayer (3) is phosphorus, and doping content is 2 * 10 15～5 * 10 16cm -3; The injection ion of the first ion implanted region (4) is phosphorus, and Implantation Energy is 80～180keV, and dosage is 10 15～10 16cm -2.
3. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1 and 2, is characterized in that, in step 1, adopts boiler tube to carry out high temperature propelling, regrowth N-type epitaxial loayer (3) after n type buried layer (2) forms.
4. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 3, is characterized in that, the temperature that high temperature advances is 1000～1100 ℃, and the time is 30～120 minutes.
5. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, it is characterized in that, in step 2, the recessed degree of depth of monocrystalline of N-type epitaxial loayer (3) is 3000～8000 dusts, the thickness of field oxygen isolation (6) is 6000～15000 dusts, the thickness of liner oxidation silicon is 100～300 dusts, and the thickness of silicon nitride is 1000～3000 dusts.
6. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, it is characterized in that, in step 3, the thickness of silica is 3000～8000 dusts, cmp is removed the silica on silicon nitride (5) completely, the silicon oxide surface of field oxygen recess, than low 500～1000 dusts of the single-crystal surface of N-type epitaxial loayer (3), forms a mono-crystalline structures that is ramped shaped between described oxygen isolation (6) and N-type epitaxial loayer (3) top.
7. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, it is characterized in that, in step 4, the thickness of sacrificial oxide layer is 100～300 dusts, the second ion implanted region (7) is once injected by selective N type ion or is repeatedly injected and form, and wherein once injects or repeatedly inject the thickness that has at least the injection degree of depth of once injecting to reach N-type epitaxial loayer (3).
8. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, is characterized in that, in step 5, unformed silicon (8) surface in an oxygen isolation (6) and the single-crystal surface of N-type epitaxial loayer (3) flush.
9. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, is characterized in that, in step 6, germanium and silicon epitaxial layer (9) is divided into silicon buffer layer, germanium silicon layer and silicon cap layer, and wherein germanium silicon layer and silicon cap layer are respectively doped with boron; The thickness of described silicon buffer layer is 100～500 dusts; The thickness of described germanium silicon layer is 200～800 dusts, 20～300 dust doped with boron wherein, and doping content is 2 * 10 19～6 * 10 19cm -3; The thickness of described silicon cap layer is 200～500 dusts, and doping content is 10 15～10 17cm -3; Germanium silicon single crystal surface on active area, base and the difference in height between the germanium policrystalline silicon surface in an oxygen isolation (6) are-300～300 dusts.
10. the manufacture method of Ge-Si heterojunction bipolar type triode device according to claim 1, is characterized in that, in step 8, N-type polysilicon is doping in place or ion implantation doping, and doping ion is phosphorus and/or arsenic, and concentration is greater than 10 20cm -3.
The manufacture method of 11. Ge-Si heterojunction bipolar type triode devices according to claim 1, is characterized in that, in step 8, and the oxide layer deposit N-type again polysilicon of the rear first rapid thermal oxidation growth in cleaning silicon chip surface 5～10 dusts.
The manufacture method of 12. Ge-Si heterojunction bipolar type triode devices according to claim 1, is characterized in that, in step 9, the injection ion of injection region, outer base area (13) is boron or boron fluoride, and Implantation Energy is 5～120keV, and implantation dosage is 10 15～10 16cm -2.
The manufacture method of 13. Ge-Si heterojunction bipolar type triode devices according to claim 1, is characterized in that, in step 10, the temperature of thermal annealing is 1015～1050 ℃, and the time is 5～30 seconds, forms 300～500 dusts and gradual EB junction.
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CN105428402A (en) * 2014-09-12 2016-03-23 恩智浦有限公司 Bipolar transistor
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