CN103676281A - Array substrate and manufacturing method thereof, and display device - Google Patents
Array substrate and manufacturing method thereof, and display device Download PDFInfo
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- CN103676281A CN103676281A CN201310717336.5A CN201310717336A CN103676281A CN 103676281 A CN103676281 A CN 103676281A CN 201310717336 A CN201310717336 A CN 201310717336A CN 103676281 A CN103676281 A CN 103676281A
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Abstract
The invention provides an array substrate and a manufacturing method thereof, and a display device. The display device comprises the array substrate and a color film substrate. The array substrate comprises a first substrate, a plurality of grid lines, data lines, an organic insulating film layer, a thin film transistor and a first shading layer, wherein the grid lines and the data lines are arranged in a perpendicularly crossed mode and formed on the first substrate; the upper sides of the grid lines and the data lines are covered with the organic insulating film layer, the film thickness of the organic insulating film layer is greater than a preset threshold value, and the organic insulating film layer is used for eliminating segment differences caused by the grid lines and the data lines; the thin film transistor is arranged in a pixel region defined by the grid lines and the data lines which are arranged in the perpendicularly crossed mode; the first shielding layer is formed on a source electrode and a drain electrode of the thin film transistor, and at least the region between the source electrode and the drain electrode can be shielded by the first shading layer. The color film substrate comprises a second substrate and a color resin filter layer which is formed on the second substrate. By the adoption of the scheme, transmittance of the display device can be improved.
Description
Technical field
The present invention relates to display technique field, relate in particular to a kind of array base palte and preparation method thereof, display device.
Background technology
Please refer to Fig. 1 to Fig. 3, thin film transistor-liquid crystal display of the prior art (TFT-LCD) panel comprises: array base palte 100 and color membrane substrates 200, this array base palte 100 comprises: first substrate 101 and be formed at grid line (scheming not shown) on described first substrate 101, data line (scheming not shown), gate electrode 102, gate insulation layer 103, active layer 104, source electrode 105, drain electrode 106, passivation (PVX) layer 107 and pixel electrode 108.This color membrane substrates 200 comprises: second substrate 201, light shield layer 202, colored filter 203 and public electrode 204.
Grid line on above-mentioned array base palte 100 and data line are can the section of causing poor, cause grid line and data line region that light leak occurs.In order to block the light leak of grid line and data line region, in prior art, be, on the corresponding grid line of color membrane substrates 200 and the position in data line region, light shield layer 202 is set.Yet this light shield layer 202 can cause the transmitance of display device to reduce.As can be seen from Figure 3, backlight 300 regions that cannot see through light shield layer 202 places.
Summary of the invention
In view of this, the invention provides a kind of array base palte and preparation method thereof, display device, in order to improve the transmitance of display device.
For solving the problems of the technologies described above, the invention provides a kind of array base palte and comprise: first substrate, and many grid lines that are formed at that square crossing on described first substrate arranges and data line, it is characterized in that, also comprise:
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause.
Preferably, described predetermined threshold value is 2 microns.
Preferably, described array base palte also comprises:
Thin film transistor (TFT) and pixel electrode, be arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit; And
The first light shield layer, is formed on the source electrode and drain electrode of described thin film transistor (TFT), and described the first light shield layer at least can block the region between described source electrode and described drain electrode.
Preferably, described organic insulation rete is covered on described source electrode, described drain electrode and described the first light shield layer, and wherein, described pixel electrode is formed on described organic insulation rete.
Preferably, described organic insulation rete is covered on described source electrode and described drain electrode; Wherein, described the first light shield layer and described pixel electrode are formed on described organic insulation rete.
Preferably, described the first light shield layer is black matrix.
The present invention also provides a kind of display device, it is characterized in that, comprises above-mentioned array base palte.
The present invention also puies forward a kind of display device, comprises array base palte and color membrane substrates, and described array base palte comprises:
First substrate;
Many grid lines that square crossing arranges and data line, be formed on described first substrate;
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause;
Thin film transistor (TFT), is arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit;
The first light shield layer, is formed on the source electrode and drain electrode of described thin film transistor (TFT), and described the first light shield layer at least can block the region between described source electrode and described drain electrode;
Described color membrane substrates comprises:
Second substrate;
Color resin filter layer, is formed on described second substrate.
The present invention also provides a kind of display device, comprises array base palte and color membrane substrates, and described array base palte comprises:
First substrate;
Many grid lines that square crossing arranges and data line, be formed on described first substrate;
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause;
Thin film transistor (TFT), is arranged at by square crossing and arranges in the pixel region that described many grid lines and data line limit;
Described color membrane substrates comprises:
Second substrate;
The second light shield layer, is formed on described second substrate, and the position of described the second light shield layer is corresponding with the source electrode of described thin film transistor (TFT) and the position in the region between drain electrode;
Color resin filter layer, is formed on described the second light shield layer.
The present invention also provides a kind of preparation method of array base palte, comprises the following steps:
Many grid lines that form on first substrate that square crossing arranges and data line;
Above described grid line and data line, form organic insulating film layer, the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause.
Preferably, the preparation method of described array base palte also comprises:
In the pixel region that many grid lines that arranged by square crossing and data line limit, form thin film transistor (TFT);
On the source of described thin film transistor (TFT) electrode and drain electrode, form the first light shield layer, described the first light shield layer at least can block the region between described source electrode and described drain electrode.
The beneficial effect of technique scheme of the present invention is as follows:
By organic insulating film layer is set above the grid line at array base palte and data line, poor to eliminate the section being caused by grid line and data line, therefore light shield layer on color membrane substrates and the corresponding setting of grid line and data line can be removed, to improve the transmitance of display device.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte of the prior art;
Fig. 2 is the A-A cross section structure schematic diagram of the array base palte in Fig. 1
Fig. 3 is that TFT-LCD panel of the prior art becomes data line B-B cross section structure schematic diagram after box;
Fig. 4 is the structural representation of the array base palte of the embodiment of the present invention one;
Fig. 5 is the C-C cross section structure schematic diagram of the array base palte in Fig. 4;
Fig. 6 is that the TFT-LCD panel of the embodiment of the present invention one becomes data line D-D cross section structure schematic diagram after box;
Fig. 7 is the structural representation of the array base palte of the embodiment of the present invention two;
Fig. 8 is the structural representation of the display device of the embodiment of the present invention two.
Embodiment
The embodiment of the present invention provides a kind of array base palte, comprising:
First substrate;
Many grid lines that are formed at that square crossing on described first substrate arranges and data line; And
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause.
Above-mentioned predetermined threshold value can be 2 microns, and preferably, the thickness of described organic insulation rete is 2-5 micron.
In the embodiment of the present invention, by organic insulating film layer is set above the grid line at array base palte and data line, poor to eliminate the section being caused by grid line and data line, therefore light shield layer on color membrane substrates and the corresponding setting of grid line and data line can be removed, to improve the transmitance of display device.
Array base palte in the embodiment of the present invention also comprises: thin film transistor (TFT) and pixel electrode, be arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit.
Described thin film transistor (TFT) comprises again: source electrode and drain electrode, the region between source electrode and drain electrode (being channel region), if be subject to the impact of extraneous light can produce photocurrent, causes described channel region light leak.In order to block the light leak of described channel region, can on position corresponding to the described channel region of color membrane substrates, light shield layer be set.In addition, because considering the aligning accuracy of molding process, guarantee into not light leak of display device after box, in design, all can increase the live width of light shield layer, yet the live width that increases light shield layer will cause the transmitance of display device to reduce.
In order to address the above problem, the array base palte of the embodiment of the present invention can also comprise:
The first light shield layer, is formed on the source electrode and drain electrode of described thin film transistor (TFT), and described the first light shield layer at least can block the region (being channel region) between described source electrode and described drain electrode.
This first light shield layer can be black matrix, or the light shield layer of other materials.
On array base palte, be provided for blocking first light shield layer in the region between source electrode and drain electrode, remove and be arranged at the locational light shield layer corresponding with described channel region on color membrane substrates simultaneously, thereby the lighttight while of the display device after guaranteeing into box, further improved the transmitance of display device.
Above-mentioned thin film transistor (TFT) can specifically comprise:
Gate electrode, is formed on described first substrate.
Gate insulation layer, is formed on described gate electrode;
Active layer, is formed on described gate insulation layer;
Source electrode and drain electrode are formed on described active layer, and wherein, described drain electrode is connected with pixel electrode.
Organic insulation rete in above-described embodiment can be covered on described source electrode, described drain electrode and described the first light shield layer, and wherein, described pixel electrode is formed on described organic insulation rete.
In addition, the organic insulation rete in above-described embodiment can also be covered on described source electrode and described drain electrode; Wherein, described the first light shield layer and described pixel electrode are formed on described organic insulation rete.
Organic insulation rete in above-described embodiment is because its thickness is thicker, except can eliminate section that data line and grid line cause poor, can also make gate electrode and the distance between pixel electrode on array base palte become large, reduce the memory capacitance (Cst) between gate electrode and pixel electrode, thereby can provide condition for the display device of design and preparation high image resolution (PPI).
The embodiment of the present invention also provides a kind of display device, comprises above-mentioned array base palte.
The embodiment of the present invention also provides a kind of display device, comprises array base palte and color membrane substrates, wherein,
Described array base palte comprises:
First substrate;
Many grid lines that square crossing arranges and data line, be formed on described first substrate;
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause;
Thin film transistor (TFT), is arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit;
The first light shield layer, is formed on the source electrode and drain electrode of described thin film transistor (TFT), and described the first light shield layer at least can block the region (channel region) between described source electrode and described drain electrode;
Described color membrane substrates does not arrange light shield layer on position corresponding to described channel region, and described color membrane substrates comprises:
Second substrate;
Color resin filter layer, is formed on described second substrate.
Above-mentioned display device is by arranging organic insulating film layer above the grid line at array base palte and data line, poor to eliminate the section being caused by grid line and data line, therefore light shield layer on color membrane substrates and the corresponding setting of grid line and data line can be removed, to improve the transmitance of display device.In addition, on array base palte, be provided for blocking first light shield layer in the region between source electrode and drain electrode, remove and be arranged at the locational light shield layer corresponding with described channel region on color membrane substrates simultaneously, thereby the lighttight while of the display device after guaranteeing into box, further improved the transmitance of display device.
The embodiment of the present invention also provides a kind of display device, comprises array base palte and color membrane substrates, wherein,
Described array base palte comprises:
First substrate;
Many grid lines that square crossing arranges and data line, be formed on described first substrate;
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause;
Thin film transistor (TFT), is arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit;
Described color membrane substrates comprises:
Second substrate;
The second light shield layer, is formed on described second substrate, and the position of described the second light shield layer is corresponding with the source electrode of described thin film transistor (TFT) and the position in the region between drain electrode;
Color resin filter layer, is formed on described the second light shield layer.
Above-mentioned display device is by arranging organic insulating film layer above the grid line at array base palte and data line, poor to eliminate the section being caused by grid line and data line, therefore light shield layer on color membrane substrates and the corresponding setting of grid line and data line can be removed, to improve the transmitance of display device.
Display device in above-described embodiment can be: liquid crystal panel, Electronic Paper, OLED(Organic Light Emitting Diode, Organic Light Emitting Diode) panel, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone or panel computer etc. have product or the parts of any Presentation Function.
The embodiment of the present invention also provides a kind of preparation method of array base palte, comprises the following steps:
Many grid lines that form on first substrate that square crossing arranges and data line;
Above described grid line and data line, form organic insulating film layer, the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause.
For fear of the region light leak between source electrode and drain electrode, the preparation method of the array base palte of the embodiment of the present invention can also comprise the following steps:
In the pixel region that many grid lines that arranged by square crossing and data line limit, form thin film transistor (TFT);
On the source of described thin film transistor (TFT) electrode and drain electrode, form the first light shield layer, described the first light shield layer at least can block the region between described source electrode and described drain electrode.
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
embodiment mono-
Please refer to Fig. 4 to Fig. 5, is the structural representation of the array base palte of the embodiment of the present invention one, and this array base palte 400 is the array base palte of twisted nematic (TN) pattern, comprising:
Grid line (scheming not shown) and gate electrode 402, be formed on described first substrate 401;
Data line (scheming not shown), source electrode 405 and drain electrode 406, be formed on described active layer 404;
The first light shield layer 407, is formed on described source electrode 405 and described drain electrode 406, at least can block the region between described source electrode 405 and described drain electrode 406;
Please refer to Fig. 6, for the TFT-LCD panel of the embodiment of the present invention one becomes data line D-D cross section structure schematic diagram after box, this display device is except comprising above-mentioned array base palte 400, also comprise color membrane substrates 500, described color membrane substrates comprises: second substrate 501, color resin filter layer 502 and public electrode 503.
As can be seen from Figure 6, except backlight 300 of the first light shield layer 407 regions cannot see through, backlight 300 of other regions all can see through, thereby have improved the transmitance of display device.
The preparation method of the array base palte of the embodiment of the present invention comprises the following steps:
1) provide a first substrate 401;
2) on first substrate 401, form grid line (scheming not shown) and gate electrode 402;
3) on the substrate 401 that is formed with described grid line and gate electrode 402, form gate insulation layer 403;
4) form active layer 404 being formed with on the substrate 401 of described gate insulation layer 403;
5) on the substrate 401 of described active layer 404, form data line (scheming not shown), source electrode 405 and drain electrode 406 being formed with;
Above-mentioned steps 1) to 5) can form traditionally.
6) on source electrode 405 and drain electrode 406, form the first light shield layer 407;
Concrete, can then be coated with light screening material film and photoresist (PR) by cleaning being formed with the first substrate 401 of data line, source electrode 405 and drain electrode 406, expose, development and baking process, form the figure of the first light shield layer 407.
7) on the substrate 401 of described the first light shield layer 407, form organic insulating film layer 408 being formed with;
Concrete, can then be coated with organic insulating material film by cleaning being formed with the first substrate 401 of the first light shield layer 407, expose, development and baking process, form the organic insulation rete 408 having an even surface.
8) on organic insulation rete 408, form pixel electrode 409.
Finally, form traditionally pixel electrode 409, thereby complete the preparation of array base palte.
The preparation method of the color membrane substrates of the embodiment of the present invention comprises the following steps:
1) provide a second substrate 501;
2) on second substrate 501, form color resin filter layer 502;
3) on color resin filter layer 502, form public electrode 503.
In some embodiments, color membrane substrates 500 can also comprise cylindrical spacer (PS), therefore, after forming public electrode 503, can also comprise the step that forms cylindrical spacer.
embodiment bis-
Please refer to Fig. 7, is the structural representation of the array base palte of the embodiment of the present invention two, this array base palte 400 is the array base palte of senior super dimension field switch (ADS) or plane conversion (IPS) pattern, comprises setting gradually:
Grid line (scheming not shown) and gate electrode 402, be formed on described first substrate 401;
Data line (scheming not shown), source electrode 405 and drain electrode 406;
The first light shield layer 407, is formed on described source electrode 405 and described drain electrode 406, at least can block the region between described source electrode 405 and described drain electrode 406;
Please refer to Fig. 8, it is the structural representation that comprises the display device of the array base palte in Fig. 7, this display device, except comprising above-mentioned array base palte 400, also comprises color membrane substrates 500, and described color membrane substrates comprises: second substrate 501 and color resin filter layer 502.
As can be seen from Figure 8, except backlight 300 of the first light shield layer 407 regions cannot see through, backlight 300 of other regions all can see through, thereby have improved the transmitance of display device.
The preparation method of the array base palte of the embodiment of the present invention comprises the following steps:
1) provide a first substrate 401;
2) on first substrate 401, form public electrode 410;
3) on first substrate 401, form grid line (scheming not shown) and gate electrode 402;
4) on the first substrate 401 that is formed with grid line and gate electrode 402, form gate insulation layer 403;
5) form active layer 404 being formed with on the first substrate 401 of gate insulation layer 403;
6) on the first substrate 401 of active layer 404, form data line (scheming not shown), source electrode 405 and drain electrode 406 being formed with;
Above-mentioned steps 1) to 6) can form traditionally.
7) on source electrode 405 and drain electrode 406, form the first light shield layer 407;
Concrete, can then be coated with light screening material film and photoresist (PR) by cleaning being formed with the first substrate 401 of data line, source electrode 405 and drain electrode 406, expose, development and baking process, form the figure of the first light shield layer 407.
8) on the first substrate 401 of the first light shield layer 407, form organic insulating film layer 408 being formed with;
Concrete, can then be coated with organic insulating material film by cleaning being formed with the first substrate 401 of the first light shield layer 407, expose, development and baking process, form the organic insulation rete 408 having an even surface.
9) on organic insulation rete 408, form pixel electrode 409.
Finally, form traditionally pixel electrode 409, thereby complete the preparation of array base palte.
The preparation method of the color membrane substrates of the embodiment of the present invention comprises the following steps:
1) provide a second substrate 501;
2) on second substrate 501, form color resin filter layer 502.
In some embodiments, color membrane substrates 500 can also comprise cylindrical spacer (PS), therefore, after forming color resin filter layer 502, can also comprise the step that forms cylindrical spacer.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (11)
1. an array base palte, comprising: first substrate, and many grid lines that are formed at that square crossing on described first substrate arranges and data line, it is characterized in that, and also comprise:
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause.
2. array base palte as claimed in claim 1, is characterized in that, described predetermined threshold value is 2 microns.
3. array base palte as claimed in claim 1, is characterized in that, also comprises:
Thin film transistor (TFT) and pixel electrode, be arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit; And
The first light shield layer, is formed on the source electrode and drain electrode of described thin film transistor (TFT), and described the first light shield layer at least can block the region between described source electrode and described drain electrode.
4. array base palte as claimed in claim 3, is characterized in that, described organic insulation rete is covered on described source electrode, described drain electrode and described the first light shield layer, and wherein, described pixel electrode is formed on described organic insulation rete.
5. array base palte as claimed in claim 3, is characterized in that, described organic insulation rete is covered on described source electrode and described drain electrode; Wherein, described the first light shield layer and described pixel electrode are formed on described organic insulation rete.
6. array base palte as claimed in claim 3, is characterized in that, described the first light shield layer is black matrix.
7. a display device, is characterized in that, comprises the array base palte as described in claim 1-6 any one.
8. a display device, comprises array base palte and color membrane substrates, it is characterized in that,
Described array base palte comprises:
First substrate;
Many grid lines that square crossing arranges and data line, be formed on described first substrate;
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause;
Thin film transistor (TFT), is arranged in the pixel region that described many grid lines that arranged by square crossing and data line limit;
The first light shield layer, is formed on the source electrode and drain electrode of described thin film transistor (TFT), and described the first light shield layer at least can block the region between described source electrode and described drain electrode;
Described color membrane substrates comprises:
Second substrate;
Color resin filter layer, is formed on described second substrate.
9. a display device, comprises array base palte and color membrane substrates, it is characterized in that,
Described array base palte comprises:
First substrate;
Many grid lines that square crossing arranges and data line, be formed on described first substrate;
Organic insulation rete, is covered in the top of described grid line and data line, and the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause;
Thin film transistor (TFT), is arranged at by square crossing and arranges in the pixel region that described many grid lines and data line limit;
Described color membrane substrates comprises:
Second substrate;
The second light shield layer, is formed on described second substrate, and the position of described the second light shield layer is corresponding with the source electrode of described thin film transistor (TFT) and the position in the region between drain electrode;
Color resin filter layer, is formed on described the second light shield layer.
10. a preparation method for array base palte, is characterized in that, comprises the following steps:
Many grid lines that form on first substrate that square crossing arranges and data line;
Above described grid line and data line, form organic insulating film layer, the thickness of described organic insulation rete is greater than predetermined threshold value, poor for eliminating the section that described grid line and described data line cause.
The preparation method of 11. array base paltes as claimed in claim 10, is characterized in that, also comprises:
In the pixel region that many grid lines that arranged by square crossing and data line limit, form thin film transistor (TFT);
On the source of described thin film transistor (TFT) electrode and drain electrode, form the first light shield layer, described the first light shield layer at least can block the region between described source electrode and described drain electrode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016065852A1 (en) * | 2014-10-31 | 2016-05-06 | 京东方科技集团股份有限公司 | Coa substrate and manufacturing method thereof and display device |
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