CN103675376B - Semiconductor device with microprobe and its manufacturing method - Google Patents
Semiconductor device with microprobe and its manufacturing method Download PDFInfo
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- CN103675376B CN103675376B CN201210394101.2A CN201210394101A CN103675376B CN 103675376 B CN103675376 B CN 103675376B CN 201210394101 A CN201210394101 A CN 201210394101A CN 103675376 B CN103675376 B CN 103675376B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002360 preparation method Methods 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 20
- 239000004642 Polyimide Substances 0.000 claims description 14
- 229920001721 polyimide Polymers 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 13
- 229920002577 polybenzoxazole Polymers 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 7
- 229910000691 Re alloy Inorganic materials 0.000 claims description 6
- DECCZIUVGMLHKQ-UHFFFAOYSA-N rhenium tungsten Chemical compound [W].[Re] DECCZIUVGMLHKQ-UHFFFAOYSA-N 0.000 claims description 6
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052790 beryllium Inorganic materials 0.000 claims description 5
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052702 rhenium Inorganic materials 0.000 claims description 5
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 38
- 239000002184 metal Substances 0.000 description 38
- 238000000034 method Methods 0.000 description 29
- 239000000523 sample Substances 0.000 description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 7
- 229920001971 elastomer Polymers 0.000 description 6
- 239000000806 elastomer Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000002861 polymer material Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 150000000183 1,3-benzoxazoles Chemical class 0.000 description 1
- 241001455226 Sauria Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- -1 benzocyclobutane Alkene Chemical class 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Abstract
A semiconductor device having a microprobe and a method of fabricating the same, the semiconductor device comprising: a substrate having a first surface and a second surface opposite to each other; a first circuit layer formed on the first surface of the substrate; a first dielectric layer formed on the first surface of the substrate and the first circuit layer and having a first opening exposing the first circuit layer; a second circuit layer formed on the first dielectric layer and in the first opening; an insulating buffer layer formed on the first dielectric layer and the second circuit layer and having at least one opening exposing the second circuit layer; a third wiring layer formed on the insulating buffer layer and in the insulating buffer layer opening; a second dielectric layer formed on the insulating buffer layer and the third circuit layer and having at least one second opening exposing the third circuit layer; and a microprobe disposed in the second opening of the second dielectric layer. The invention can effectively buffer the external force applied to the microprobe and avoid elastic fatigue.
Description
Technical field
The present invention is about a kind of semiconductor device and preparation method thereof, and in more detail, the present invention is that one has resistance to elastic fatigue
The semiconductor device of microprobe and preparation method thereof.
Background technology
Now, along with the progress of development in science and technology, the dealer of electronic product develop one after another various different kenel in order to survey
The test probe card of examination electronic product.The preparation method of conventional probe card enjoys restriction and cost of manufacture higher because of probe size, so
Need to overcome many bottlenecks during making probe.And the size trend of semiconductor chip tends to microminiaturization and this is partly led at present
Body chip output contact is the most, and test probe structure is all formed by the most tiny probe wires again, therefore, and must be constantly
Improve and overcome the Technology of probe structure, coordinating with the semiconductor chip with microminiaturization, and overcome conventional probe structure in
The tired problem limited with probe size it is easily generated, to meet the trend of modern science and technology product during operation.
8001685B2 United States Patent (USP) discloses the preparation method of a kind of probe card, refers to 1A to 1K figure, for existing probe
The generalized section of the preparation method of card.
As shown in Figure 1A to Fig. 1 C, it is provided that a stack of ceramic plates 10, and in the end face formation first of this stack of ceramic plates 10
Conductive layer 12, and on this first conductive layer 12, form the first resistance layer 14, and should prior to removing part on this first conductive layer 12
First resistance layer 14, and this first conductive layer 12 of exposed parts, then this first conductive layer 12 of the part exposed is removed, move the most again
Except this first resistance layer 14, above-mentioned technique is defined as step 1.
As shown in Figure 1A ' to Fig. 1 C ', it is provided that semiconductor chip 10 ', and in the end face formation of this semiconductor chip 10 '
Photoresist layer 12 ', then pattern this photoresist layer 12 ' and form multiple opening 121 ' with the end face in this semiconductor chip 10 ', then,
Utilizing macromolecular elastomer 14 ' respectively to fill up by this opening 121 ', above-mentioned technique is defined as step 2.
As shown in figure ip, this macromolecular elastomer 14 ' of the structure of Fig. 1 C ' of step 2 is posted Fig. 1 C in step 1
In structure so that this macromolecular elastomer 14 ' is located at the end face of this stack of ceramic plates 10, and this macromolecular elastomer 14 ' has
Expose the first perforate 122 of the first conductive layer 12 of the end face of this stack of ceramic plates 10.
As referring to figure 1e, on this first conductive layer 12, the first metal layer 15, and the bottom of this first metal layer 15 are formed
For nickel dam 151, and top layer is layer gold 152.
As shown in fig. 1f, on this macromolecular elastomer 14 ' with this layer gold 152, form the second conductive layer 16, and in this
Two conductive layers 16 are provided with the second resistance layer 141.
As shown in Figure 1 G, pattern the perforate with formation this second conductive layer 16 of exposed parts of this second resistance layer 141, then at
The second metal level 18 is formed on this second conductive layer 16.
As shown in fig. 1h, it is provided with the 3rd resistance layer 142 in this second resistance layer 141 with this second metal level 18, and patterns
3rd resistance layer 142 exposes the opening of this second metal level 18 to be formed, and then, forms the 3rd gold medal on this second metal level 18
Belong to layer 181.
As shown in Figure 1 I, it is provided with the 4th resistance layer 143 in the 3rd resistance layer 142 with the 3rd metal level 181, and patterns
4th resistance layer 143 exposes the opening of the 3rd metal level 181 to be formed, and then, forms the 4th on the 3rd metal level 181
Metal level 182.
As shown in figure ij, it is provided with the 5th resistance layer 144 in the 4th resistance layer 143 with the 4th metal level 182, and patterns
4th resistance layer 143 exposes the opening of the 4th metal level 182 to be formed, and then, forms probe on the 4th metal level 182
Projection 183.
As shown in figure ik, this second resistance layer the 141, the 3rd resistance layer the 142, the 4th resistance layer 143 and the 5th resistance layer 144 are removed,
And complete probe card.
But, the preparation method of aforementioned existing probe card needs the structure of step 1 to be posted the structure to step 2, uses simultaneously
Semiconductor chip process and stack of ceramic plates technique, cause that integrated artistic is more complicated, yield is poor and Production Time is elongated, and causes
The problems such as cost raising, moreover, existing probe card because of structure is tiny and probe base partial suspended and do not have cushion to protect,
Therefore when operation is mobile, it is easily generated the disappearance such as elastic fatigue or damage.
Therefore, the variety of problems of prior art, actually an important topic how are overcome.
Summary of the invention
For solving the variety of problems of above-mentioned prior art, present invention is primarily targeted to disclose and a kind of there is microprobe
Semiconductor device and preparation method thereof, can effectively buffer external force suffered by microprobe and avoid elastic fatigue.
The semiconductor device with microprobe of the present invention includes: substrate, has relative first surface and second surface；
First line layer, is formed on the first surface of this substrate；First dielectric layer, be formed at the first surface of this substrate with this first
On line layer, and there is the first perforate exposing this first line layer；Second line layer, is formed on this first dielectric layer and is somebody's turn to do
In first perforate；Insulating buffer layer, is formed on this first dielectric layer and this second line layer, and have at least one expose this
The insulating buffer layer perforate of two line layers；Tertiary circuit layer, be formed on this insulating buffer layer with in this insulating buffer layer perforate；
Second dielectric layer, is formed on this insulating buffer layer and this tertiary circuit layer, and has at least one and expose this tertiary circuit layer
Second perforate；And microprobe, it is located in the second perforate of this second dielectric layer, and protrudes from this second dielectric layer.
The present invention provides again the preparation method of a kind of semiconductor device with microprobe, including: in one, there is relative first
First line layer is formed on the first surface of the substrate of surface and second surface；First surface and this first line in this substrate
Forming the first dielectric layer on layer, this first dielectric layer also has the first perforate exposing this first line layer；Form the second circuit
Layer on this first dielectric layer with in this first perforate；A buffer insulation is formed on this first dielectric layer with this second line layer
Layer, this insulating buffer layer also has at least one insulating buffer layer perforate exposing this second line layer；Formed tertiary circuit layer in
On this insulating buffer layer with in this insulating buffer layer perforate；The second dielectric is formed on this insulating buffer layer with this tertiary circuit layer
Layer, this second dielectric layer also has at least one the second perforate exposing this tertiary circuit layer；And in the of this second dielectric layer
Two perforates are formed microprobe, and this microprobe protrudes from this second dielectric layer.
In the preparation method of the aforesaid semiconductor device with microprobe, this first line layer, this second line layer with this
Three line layers and this microprobe are to be formed by plating mode.
In the preparation method of the aforesaid semiconductor device with microprobe, the position of this insulating buffer layer perforate is not to should
The position of one perforate, and the position of this second perforate not to should insulating buffer layer perforate, the position of this first perforate is right again
Should the position of the second perforate.
In the preparation method of the aforesaid semiconductor device with microprobe, this insulating buffer layer has two these insulating buffer layer
Perforate, and these two insulating buffer layer perforates be by this tertiary circuit layer connect, this microprobe is electrically connected with this tertiary circuit
Layer.
In the preparation method of the aforesaid semiconductor device with microprobe, also it is included in this second perforate and is formed with the 4th line
Road floor, and this microprobe is electrically connected with the 4th line layer.
In the preparation method of the aforesaid semiconductor device with microprobe, the material of this insulating buffer layer is BCB (benzocyclobutane
Alkene, Benzocyclo-buthene), polyimides (PI) or polybenzoxazoles (polybenzoxazole, PBO).
In the preparation method of the aforesaid semiconductor device with microprobe, the material of this microprobe is tungsten (W), rhenium (Re), beryllium
(Be), palladium (Pd), titanium-tungsten (TiW), tungsten-rhenium alloy (ReW) or beallon (BeCu).
According to upper described, the present invention utilizes the semiconductor device with microprobe to have the arcuate underlying structure and absolutely of syllogic
Edge cushion is to reduce microprobe structure when operation is mobile easily by elastic fatigue or the problem of damage, and the present invention more can produce
High density (being smaller than 40 microns of the most each microprobe) and the microprobe structure of microminiaturization, to expand test area, increase
Test contacts pin number (more than 10000 microprobe numbers).
Accompanying drawing explanation
Figure 1A to Fig. 1 K is for showing the generalized section of the preparation method of existing microprobe card, and Figure 1A to Fig. 1 C is used for showing
The generalized section of step 1 preparation method of existing microprobe card, Figure 1A ' to Fig. 1 C ' is for showing that the step 2 of existing microprobe card is made
The generalized section of method.
Fig. 2 A to Fig. 2 U is the section of the first embodiment of the semiconductor device with microprobe of the present invention and preparation method thereof
Schematic diagram.
Fig. 3 is the generalized section of the second embodiment of the semiconductor device with microprobe of the present invention and preparation method thereof.
Fig. 4 is the generalized section of the 3rd embodiment of the semiconductor device with microprobe of the present invention and preparation method thereof.
Fig. 5 is the generalized section of the 4th embodiment of the semiconductor device with microprobe of the present invention and preparation method thereof.
Primary clustering symbol description
10 stack of ceramic plates
10 ' semiconductor chips
12,214 first conductive layer
122,212 first perforate
12 ' photoresist layers
121 ' openings
14,202 first resistance layer
141,23 second resistance layer
142,26 the 3rd resistance layer
143,29 the 4th resistance layer
144,31 the 5th resistance layer
14 ' macromolecular elastomers
15 the first metal layers
151 nickel dams
152 layer gold
16,244 second conductive layer
18 second metal levels
181 the 3rd metal levels
182 the 4th metal levels
183 probe projections
20 base materials
20a first surface
20b second surface
201 the first metal layers
201 ' first line layers
2020 first resistance layer perforates
203 conductive through holes
204 polymer material layers
205 the 3rd perforates
206 soldering projections
21 first dielectric layers
22 second metal levels
22 ' second line layers
24 insulating buffer layer
242 insulating buffer layer perforates
25 the 3rd metal levels
25 ' tertiary circuit layers
27 second dielectric layers
272 second perforates
274 the 3rd conductive layers
28 the 4th metal levels
28 ' the 4th line layers
30 microprobes
32 bonding wires.
Detailed description of the invention
By particular specific embodiment, embodiments of the present invention being described below, those skilled in the art can be by this explanation
Content disclosed in book understands further advantage and effect of the present invention easily.
It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only in order to coordinate description to be taken off
The content shown, for understanding and the reading of those skilled in the art, is not limited to the enforceable qualifications of the present invention, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, do not affecting the present invention
Under the effect that can be generated by and the purpose that can reach, all should still fall and obtain, at disclosed technology contents, the model that can contain
In enclosing.Meanwhile, in this specification cited as " on ", " top ", " end ", the term of " " and " two " etc., be also only and be easy to chat
That states understands, and is not used to limit the enforceable scope of the present invention, being altered or modified of its relativeness, is changing skill without essence
Hold in art, when being also considered as the enforceable category of the present invention.
First embodiment
Below in conjunction with Fig. 2 A to Fig. 2 U to describe the semiconductor device with microprobe and the preparation method thereof of the present invention in detail
The generalized section of first embodiment.
As shown in Figure 2 A, it is provided that one has the substrate 20 of relative first surface 20a and second surface 20b, in this first
The first metal layer 201 is formed on the 20a of surface.
Also referring to Fig. 2 B, it continues from Fig. 2 A, forms the first resistance layer 202 on this first metal layer 201, this first resistance
Layer 202 has the first resistance layer perforate 2020 of this first metal layer 201 of exposed parts.
As shown in Figure 2 C, its technique continued from Fig. 2 B, remove the first metal layer in this first resistance layer perforate 2020
201, to constitute first line layer 201 ', and remove this first resistance layer 202.
As shown in Figure 2 D, its technique from Fig. 2 C that continues, in first surface 20a and this first line layer of this substrate 20
201 ' upper first dielectric layers 21 that formed, and this first dielectric layer 21 there is the first perforate exposing this first line layer 201 '
212。
As shown in Figure 2 E, its technique from Fig. 2 D that continues, on this first dielectric layer 21 with on this first line layer 201 '
The first conductive layer 214 is formed in the way of such as sputter copper/ni au.
As shown in Figure 2 F, its technique from Fig. 2 E that continues, with the plating of such as copper or electroplated aluminum on this first conductive layer 214
Mode form the second metal level 22.
As shown in Figure 2 G, its technique from Fig. 2 F that continues, on this second metal level 22, form this second gold medal of exposed parts
Belong to the second resistance layer 23 of layer 22.
As illustrated in figure 2h, its technique continued from Fig. 2 G, remove this second metal not covered by this second resistance layer 23
Layer 22 and first conductive layer 214, to constitute the second line layer 22 ' of this first line layer 201 ' of electric connection, then remove this
Two resistance layers 23.
As shown in figure 2i, its technique from Fig. 2 H that continues, in this first dielectric layer 21 and this upper formation of the second line layer 22 '
One insulating buffer layer 24, this insulating buffer layer 24 also has at least one insulating buffer layer exposed on this second line layer 22 ' and opens
Hole 242, wherein, the position of this insulating buffer layer perforate 242 not to should the position of the first perforate 212, and this insulating buffer layer
The material of 24 is BCB (benzocyclobutene, Benzocyclo-buthene), polyimides (PI) or polybenzoxazoles
(polybenzoxazole, PBO).
As shown in fig. 2j, its technique from Fig. 2 I that continues, with example on this insulating buffer layer 24 with this second line layer 22 '
As the mode of sputter copper/ni au forms the second conductive layer 244.
As shown in figure 2k, its technique from Fig. 2 J that continues, on this second conductive layer 244, form the 3rd gold medal with plating mode
Belong to layer 25.
As shown in figure 2l, its technique from Fig. 2 K that continues, on the 3rd metal level 25, form exposed parts the 3rd gold medal
Belong to the 3rd resistance layer 26 of layer 25.
As shown in figure 2m, its technique continued from Fig. 2 L, remove the part the 3rd not covered by the 3rd resistance layer 26
Metal level 25 and the second conductive layer 244, to constitute the tertiary circuit layer 25 ' being electrically connected with this second line layer 22 ', and expose portion
Divide this insulating buffer layer 24, then remove the 3rd resistance layer 26.
As shown in figure 2n, its technique from Fig. 2 M that continues, in this insulating buffer layer 24 and this upper formation of tertiary circuit layer 25 '
Second dielectric layer 27, this second dielectric layer 27 also has at least one the second perforate 272 exposing this tertiary circuit layer 25 ', wherein,
The position of this second perforate 272 be to should the position of the first perforate 212, and the position of this second perforate 272 is not to should be exhausted
Edge cushion perforate 242.
As shown in Figure 2 O, its technique from Fig. 2 N that continues, on this second dielectric layer 27 with this tertiary circuit layer 25 ' on
The such as mode of sputter copper/ni au forms the 3rd conductive layer 274.
As shown in figure 2p, its technique from Fig. 2 O that continues, on the 3rd conductive layer 274, form the 4th gold medal with plating mode
Belong to layer 28.
As shown in fig. 2q, its technique from Fig. 2 P that continues, on the 4th metal level 28, form the 4th resistance layer 29, and expose
The 4th metal level 28 in this second perforate 272.
As shown in Fig. 2 R, its technique from Fig. 2 Q that continues, on the 4th metal level 28, form microprobe with plating mode
30, and the material of this microprobe 30 is tungsten (W), rhenium (Re), beryllium (Be), palladium (Pd), titanium-tungsten (TiW), tungsten-rhenium alloy (ReW)
Or beallon (BeCu).
As shown in Fig. 2 S, its technique continued from Fig. 2 R, remove the 4th resistance layer 29.
As shown in Fig. 2 T, its technique from Fig. 2 S that continues, on this microprobe 30, form the 5th resistance layer 31.
As shown in Fig. 2 U, its technique continued from Fig. 2 T, remove the 4th metal level not covered by the 5th resistance layer 31
28 and the 3rd conductive layer 274, to constitute the 4th line layer 28 ', and remove the 5th resistance layer 31 so that this microprobe 30 exposes；
Also, the 4th line layer 28 ' is formed in this second perforate 272, and this microprobe 30 is electrically connected with the 4th line layer 28 '.
Second embodiment
Referring to Fig. 3, it is the generalized section of the second embodiment of the semiconductor device with microprobe of the present invention.
The present embodiment is with the difference of above-described embodiment: partly this first line layer 201 ' is along the semiconductor device sidepiece of this microprobe
(non-icon) stretches out, and can above be electrically connected with bonding wire 32, for external in this first line layer 201 ' exposing to air
It is electrically connected with.Similar as other related process, therefore repeat no more.
3rd embodiment
Referring to Fig. 4, it is the generalized section of the 3rd embodiment of the semiconductor device with microprobe of the present invention.
The present embodiment is with the difference of first embodiment: this substrate 20 also have run through this first surface 20a and second surface 20b and
It is electrically connected with the conductive through hole 203 of this first line layer 201 ', and with polyimides on the second surface 20b of this substrate 20
(PI) material forms polymer material layer 204, and this polymer material layer 204 has correspondence and exposes the of this conductive through hole 203
Three perforates 205, and soldering projection 206 is set on this conductive through hole 203 to be electrically connected with the external world.As for other related process
Similar, therefore repeat no more.
4th embodiment
Referring to Fig. 5, it is the generalized section of the 4th embodiment of the semiconductor device with microprobe of the present invention.
The present embodiment is with the difference of first embodiment: have two these insulating buffer layer perforates 242 in this insulating buffer layer 24, should
Tertiary circuit layer 25 ' connects this two insulating buffer layer perforates 242, and this microprobe 30 is electrically connected with this tertiary circuit layer 25 ',
At least one this second perforate 262 is between these two insulating buffer layer perforates 242 again, additionally, these two insulating buffer layer are opened
Hole 242 is relative to this asymmetric setting in the second perforate 272 ground, or, these two insulating buffer layer perforates 242 are relative to this
Second perforate 262 ground is symmetrical arranged (being symmetrical in microprobe 30, this situation of non-icon).Similar as other related process, therefore
Repeat no more.
The present invention also provides for a kind of semiconductor device with microprobe, including: substrate 20, first line layer 201 ',
One dielectric layer the 21, second line layer 22 ', insulating buffer layer 24, tertiary circuit layer the 25 ', second dielectric layer 27 and microprobe 30.
This substrate 20 has relative first surface 20a and second surface 20b, shape on the first surface 20a of this substrate 20
Become and have this first line layer 201 ', and be formed with first Jie on the first surface 20a of this substrate 20 and this first line layer 201 '
Electric layer 21, this first dielectric layer 21 also has the first perforate 212 exposing this first line layer 201 '.
This second line layer 22 ' be formed on this first dielectric layer 21 with in this first perforate 212, again in this first dielectric
With BCB (benzocyclobutene, Benzocyclo-buthene), polyimides (PI) or poly-on layer 21 and this second line layer 22 '
Benzoxazoles (polybenzoxazole, PBO) material is formed with this insulating buffer layer 24, and this insulating buffer layer 24 have to
The few one insulating buffer layer perforate 242 exposing this second line layer 22 '.
This tertiary circuit layer 25 ' is formed on this insulating buffer layer 24 with in this insulating buffer layer perforate 242 and exhausted in this
It is formed with this second dielectric layer 27 on edge cushion 24 and this tertiary circuit layer 25 ', and this second dielectric layer 27 has at least one
Expose the second perforate 272 of this tertiary circuit layer 25 ', and the position of this second perforate 272 is not to should insulating buffer layer perforate
242, and in the second perforate 272 of this second dielectric layer 27, form material for example, tungsten (W), rhenium (Re), beryllium (Be), palladium
(Pd), titanium-tungsten (TiW), tungsten-rhenium alloy (ReW) or this microprobe 30 of beallon (BeCu), and this microprobe 30 highlights
In this second dielectric layer 27.
According to the aforesaid semiconductor device with microprobe, the position of this insulating buffer layer perforate 242 is not to should
The position of one perforate 212, again the position of this second perforate 272 not to should insulating buffer layer perforate 242, but this first perforate
The position of 212 is to should the position of the second perforate 272.
In the semiconductor device with microprobe of the present invention, partly this first line layer 201 ' exposes to air, with
For external electric connection, this substrate 20 also have run through this first surface 20a and second surface 20b and be electrically connected with this first
The conductive through hole 203 of line layer 201 '.
According to front described semiconductor device, this insulating buffer layer perforate 242 has two these insulating buffer layer perforates 242,
And these two insulating buffer layer perforates 242 are to connect by this tertiary circuit layer 25 ', and this microprobe 30 is electrically connected with the 3rd
Line layer 25 ', and at least one this second perforate 272 is between these two insulating buffer layer perforates 242, these two buffer insulations
Layer perforate 242 is that this second perforate 272 ground asymmetric or symmetric is arranged relative to one.Above-described embodiment, this first metal layer
201, the material of the second metal level the 22, the 3rd metal level 25 and the 4th metal level 28 is copper or aluminum, this first dielectric layer 21 and should
The material of the second dielectric layer 27 is BCB (benzocyclobutene, BenzocycloBu-thene), polyimides (PI) or polyphenyl are disliked
(Polybenzoxazole, PBO), the material of this base material 20 is silicon (silicon), insulating barrier silicon (silicon on
Insulator, SOI), GaAs (GaAs), glass (glass), germanium (Ge), SiGe (SiGe) or carborundum (SiC).
In sum, the semiconductor device with microprobe of the present invention has an arcuate underlying structure of syllogic, and with
Material for example, BCB (benzocyclobutene, Benzocyclo-buthene), polyimides (PI) or polybenzoxazoles
The insulating buffer layer of (polybenzoxazole, PBO), therefore can subtract to provide preferable elastic force as buffering and cladding arcuate substrate
Subject to damage and the problem of elastic fatigue when few microprobe operation is mobile, and the microprobe of the present invention to have again fine pitch (little
In 40 microns) and vast number (more than 10000 microprobe numbers)；Additionally, the syllogic diapsida buffer structure such as Fig. 5 more enters one
Step provides preferably elastic force；Again the material on this microprobe surface can be wear-resisting titanium-tungsten (TiW), tungsten-rhenium alloy (ReW) or
Beallon (BeCu), to increase the service life of microprobe；Additionally, the structure of the semiconductor device with microprobe of the present invention
Make simple, and be prone to make, the shortcoming not having existing probe manufacturing: need to use semiconductor chip process and multi-layer ceramics simultaneously
Plate technique, causes that integrated artistic is more complicated, yield is poor and Production Time is elongated, and causes the problems such as cost raising.
Effect of those embodiments above-mentioned only illustrative present invention, not for limiting the present invention, any this area
Those embodiments above-mentioned all can be modified under the spirit and the scope of the present invention and change by technical staff.Additionally,
The quantity of the assembly in those embodiments above-mentioned is only illustrative, the most non-for limiting the present invention.Therefore the present invention
Rights protection scope should be as listed by claims.
Claims (24)
1. there is a preparation method for the semiconductor device of microprobe, including:
First line layer is formed on the first surface of a substrate with relative first surface and second surface；
Forming the first dielectric layer on first surface and this first line layer of this substrate, this first dielectric layer also has and exposes this
First perforate of first line layer；
Formed the second line layer on this first dielectric layer with in this first perforate；
Forming an insulating buffer layer on this first dielectric layer with this second line layer, this insulating buffer layer also has outside at least one
Reveal the insulating buffer layer perforate of this second line layer；
Formed tertiary circuit layer on this insulating buffer layer with in this insulating buffer layer perforate；
Forming the second dielectric layer on this insulating buffer layer and this tertiary circuit layer, this second dielectric layer also has and exposes the 3rd
At least the one of line layer second perforate；And
In the second perforate of this second dielectric layer, form microprobe, and this microprobe protrudes from this second dielectric layer.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this first line
Layer, this second line layer or this tertiary circuit layer are to be formed by plating mode.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this microprobe is to borrow
Formed by plating mode.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this insulating buffer layer
The position of perforate is not to should the position of the first perforate.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this second perforate
Position is not to should insulating buffer layer perforate.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this first perforate
Position is to should the position of the second perforate.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that partly this First Line
Road floor stretches out along the semiconductor device sidepiece of this microprobe, for external electric connection.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this substrate also has
Run through this first surface and second surface and be electrically connected with the conductive through hole of this first line layer.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this insulating buffer layer
Material be BCB, polyimides or polybenzoxazoles.
The preparation method of the semiconductor device with microprobe the most according to claim 1, it is characterised in that this microprobe
Material is titanium-tungsten, tungsten-rhenium alloy or beallon.
The preparation method of 11. semiconductor devices with microprobe according to claim 1, it is characterised in that this microprobe
Material is tungsten, rhenium, beryllium or palladium.
The preparation method of 12. semiconductor devices with microprobe according to claim 1, it is characterised in that this preparation method is also wrapped
Include in this second perforate, be formed with the 4th line layer, and this microprobe is electrically connected with the 4th line layer.
The preparation method of 13. semiconductor devices with microprobe according to claim 1, it is characterised in that this buffer insulation
Layer has two these insulating buffer layer perforates, and these two insulating buffer layer perforates are to connect by this tertiary circuit layer, and is somebody's turn to do
Microprobe is electrically connected with this tertiary circuit layer.
14. 1 kinds of semiconductor devices with microprobe, including:
Substrate, has relative first surface and second surface；
First line layer, is formed on the first surface of this substrate；
First dielectric layer, is formed at the first surface of this substrate with on this first line layer, and has and expose this first line layer
The first perforate；
Second line layer, be formed on this first dielectric layer with in this first perforate；
Insulating buffer layer, is formed on this first dielectric layer and this second line layer, and has at least one and expose this second circuit
The insulating buffer layer perforate of layer；
Tertiary circuit layer, be formed on this insulating buffer layer with in this insulating buffer layer perforate；
Second dielectric layer, is formed on this insulating buffer layer and this tertiary circuit layer, and has at least one and expose this tertiary circuit
Second perforate of layer；And
Microprobe, is located in the second perforate of this second dielectric layer, and protrudes from this second dielectric layer.
15. semiconductor devices with microprobe according to claim 14, it is characterised in that this insulating buffer layer perforate
Position not to should the position of the first perforate.
16. semiconductor devices with microprobe according to claim 14, it is characterised in that the position of this second perforate
Not to should insulating buffer layer perforate.
17. semiconductor devices with microprobe according to claim 14, it is characterised in that the position of this first perforate
It is to should the position of the second perforate.
18. semiconductor devices with microprobe according to claim 14, it is characterised in that partly this first line layer
Expose to air, for external electric connection.
19. semiconductor devices with microprobe according to claim 14, it is characterised in that this substrate also has and runs through
This first surface and second surface and be electrically connected with the conductive through hole of this first line layer.
20. semiconductor devices with microprobe according to claim 14, it is characterised in that the material of this insulating buffer layer
Matter is BCB, polyimides or polybenzoxazoles.
21. semiconductor devices with microprobe according to claim 14, it is characterised in that the material of this microprobe is
Titanium-tungsten, tungsten-rhenium alloy or beallon.
22. semiconductor devices with microprobe according to claim 14, it is characterised in that the material of this microprobe is
Tungsten, rhenium, beryllium or palladium.
23. semiconductor devices with microprobe according to claim 14, it is characterised in that this insulating buffer layer has
Two these insulating buffer layer perforates, and these two insulating buffer layer perforates are to connect by this tertiary circuit layer, and this microprobe
It is electrically connected with this tertiary circuit layer.
24. semiconductor devices with microprobe according to claim 14, it is characterised in that this semiconductor device also wraps
Include in this second perforate, be formed with the 4th line layer, and this microprobe is electrically connected with the 4th line layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101134234A TWI447399B (en) | 2012-09-19 | 2012-09-19 | Semiconductor device having micro-probe and fabrication method thereof |
| TW101134234 | 2012-09-19 |
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| CN103675376A CN103675376A (en) | 2014-03-26 |
| CN103675376B true CN103675376B (en) | 2016-12-21 |
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| WO2015152716A1 (en) * | 2014-04-04 | 2015-10-08 | Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno | Actuator module for actuating a load |
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|---|---|---|---|---|
| CN1693181A (en) * | 2004-03-11 | 2005-11-09 | 帕洛阿尔托研究中心公司 | Integrated driver electronics for mems device using high voltage thin film transistors |
| US8001685B2 (en) * | 2005-08-19 | 2011-08-23 | Byung Ho Jo | Method for manufacturing probe card needles |
| CN102398886A (en) * | 2010-09-15 | 2012-04-04 | 矽品精密工业股份有限公司 | Packaged structure with micro-electromechanical device and manufacture method thereof |
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| US6807734B2 (en) * | 1998-02-13 | 2004-10-26 | Formfactor, Inc. | Microelectronic contact structures, and methods of making same |
| US20060051948A1 (en) * | 2003-02-04 | 2006-03-09 | Microfabrica Inc. | Microprobe tips and methods for making |
| KR100915326B1 (en) * | 2007-10-22 | 2009-09-03 | 주식회사 파이컴 | Method of manufacturing an apparatus for inspecting electric condition |
| WO2010011627A1 (en) * | 2008-07-23 | 2010-01-28 | Meadwestvaco Corporation | Paperboard bin-cube |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1693181A (en) * | 2004-03-11 | 2005-11-09 | 帕洛阿尔托研究中心公司 | Integrated driver electronics for mems device using high voltage thin film transistors |
| US8001685B2 (en) * | 2005-08-19 | 2011-08-23 | Byung Ho Jo | Method for manufacturing probe card needles |
| CN102398886A (en) * | 2010-09-15 | 2012-04-04 | 矽品精密工业股份有限公司 | Packaged structure with micro-electromechanical device and manufacture method thereof |
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| CN103675376A (en) | 2014-03-26 |
| TWI447399B (en) | 2014-08-01 |
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