TW201413250A - Semiconductor device having micro-probe and fabrication method thereof - Google Patents

Abstract

The invention provides a semiconductor device having a micro-probe and a fabrication method thereof, the semiconductor device comprising a substrate having opposing first and second surfaces; a first circuit layer formed on the first surface of the substrate; a first dielectric layer formed on the first surface of the substrate and the first circuit layer and having a first opening for exposing the first circuit layer therefrom; a second circuit layer formed on the first dielectric layer and in the first opening; an insulating buffering layer formed on the first dielectric layer and the second circuit layer and having at least an insulating buffering opening for exposing the second circuit layer therefrom; a third circuit layer formed on the insulating buffering layer and in the insulating buffering layer opening; a second dielectric layer formed on the insulating buffering layer and the third circuit layer and having at least a second opening for exposing the third circuit layer therefrom; and a micro-probe disposed in the second opening of the second dielectric layer, thereby providing the micro-probe with buffer against external forces and thus preventing elasticity fatigue.

Description

Semiconductor device with micro-probe and its preparation method

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having an elastic fatigue resistant microprobe and a method of fabricating the same.

Nowadays, with the advancement of technology, electronic products manufacturers have developed various types of test probe cards for testing electronic products. Conventional probe cards are manufactured with limited probe sizes and high manufacturing costs, so many bottlenecks have to be overcome in the process of making probes. At present, the size trend of semiconductor wafers tends to be miniaturized and the output contacts of the semiconductor wafers are more and more, and the test probe structures are all wired by a small probe. Therefore, it is necessary to continuously improve and overcome the probes. The process technology of the structure cooperates with the miniaturized semiconductor wafer and overcomes the problem that the conventional probe structure is prone to fatigue during operation and the size of the probe is limited to conform to the trend of modern technology products.

U.S. Patent No. 8001685B2 discloses a method of making a probe card. Please refer to Figures 1A to 1K for a schematic cross-sectional view of a conventional probe card.

As shown in FIGS. 1A to 1C, a multilayer ceramic plate 10 is provided, and a first conductive layer 12 is formed on a top surface of the multilayer ceramic plate 10, and a first resist layer 14 is formed on the first conductive layer 12. And removing a portion of the first resist layer 14 from the first conductive layer 12, and exposing a portion of the first conductive layer 12, and then removing the exposed portion of the first conductive layer 12, and then removing For the first resist layer 14, the above process is defined as step 1.

As shown in FIGS. 1A' to 1C', a semiconductor wafer 10' is provided, and a photoresist layer 12' is formed on the top surface of the semiconductor wafer 10', and the photoresist layer 12' is patterned to form the semiconductor wafer 10. The top surface of the 'top surface is formed with a plurality of openings 121'. Next, each of the openings 121' is filled with a polymer elastic body 14', and the above process is defined as step 2.

As shown in FIG. 1D, the polymeric elastomer 14' having the structure of the first embodiment of the step 2C is attached to the structure of the first embodiment of the first embodiment, so that the polymeric elastomer 14' is disposed on the multilayer ceramic. The top surface of the board 10, and the polymeric elastomer 14' has a first opening 122 for exposing the first conductive layer 12 of the top surface of the multilayer ceramic board 10.

As shown in FIG. 1E, a first metal layer 15 is formed on the first conductive layer 12, and a bottom layer of the first metal layer 15 is a nickel layer 151, and a top layer is a gold layer 152.

As shown in Fig. 1F, a second conductive layer 16 is formed on the polymer elastic body 14' and the gold layer 152, and a second resist layer 141 is provided on the second conductive layer 16.

As shown in FIG. 1G, the second resist layer 141 is patterned to form an exposed portion of the second conductive layer 16 and a second metal layer 18 is formed on the second conductive layer 16.

As shown in FIG. 1H, a third resist layer 142 is disposed on the second resist layer 141 and the second metal layer 18, and the third resist layer 142 is patterned to form an opening exposing the second metal layer 18. Next, a third metal layer 181 is formed on the second metal layer 18.

As shown in FIG. 1I, the third resist layer 142 and the third metal layer A fourth resist layer 143 is disposed on the 181, and the fourth resist layer 143 is patterned to form an opening exposing the third metal layer 181. Then, a fourth metal layer 182 is formed on the third metal layer 181.

As shown in FIG. 1J, a fifth resist layer 144 is disposed on the fourth resist layer 143 and the fourth metal layer 182, and the fourth resist layer 143 is patterned to form an opening exposing the fourth metal layer 182. Next, a probe bump 183 is formed on the fourth metal layer 182.

As shown in FIG. 1K, the second resist layer 141, the third resist layer 142, the fourth resist layer 143, and the fifth resist layer 144 are removed to complete the probe card.

However, the conventional probe card manufacturing method requires the structure of the step 1 to be transferred to the structure of the step 2, and the semiconductor wafer process and the multilayer ceramic plate process are used, resulting in a complicated overall process, a poor yield, and an elongated production time, resulting in cost. Moreover, the conventional probe card has a small structure and a partial suspension of the probe base without buffer layer protection, so that elastic fatigue or damage is easily generated when the operation is moved.

Therefore, how to overcome various problems of the prior art is an important issue.

In order to solve the problems of the above-mentioned prior art, the present invention discloses a semiconductor device having a micro-probe, comprising: a substrate having opposite first and second surfaces; and a first circuit layer formed on the substrate a first dielectric layer formed on the first surface of the substrate and the first circuit layer, and having a first opening exposing the first circuit layer; the second circuit layer is formed On the first dielectric layer and the first opening; The edge buffer layer is formed on the first dielectric layer and the second circuit layer, and has at least one insulating buffer layer opening exposing the second circuit layer; and a third circuit layer is formed on the insulating buffer layer And the second dielectric layer is formed on the insulating buffer layer and the third circuit layer, and has at least one second opening exposing the third circuit layer; and the micro-exploration The pin is disposed in the second opening of the second dielectric layer and protrudes from the second dielectric layer.

The invention further provides a method for fabricating a semiconductor device having a microprobe, comprising: forming a first wiring layer on a first surface of a substrate having a first surface and a second surface; and a first surface of the substrate Forming a first dielectric layer on the first circuit layer, the first dielectric layer having a first opening exposing the first circuit layer; forming a second circuit layer on the first dielectric layer and the first Forming an insulating buffer layer on the first dielectric layer and the second circuit layer, the insulating buffer layer having at least one insulating buffer layer opening exposing the second circuit layer; forming a third line a layer is formed in the insulating buffer layer and the insulating buffer layer; a second dielectric layer is formed on the insulating buffer layer and the third circuit layer, and the second dielectric layer has at least one exposed third line a second opening of the layer; and forming a micro-probe in the second opening of the second dielectric layer, and the micro-probe protrudes from the second dielectric layer.

In the above method of fabricating a micro-probe semiconductor device, the first wiring layer, the second wiring layer, the third wiring layer, and the micro-probe are formed by electroplating.

In the above method for fabricating a semiconductor device having a micro-probe, the position of the opening of the insulating buffer layer is not corresponding to the position of the first opening, and the second opening The position of the hole is not corresponding to the opening of the insulating buffer layer, and the position of the first opening corresponds to the position of the second opening.

In the above method for fabricating a micro-probe semiconductor device, the insulating buffer layer has two openings of the insulating buffer layer, and the insulating buffer layer opening is connected by the third circuit layer, the micro-probe system The third circuit layer is electrically connected.

In the above method for fabricating a semiconductor device having a micro-probe, a fourth wiring layer is formed in the second opening, and the micro-probe is electrically connected to the fourth wiring layer.

In the above method for fabricating a semiconductor device having a microprobe, the material of the insulating buffer layer is BCB (Benzocyclo-buthene), polybenzamine (PI) or polybenzoxazole (PBO).

In the above method for fabricating a semiconductor device having a microprobe, the material of the microprobe is tungsten (W), bismuth (Re), beryllium (Be), palladium (Pd), titanium tungsten alloy (TiW), tantalum tungsten. Alloy (ReW) or beryllium copper alloy (BeCu).

According to the above description, the semiconductor device with the micro-probe has a three-stage arch type base structure and an insulating buffer layer to reduce the problem that the micro-probe structure is susceptible to elastic fatigue or damage during operation, and the present invention further High-density (eg, less than 40 micrometers between microprobes) and miniaturized microprobe structures can be fabricated to increase the test area and increase the number of test contacts (greater than 10,000 microprobes).

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can easily Other advantages and effects of the present invention are understood.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "top", "bottom", "one" and "two" are used in this description for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

First embodiment

Hereinafter, a cross-sectional view of a first embodiment of a semiconductor device having a microprobe according to the present invention and a method of manufacturing the same will be described in detail with reference to FIGS. 2A to 2U.

As shown in FIG. 2A, a substrate 20 having a first surface 20a and a second surface 20b opposite thereto is provided, and a first metal layer 201 is formed on the first surface 20a.

Referring to FIG. 2B , a first resist layer 202 is formed on the first metal layer 201 , and the first resist layer 202 has an exposed portion of the first resist layer of the first metal layer 201 . Hole 2020.

As shown in FIG. 2C, the first metal layer 201 in the first barrier opening 2020 is removed from the process of FIG. 2B to form the first wiring layer 201', and the first resistor is removed. Layer 202.

As shown in FIG. 2D, the first dielectric layer 21 is formed on the first surface 20a of the substrate 20 and the first circuit layer 201', and the first dielectric layer 21 is connected to the process of the second embodiment. And having a first opening 212 exposing the first circuit layer 201'.

As shown in FIG. 2E, the first conductive layer is formed on the first dielectric layer 21 and the first wiring layer 201' by, for example, sputtering copper/nickel/gold. 214.

As shown in FIG. 2F, the second metal layer 22 is formed on the first conductive layer 214 by, for example, copper plating or aluminum plating, as shown in FIG.

As shown in FIG. 2G, the second resist layer 23 of the second metal layer 22 is exposed on the second metal layer 22 in the process of the second F-layer.

As shown in FIG. 2H, the second metal layer 22 and the first conductive layer 214 not covered by the second resist layer 23 are removed from the process of FIG. 2G to form an electrical connection. The second circuit layer 22' of the circuit layer 201' is removed, and the second resist layer 23 is removed.

As shown in FIG. 2I, an insulating buffer layer 24 is formed on the first dielectric layer 21 and the second wiring layer 22', and the insulating buffer layer 24 has at least one exposed portion. The insulating buffer layer opening 242 is disposed on the second circuit layer 22 ′, wherein the insulating buffer layer opening 242 is located at a position that does not correspond to the first opening 212, and the insulating buffer layer 24 is made of BCB. (Benzocyclo-buthene), polybenzamine (PI) or polybenzoxazole (PBO).

As shown in Fig. 2J, the second conductive layer 244 is formed on the insulating buffer layer 24 and the second wiring layer 22' by, for example, sputtering copper/nickel/gold, as shown in Fig. 2J.

As shown in FIG. 2K, the third metal layer 25 is formed on the second conductive layer 244 by electroplating from the process of FIG. 2J.

As shown in FIG. 2L, the third resist layer 26 of the third metal layer 25 is exposed on the third metal layer 25 in the process of the second FIG.

As shown in FIG. 2M, the third metal layer 25 and the second conductive layer 244 not covered by the third resist layer 26 are removed from the process of the second embodiment to form an electrical connection. The third circuit layer 25' of the second circuit layer 22' exposes a portion of the insulating buffer layer 24, and the third resist layer 26 is removed.

As shown in FIG. 2N, the second dielectric layer 27 is formed on the insulating buffer layer 24 and the third wiring layer 25', and the second dielectric layer 27 has at least one. The second opening 272 of the third circuit layer 25' is exposed, wherein the position of the second opening 272 is corresponding to the position of the first opening 212, and the position of the second opening 272 is not correspondingly insulated. Buffer layer opening 242.

As shown in FIG. 20, the process is continued from the process of FIG. 2N, and a third conductive layer is formed on the second dielectric layer 27 and the third circuit layer 25' by, for example, sputtering copper/nickel/gold. 274.

As shown in FIG. 2P, the process of FIG. 20 is continued, and a fourth metal layer 28 is formed on the third conductive layer 274 by electroplating.

As shown in Figure 2Q, the process continues from the 2P diagram, in the fourth A fourth resist layer 29 is formed on the metal layer 28, and the fourth metal layer 28 in the second opening 272 is exposed.

As shown in FIG. 2R, the micro-probe 30 is formed by electroplating on the fourth metal layer 28, and the material of the micro-probe 30 is tungsten (W), 铼 ( Re), beryllium (Be), palladium (Pd), titanium tungsten alloy (TiW), tantalum tungsten alloy (ReW) or beryllium copper alloy (BeCu).

As shown in FIG. 2S, the fourth resist layer 29 is removed from the process of the 2R pattern.

As shown in FIG. 2T, the fifth resist layer 31 is formed on the microprobe 30 by the process of the second S-picture.

As shown in FIG. 2U, the fourth metal layer 28 and the third conductive layer 274 not covered by the fifth resist layer 31 are removed from the process of FIG. 2T to form a fourth circuit layer 28'. And removing the fifth resist layer 31 to expose the micro probe 30; further, the fourth circuit layer 28' is formed in the second opening 272, and the micro probe 30 is electrically connected to the first Four circuit layers 28'.

Second embodiment

Please refer to FIG. 3, which is a cross-sectional view showing a second embodiment of a semiconductor device having a microprobe according to the present invention. The difference between this embodiment and the above embodiment is that a portion of the first circuit layer 201' extends outwardly along a side portion (not shown) of the semiconductor device of the micro-probe, and is exposed to the first circuit layer exposed to the atmosphere. 201' is electrically connected to the bonding wire 32 for external electrical connection. As for other related processes, they are similar, so they will not be described again.

Third embodiment

Please refer to FIG. 4, which is a semiconductor device with a microprobe according to the present invention. A schematic cross-sectional view of a third embodiment. The difference between the present embodiment and the first embodiment is that the substrate 20 has a conductive via 203 extending through the first surface 20a and the second surface 20b and electrically connected to the first circuit layer 201 ′, and the substrate 20 is On the second surface 20b, a polymer material layer 204 is formed by using a polyamidamine (PI) material, and the polymer material layer 204 has a third opening 205 corresponding to the conductive via 203, and the conductive via hole is formed in the conductive via hole. A solder bump 206 is disposed on the 203 to be electrically connected to the outside. As for other related processes, they are similar, so they will not be described again.

Fourth embodiment

Please refer to FIG. 5, which is a cross-sectional view showing a fourth embodiment of a semiconductor device having a microprobe according to the present invention. The difference between this embodiment and the first embodiment is that the insulating buffer layer 24 has two insulating buffer layer openings 242, and the third circuit layer 25' connects the insulating buffer layer openings 242, and the micro-exploration The pin 30 is electrically connected to the third circuit layer 25', and at least one of the second openings 262 is located between the insulating buffer layer openings 242. Further, the insulating buffer layer opening 242 is opposite to the insulating buffer layer opening 242. The second opening 272 is asymmetrically disposed, or the insulating buffer opening 242 is symmetrically disposed with respect to the second opening 262 (symmetric to the microprobe 30, which is not shown). As for other related processes, they are similar, so they will not be described again.

The present invention further provides a semiconductor device having a micro-probe comprising: a substrate 20, a first wiring layer 201', a first dielectric layer 21, a second wiring layer 22', an insulating buffer layer 24, and a third wiring layer 25. ', second dielectric layer 27 and microprobe 30.

The substrate 20 has opposite first and second surfaces 20a, 20b, The first circuit layer 201 ′ is formed on the first surface 20 a of the substrate 20 , and the first surface 20 a of the substrate 20 and the first circuit layer 201 ′ are formed with a first dielectric layer 21 , the first The dielectric layer 21 has a first opening 212 exposing the first circuit layer 201'.

The second circuit layer 22' is formed on the first dielectric layer 21 and the first opening 212, and the BCB (Benzocyclo-) on the first dielectric layer 21 and the second circuit layer 22'. The insulating buffer layer 24 is formed of buthene), polybenzamine (PI) or polybenzoxazole (PBO), and the insulating buffer layer 24 has at least one insulating buffer layer exposing the second wiring layer 22'. Opening 242.

The third circuit layer 25 ′ is formed on the insulating buffer layer 24 and the insulating buffer layer opening 242 , and the second dielectric layer is formed on the insulating buffer layer 24 and the third circuit layer 25 ′. 27, and the second dielectric layer 27 has at least one second opening 272 exposing the third circuit layer 25', and the position of the second opening 272 is not corresponding to the insulating buffer opening 242, and The second opening 272 of the second dielectric layer 27 is made of a material such as tungsten (W), ruthenium (Re), beryllium (Be), palladium (Pd), titanium tungsten alloy (TiW), or tantalum tungsten alloy (ReW). Or the micro-probe 30 of beryllium copper alloy (BeCu), and the micro-probe 30 protrudes from the second dielectric layer 27.

According to the foregoing semiconductor device having a micro-probe, the position of the insulating buffer layer opening 242 is not corresponding to the position of the first opening 212, and the position of the second opening 272 is not corresponding to the opening of the insulating buffer layer. 242, but the position of the first opening 212 corresponds to the position of the second opening 272.

In the semiconductor device with micro-probe of the present invention, part of the first The circuit layer 201 is exposed to the atmosphere for external electrical connection. The substrate 20 has a conductive via 203 extending through the first surface 20a and the second surface 20b and electrically connected to the first wiring layer 201'.

According to the semiconductor device described above, the insulating buffer layer opening 242 has two insulating buffer layer openings 242, and the insulating buffer layer opening 242 is connected by the third circuit layer 25'. The probe 30 is electrically connected to the third circuit layer 25 ′, and at least one of the second openings 272 is located between the insulating buffer layer openings 242 , and the insulating buffer layer opening 242 is opposite to the one. The second opening 272 is asymmetrically or symmetrically disposed. In the above embodiment, the materials of the first metal layer 201, the second metal layer 22, the third metal layer 25, and the fourth metal layer 28 are copper or aluminum, and the first dielectric layer 21 and the second dielectric layer The material of 27 is BCB (BenzocycloBu-thene), polyamidamine (PI) or polybenzoxazole (PBO), and the material of the substrate 20 is silicon, silicon on insulator, SOI), gallium arsenide (GaAs), glass, germanium (Ge), germanium (SiGe) or tantalum carbide (SiC).

In summary, the semiconductor device with microprobe of the present invention has a three-stage arch type base structure and is made of, for example, BCB (Benzocyclo-buthene), poly-liminamide (PI) or polybenzoxazole. The insulating buffer layer of polybenzoxazole (PBO) serves as a cushioning and covering arched substrate to provide better elastic force, thereby reducing the problem of damage and elastic fatigue when the microprobe is moved, and the microprobe of the present invention It has a fine pitch (less than 40 microns) and a large number (more than 10,000 micro-probes); in addition, the three-segment double-bow buffer structure as shown in Figure 5 provides further Good elasticity; the surface of the microprobe can be made of wear-resistant titanium tungsten alloy (TiW), tantalum tungsten alloy (ReW) or beryllium copper alloy (BeCu) to increase the service life of the microprobe; The semiconductor device with micro-probe of the invention has simple structure and is easy to manufacture, and has the disadvantages of the conventional probe fabrication: the semiconductor wafer process and the multi-layer ceramic plate process are required at the same time, resulting in a complicated overall process and poor yield. The production time is lengthened, resulting in problems such as increased costs.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10‧‧‧Multilayer ceramic plates

10'‧‧‧Semiconductor wafer

12, 214‧‧‧ first conductive layer

122, 212‧‧‧ first opening

12'‧‧‧Light barrier

121’‧‧‧ openings

14, 202‧‧‧ first resistance layer

141, 23‧‧‧ second resistive layer

142, 26‧‧‧ third resistive layer

143, 29‧‧‧ fourth resistive layer

144, 31‧‧‧ fifth resistive layer

14'‧‧‧Polymer elastomer

15‧‧‧First metal layer

151‧‧‧ Nickel layer

152‧‧‧ gold layer

16, 244‧‧‧ second conductive layer

18‧‧‧Second metal layer

181‧‧‧ Third metal layer

182‧‧‧ fourth metal layer

183‧‧‧Probe bumps

20‧‧‧Substrate

20a‧‧‧ first surface

20b‧‧‧second surface

201‧‧‧First metal layer

201’‧‧‧First circuit layer

2020‧‧‧First barrier opening

203‧‧‧ conductive through hole

204‧‧‧ polymer material layer

205‧‧‧ third opening

206‧‧‧welding bumps

21‧‧‧First dielectric layer

22‧‧‧Second metal layer

22’‧‧‧Second circuit layer

24‧‧‧Insulation buffer

242‧‧‧Insulation buffer opening

25‧‧‧ Third metal layer

25’‧‧‧ third circuit layer

27‧‧‧Second dielectric layer

272‧‧‧Second opening

274‧‧‧ Third conductive layer

28‧‧‧Fourth metal layer

28’‧‧‧fourth circuit layer

30‧‧‧Microprobe

32‧‧‧welding line

1A to 1K are schematic cross-sectional views showing a method of manufacturing a conventional microprobe card, and FIGS. 1A to 1C are schematic cross-sectional views showing a conventional microprobe card in the first step, and FIGS. 1A' to 1C' are shown. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view showing a second embodiment of a semiconductor device having a microprobe according to the present invention; and FIG. 3 is a schematic view of the first embodiment of the present invention; A cross-sectional view of a second embodiment of a semiconductor device having a microprobe and a method for fabricating the same; and FIG. 4 is a cross-sectional view showing a third embodiment of the semiconductor device having the microprobe of the present invention and a method of fabricating the same; Fig. 5 is a schematic cross-sectional view showing a fourth embodiment of a semiconductor device having a microprobe according to the present invention and a method of manufacturing the same.

20‧‧‧Substrate

21‧‧‧First dielectric layer

212‧‧‧First opening

214‧‧‧First conductive layer

22’‧‧‧Second circuit layer

24‧‧‧Insulation buffer

242‧‧‧Insulation buffer opening

244‧‧‧Second conductive layer

25’‧‧‧ third circuit layer

27‧‧‧Second dielectric layer

272‧‧‧Second opening

28’‧‧‧fourth circuit layer

30‧‧‧Microprobe

Claims (24)

A method of fabricating a semiconductor device having a microprobe, comprising: forming a first wiring layer on a first surface of a substrate having a first surface and a second surface; and forming a first surface on the first surface of the substrate Forming a first dielectric layer on the circuit layer, the first dielectric layer having a first opening exposing the first circuit layer; forming a second circuit layer on the first dielectric layer and the first opening Forming an insulating buffer layer on the first dielectric layer and the second circuit layer, the insulating buffer layer having at least one insulating buffer layer opening exposing the second circuit layer; forming a third circuit layer on the insulating layer Forming a second dielectric layer on the insulating buffer layer and the third circuit layer, the second dielectric layer having at least one second exposed the third circuit layer Opening a hole; and forming a micro-probe in the second opening of the second dielectric layer, and the micro-probe protrudes from the second dielectric layer. The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the first circuit layer, the second circuit layer or the third circuit layer is formed by electroplating. The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the microprobe is formed by electroplating. The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the position of the opening of the insulating buffer layer is not corresponding to the position of the first opening. The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the position of the second opening is not corresponding to the opening of the insulating buffer layer. The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the position of the first opening corresponds to a position of the second opening. The method of manufacturing a semiconductor device with a microprobe according to claim 1, wherein a portion of the first circuit layer extends outward along a side of the semiconductor device of the micro-probe for external electrical connection. . The method of fabricating a semiconductor device having a micro-probe according to claim 1, wherein the substrate has a conductive via extending through the first surface and the second surface and electrically connecting the first wiring layer. The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the insulating buffer layer is made of BCB (Benzocyclo-buthene), polybenzamine (PI) or polybenzoxazole ( Polybenzoxazole, PBO). The method of manufacturing a semiconductor device with a microprobe according to claim 1, wherein the material of the microprobe is titanium tungsten alloy (TiW), tantalum tungsten alloy (ReW) or beryllium copper alloy (BeCu). . The method of manufacturing a semiconductor device having a microprobe according to the first aspect of the invention, wherein the material of the microprobe is tungsten (W) or germanium. (Re), bismuth (Be) or palladium (Pd). The method for fabricating a semiconductor device having a microprobe according to claim 1, wherein the fourth opening is formed in the second opening, and the micro probe is electrically connected to the fourth circuit layer. . The method of fabricating a semiconductor device having a microprobe according to claim 1, wherein the insulating buffer layer has two openings of the insulating buffer layer, and wherein the insulating buffer layer is opened by the third The circuit layers are connected, and the micro probes are electrically connected to the third circuit layer. A semiconductor device having a micro-probe includes: a substrate having opposite first and second surfaces; a first circuit layer formed on the first surface of the substrate; and a first dielectric layer formed On the first surface of the substrate and the first circuit layer, and having a first opening for exposing the first circuit layer; the second circuit layer is formed on the first dielectric layer and the first opening An insulating buffer layer is formed on the first dielectric layer and the second circuit layer, and has at least one insulating buffer layer opening exposing the second circuit layer; and a third circuit layer is formed on the insulating layer a buffer layer is formed in the opening of the insulating buffer layer; a second dielectric layer is formed on the insulating buffer layer and the third circuit layer, and has at least one second opening exposing the third circuit layer; a microprobe disposed in the second opening of the second dielectric layer, and Highlighting the second dielectric layer. The semiconductor device with a microprobe according to claim 14, wherein the position of the opening of the insulating buffer layer is not corresponding to the position of the first opening. The semiconductor device with a microprobe according to claim 14, wherein the position of the second opening is not corresponding to the opening of the insulating buffer layer. The semiconductor device with a microprobe according to claim 14, wherein the position of the first opening corresponds to the position of the second opening. The semiconductor device with a microprobe according to claim 14, wherein a part of the first circuit layer is exposed to the atmosphere for external electrical connection. The semiconductor device with a microprobe according to claim 14, wherein the substrate has a conductive via extending through the first surface and the second surface and electrically connecting the first wiring layer. The semiconductor device with a microprobe according to claim 14, wherein the insulating buffer layer is made of BCB (Benzocyclo-buthene), polyimide (PI) or polybenzoxazole. PBO). The semiconductor device with a microprobe according to claim 14, wherein the material of the microprobe is titanium tungsten alloy (TiW), tantalum tungsten alloy (ReW) or beryllium copper alloy (BeCu). A semiconductor package with a microprobe as described in claim 14 The material of the microprobe is tungsten (W), ruthenium (Re), beryllium (Be) or palladium (Pd). The semiconductor device with a microprobe according to claim 14, wherein the insulating buffer layer has two openings of the insulating buffer layer, and the insulating buffer layer is opened by the third circuit layer Connected, and the micro probe is electrically connected to the third circuit layer. The semiconductor device with a microprobe according to claim 14, wherein a fourth circuit layer is formed in the second opening, and the micro probe is electrically connected to the fourth circuit layer.