CN103659574B - Observe the method to metallic corrosion situation in chemical mechanical milling tech - Google Patents
Observe the method to metallic corrosion situation in chemical mechanical milling tech Download PDFInfo
- Publication number
- CN103659574B CN103659574B CN201310630329.1A CN201310630329A CN103659574B CN 103659574 B CN103659574 B CN 103659574B CN 201310630329 A CN201310630329 A CN 201310630329A CN 103659574 B CN103659574 B CN 103659574B
- Authority
- CN
- China
- Prior art keywords
- ion trap
- metal wire
- different
- trap
- described metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Analysing Materials By The Use Of Radiation (AREA)
Abstract
The present invention provides a kind of and observes in chemical mechanical milling tech the method to metallic corrosion situation, being applied in the different semiconductor device structure of ion trap concentration, described method comprises: arrange the ion trap that some have same ionic species and ionic concn on the cutting groove of a wafer; The metal wire formed after connecting two cmps by two contact holes above ion trap described in each; The order that ion trap described in each is successively decreased according to the distance between described metal wire is arranged; By microscope, described metal wire surface is observed. The inventive method can adopt electron microscope directly to observe the interconnection structure formed when different chemical mechanical milling tech, can directly find the corrosion condition of different distance metal wire in the ion trap of different ions concentration, and the corrosion distribution situation of a complete wafer can be obtained by observing the different positions of wafer, and then it is convenient to technique be carried out fast and effective optimization.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to and a kind of observe in chemical mechanical milling tech the method to metallic corrosion situation.
Background technology
More than one hundred million devices are focused on a silicon chip by the operation that advanced integrated circuit fabrication process generally all comprises several hundred steps, and these operations are broadly divided into six big techniques, are photoetching, etching, cleaning, cmp, ion implantation and film growth respectively.
Owing to the requirement of device electric property constantly promotes, rear section circuit be formed in 130nm after technique generally all adopt metallic copper interconnection process, and copper lines figure is formed after have passed through chemical mechanical milling tech.
The principle of cmp is that the wafer by needing grinding is in certain overdraft, and under coordinating the effect of the mixture being made up of ultra-fine grain, chemical oxidizing agent and liquor, the surface being polished is rotated relative to a grinding pad, in rotary movement, by the mechanical grinding of abrasive particle and the corrosive nature of chemical oxidizing agent, crystal column surface material is removed, obtain bright and clean surface. But, in the process that copper surface is ground, if the situation of lapping liquid (such as acid-basicity, concentration and temperature etc.) changes, all can cause the defect of various metallic corrosion, thus affect the electric property of device.
Often there is the device architecture of multiple different ions trap concentration on a single die, and the difference of ion trap concentration will directly cause the extent of corrosion of connected metallic copper. In the production process of reality, owing to metal interconnect structure is often connected with multiple different device, therefore, it is difficult to directly study the impact on metallic corrosion by cmp condition.
Chinese patent (CN100592960C) discloses a kind of method reducing wafer in chemomechanical copper grinding technique and being corroded, comprise: after wafer is polished and wafer be put back into grinding head clean vacuum device used before, wait and transfer to washing unit device from grinding plant, open grinding head on grinding plant clean vacuum device used in water jet, in order to wash the lapping liquid sticking on wafer.
Although above-mentioned patent decreases the infection of chemical mechanical milling tech for wafer to a certain extent, but to be not the condition by cmp reduce metallic corrosion for it, so the method for this patent has certain limitation for the generation reducing metallic corrosion situation.
Summary of the invention
In view of the above problems, the present invention provides a kind of and observes in chemical mechanical milling tech the method to metallic corrosion situation.
The technical scheme that technical solution problem of the present invention adopts is:
Observing the method to metallic corrosion situation in chemical mechanical milling tech, be applied in the different semiconductor device structure of ion trap concentration, wherein, described method comprises:
The cutting groove of a wafer arranges some the ion traps that ionic species is identical and ionic concn is different;
The metal wire formed after connecting two cmps by two contact holes above ion trap described in each;
The order that ion trap described in each is successively decreased according to the distance between described metal wire is arranged;
By microscope, described metal wire surface is observed.
Described method, wherein, P type trap and the N-type trap that described ion trap comprises a P type trap zone and is formed in this P type trap zone.
Described method, wherein, is isolated by insulating material between described contact hole.
Described method, wherein, the concrete grammar forming two described metal wires is:
A layer insulating is prepared at the upper surface of described contact hole and described insulating material;
All it is formed with an opening being arranged in the insulation layer above contact hole described in each;
Preparation layer of metal layer covers opening described in each and the upper surface of described insulation layer;
Described metal level is carried out cmp, forms two described metal wires.
Described method, wherein, the material of described metal level is copper.
Described method, wherein, two described contact holes lay respectively at the top of described P type trap and described N-type trap.
Described method, wherein, prepares described metal level by electroplating technique method.
Described method, wherein, adopts electron microscope to be observed on described metal wire surface.
Technique scheme tool has the following advantages or useful effect:
The present invention is by being placed on the cutting groove of wafer by the ion trap structure of different ions concentration, and adopt electron microscope directly to observe the interconnection structure formed when different chemical mechanical milling tech, can directly find the corrosion condition of different distance metal wire in the ion trap of different ions concentration, and the corrosion distribution situation of a complete wafer can be obtained by observing the different positions of wafer, and then it is convenient to technique be carried out fast and effective optimization.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully. But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is the cross-sectional view of the inventive method embodiment intermediate ion trap;
Fig. 2 is the cross-sectional view after forming contact hole in the inventive method embodiment in ion trap;
Fig. 3 is the cross-sectional view after forming opening in the inventive method embodiment;
Fig. 4 is cross-sectional view after covering metal copper in the inventive method embodiment;
Fig. 5 is the cross-sectional view after carrying out cmp in the inventive method embodiment;
Fig. 6 is the plan structure schematic diagram of the ion trap structure in the inventive method embodiment with N1 concentration;
Fig. 7 is the plan structure schematic diagram of the ion trap structure in the inventive method embodiment with N2 concentration;
Fig. 8 is the plan structure schematic diagram of the ion trap structure in the inventive method embodiment with N3 concentration.
Embodiment
The present invention provides a kind of and observes in chemical mechanical milling tech the method to metallic corrosion situation, can be applicable to technology node and is 90nm, 65/55nm, 45/40nm, 32/28nm, is more than or equal to 130nm and is less than or equal in the technique of 22nm; And it is applied in following technology platform: Logic, Memory, RF, HV, Analog/Power, MEMS, CIS, Flash, eFlash.
The core concept of the present invention be to provide some analyze with ion trap and by the metal interconnect structure of contact hole connection, the kind of control ion trap intermediate ion and concentration, and distance between two metal wires arranged side by side in control metal interconnect structure, successively decrease according to a certain percentage based on metal minor increment on chip and sort, form some different ion trap structure. By the metal interconnect structure in these ion trap structure being carried out the observation of electron microscope, the region that transition metal is corroded can be observed, corresponding ion trap situation just can be grasped in the region corroded by these transition metal, thus grasps various processing condition to the corrosion condition of metallic copper in different ions trap concentration.
Below in conjunction with specific embodiments and the drawings, the inventive method is described in detail.
First, some the ion traps that ionic species is identical and ionic concn is different are provided, the kind of ion trap should be identical with the ion trap kind in product device, and as shown in Figure 1, ion trap in the present embodiment comprises a P trap and is positioned at a P trap and a N trap of this P trap inner upper. Unfilled contact hole is formed at the P trap and N trap surface that are positioned at P trap inner upper, isolate with insulating material 2 between contact hole, the metallic substance of filled conductive in this contact hole, form contact hole 1, preferred employing copper is filled, and the structure after filling is as shown in Figure 2.
Then, a layer insulating is applied at the body structure surface shown in Fig. 2, and be positioned at the part above contact hole at this insulation layer and form opening 3, to expose the upper surface of the contact hole after filling, as shown in Figure 3, by processing methodes such as plating, metallic copper 4 ' is electroplated in opening, make it to contact with the metallic substance in contact hole, in this process, metallic copper covers the upper surface of opening and insulation layer completely, forms structure as shown in Figure 4.
Afterwards the structure shown in Fig. 4 is carried out cmp, to expose insulation layer part, form two metal wires 4, between these two metal wires, there is certain interval, as shown in Figure 5.
Obtaining organizing ion trap structure by above-mentioned method, the ion trap concentration in these ion trap structure is not identical more, and distance between metal wire in ion trap is also different. As can be seen from figures 6 to 8, wherein, in shown in Fig. 6 group ion trap structure, the ionic concn of each ion trap is identical all to be represented with N1, and the spacing between metal wire reduces from top to bottom successively;As shown in Figure 7, in one group of ion trap structure in Fig. 7, the concentration of each ion trap is also identical, all represents with N2, but the concentration being all greater than the ion trap structure shown in Fig. 6, the spacing between metal wire in the ion trap structure illustrated in the figure 7 also reduces from top to bottom successively; As shown in Figure 8, in one group of ion trap structure in Fig. 8, the concentration of each ion trap is also identical, all represents with N3, but the concentration being all greater than the ion trap structure shown in Fig. 6 and Fig. 7, the spacing between metal wire in the ion trap structure illustrated in fig. 8 also reduces from top to bottom successively.
Then, all ion trap structure with different ions concentration are placed on the cutting groove of wafer, electron microscope is adopted to be observed on the surface of the metal wire in these ion trap structure, thus find the corrosion condition on different distance metal wire surface in the ion trap of different ions concentration, then the corrosion condition of the metal wire of wafer different positions is observed, the corrosion distribution situation of a complete wafer can be obtained, thus effectively and fast process optimization can be carried out in follow-up R & D of complex.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent. Therefore, appending claims should regard whole change and the correction of the true intention containing the present invention and scope as. In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (8)
1. observe the method to metallic corrosion situation in chemical mechanical milling tech, it be applied in the different semiconductor device structure of ion trap concentration, it is characterised in that, described method comprises:
The cutting groove of a wafer arranges some the ion traps that ionic species is identical and ionic concn is different;
The metal wire formed after connecting two cmps by two contact holes above ion trap described in each;
The order that ion trap described in each is successively decreased according to the distance between described metal wire is arranged;
By microscope, described metal wire surface is observed.
2. the method for claim 1, it is characterised in that, P type trap and the N-type trap that described ion trap comprises a P type trap zone and is formed in this P type trap zone.
3. the method for claim 1, it is characterised in that, isolated by insulating material between described contact hole.
4. method as claimed in claim 3, it is characterised in that, the concrete grammar forming two described metal wires is:
A layer insulating is prepared at the upper surface of described contact hole and described insulating material;
All it is formed with an opening being arranged in the insulation layer above contact hole described in each;
Preparation layer of metal layer covers opening described in each and the upper surface of described insulation layer;
Described metal level is carried out cmp, forms two described metal wires.
5. method as claimed in claim 4, it is characterised in that, the material of described metal level is copper.
6. method as claimed in claim 2, it is characterised in that, two described contact holes lay respectively at the top of described P type trap and described N-type trap.
7. method as claimed in claim 4, it is characterised in that, prepare described metal level by electroplating technique method.
8. the method for claim 1, it is characterised in that, adopt electron microscope to be observed on described metal wire surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310630329.1A CN103659574B (en) | 2013-11-29 | 2013-11-29 | Observe the method to metallic corrosion situation in chemical mechanical milling tech |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310630329.1A CN103659574B (en) | 2013-11-29 | 2013-11-29 | Observe the method to metallic corrosion situation in chemical mechanical milling tech |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103659574A CN103659574A (en) | 2014-03-26 |
CN103659574B true CN103659574B (en) | 2016-06-08 |
Family
ID=50298998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310630329.1A Active CN103659574B (en) | 2013-11-29 | 2013-11-29 | Observe the method to metallic corrosion situation in chemical mechanical milling tech |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103659574B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101157186A (en) * | 2006-10-08 | 2008-04-09 | 中芯国际集成电路制造(上海)有限公司 | A method for reducing corrosion of crystal plate in cuprum chemistry mechanical lapping technics |
CN101655427A (en) * | 2009-09-04 | 2010-02-24 | 中国电子科技集团公司第四十六研究所 | Dislocation corrosion detecting method of single germanium wafer |
CN102881646A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for preparing copper metal covering layer |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012638A (en) * | 1998-06-22 | 2000-01-14 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
KR100607408B1 (en) * | 2004-07-21 | 2006-08-02 | 삼성전자주식회사 | Method of appraising of confidence a semiconductor wafer |
-
2013
- 2013-11-29 CN CN201310630329.1A patent/CN103659574B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101157186A (en) * | 2006-10-08 | 2008-04-09 | 中芯国际集成电路制造(上海)有限公司 | A method for reducing corrosion of crystal plate in cuprum chemistry mechanical lapping technics |
CN101655427A (en) * | 2009-09-04 | 2010-02-24 | 中国电子科技集团公司第四十六研究所 | Dislocation corrosion detecting method of single germanium wafer |
CN102881646A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for preparing copper metal covering layer |
Also Published As
Publication number | Publication date |
---|---|
CN103659574A (en) | 2014-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9318465B2 (en) | Methods for forming a semiconductor device package | |
EP2549532B1 (en) | Method of electroplating pads on a semiconductor wafer | |
EP3118892B1 (en) | Laminated semiconductor integrated circuit device | |
US9735090B2 (en) | Integrated circuit devices having through-silicon vias and methods of manufacturing such devices | |
US20150028476A1 (en) | Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs | |
CN102565680B (en) | The failure analysis method of semiconductor device | |
CN104051333A (en) | Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers | |
CN103456685B (en) | Manufacturing method for TSV and first layer re-wiring layer with no need of CMP | |
US8476763B2 (en) | Semiconductor device conductive pattern structures including dummy conductive patterns | |
TWI434373B (en) | Method of bevel trimming a three dimensional semiconductor device, method for forming a three dimensional semiconductor device | |
US9842774B1 (en) | Through substrate via structure for noise reduction | |
CN106449465A (en) | Method for testing single bit on memory chip | |
CN105990295A (en) | Bonding pad structure and manufacturing method thereof | |
CN103659574B (en) | Observe the method to metallic corrosion situation in chemical mechanical milling tech | |
CN102437097A (en) | Novel manufacturing method of contact hole | |
CN104037106B (en) | The method of semiconductor chip failure analysis | |
CN106328546B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
CN108231737A (en) | For reducing the silicon hole with improvement substrate contact of silicon hole capacitance variation | |
US20160005713A1 (en) | Three dimensional stacked multi-chip structure and manufacturing method of the same | |
CN108109996B (en) | Diode-based antistatic adapter plate for integrated circuit and preparation method thereof | |
CN102420173A (en) | Surface treatment method for improving copper interconnection reliability | |
CN104440513A (en) | Silicon wafer machining device and method | |
CN104091792A (en) | Structure for improving TSV adapter plate electromigration reliability and preparation method | |
CN105742196B (en) | Method, semi-conductor device manufacturing method | |
CN106935526B (en) | Polysilicon strain gauge structure and preparation method thereof for interconnecting silicon through holes |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |